GMS87C1408

GMS87C1404 HYNIX | Alldatasheet

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8-BIT SINGLE-CHIP MICROCONTROLLERS GMS87C1404 GMS87C1408 User’s Manual Oct. 1999 Ver 1.0 HYUNDAI MicroElectronics

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 Table of Contents ELECTRICAL CHARACTERISTICS . . .11 Recommended Operating Conditions 11 ANALOG TO DIGITAL CONVERTER . 48 STOP Mode using Internal RCWDT . . 61 Minimizing Current Consumption . . . . 63 DEVICE CONFIGURATION AREA . . . 68

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 1 GMS87C1404 / GMS87C1408 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER 1. OVERVIEW

1.1 Description

The GMS87C1404 and GMS87C1408 are an advanced CMOS 8-bit microcontroller with 4K/8K bytes of EPROM. The HYUNDAI MicroElectronics GMS87C1404 and GMS87C1408 are a powerful microcontroller which provides a highly flexible and cost effective solution to many small applications such as controller for battery charger. The GMS87C1404 and GMS87C1408 provide the following standard features: 4K/8K bytes of EPROM, 192 bytes of RAM, 8-bit timer/counter, 8- bit A/D converter, 10-bit high speed PWM output, programmable buzzer driving port, 8-bit serial communication port, on- chip oscillator and clock circuitry. In addition, the GMS87C1404 and GMS87C1408 supports power saving modes to reduce power consumption.

1.2 Features

• 4K/8K Bytes On-chip Program Memory (OTP)
• 192 Bytes of On-chip Data RAM (Included stack memory)
• Instruction Cycle Time: - 250nS at 8MHz
• 23 Programmable I/O pins (LED direct driving can be source and sink)
• 2.5V to 5.5V Wide Operating Range
• One 8-bit A/D Converter
• One 8-bit Basic Interval Timer
• Four 8-bit Timer / Counters
• Two 10-bit High Speed PWM Outputs
• Watchdog timer (can be operate with internal RC-oscillation)
• One 8-bit Serial Peripheral Interface
• Twelve Interrupt sources - External input: 4 - A/D Conversion: 1 - Serial Peripheral Interface: 1 - Timer: 6
• One Programmable Buzzer Driving port - 500Hz ~ 130kHz
• Oscillator Type - Crystal - Ceramic Resonator
• Noise Immunity Circuit - Power Fail Processor
• P o w e r D o w n M o d e - STOP mode - Wake-up Timer mode

1.3 Development Tools

The GMS87C1404 and GMS87C1408 are supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Dr TM . Device name ROM Size RAM Size Package GMS87C1404 4K bytes 192bytes 28 SKDIP or SOP GMS87C1408 8K bytes 192bytes 28 SKDIP or SOP In Circuit Emulators CHOICE-Dr. Assembler HME Macro Assembler OTP Writer Dr. Writer

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 2 Oct. 1999 Ver 1.0 2. BLOCK DIAGRAM ALU Accumulator Stack Pointer Interrupt Controller Data Memory 8-bit Converter A/D 8-bit Counter Timer/ Program Memory Data Table PC 8-bit Basic Timer Interval Watch-dog Timer Instruction RA RB RC Buzzer Driver PSW System controller Timing generator System Clock Controller Clock Generator RESET Xin Xout RA0 / EC0 RA1 / AN1 RA2 / AN2 RA3 / AN3 RA4 / AN4 RA5 / AN5 RA6 / AN6 RA7 / AN7 RB0 / AN0 / Avref RB1 / BUZ RB2 / INT0 RB3 / INT1 RB4 / CMP0 / PWM0 RC3 / SRDY RC4 / SCK VDD VSS Power Supply Decoder High PWM Speed RB5 / CMP1 / PWM1 RB6 / EC1 RB7 / TMR2OV RC5 / SIN RC6 / SOUT RD RD0 / INT2 RD1 / INT3 RD2 SPI

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 3 3. PIN ASSIGNMENT RA3 / AN3 RA2 / AN2 RA1 / AN1 RA0 / EC0 RD1 / INT3 RD0 / INT2 V SS RESET Xout Xin AN4 / RA4 AN5 / RA5 AN6 / RA6 AN7 / RA7 V DD AN0 / AVref / RB0 BUZ / RB1 INT0 / RB2 INT1 / RB3 PWM0 / COMP0 / RB4

28 SKINNY DIP

V SS RESET Xout Xin AN4 / RA4 AN5 / RA5 AN6 / RA6 AN7 / RA7 V DD AN0 / AVref / RB0 BUZ / RB1 INT0 / RB2 INT1 / RB3 PWM0 / COMP0 / RB4

28 SOP

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 4 Oct. 1999 Ver 1.0 4. PACKAGE DIAGRAM 1.375 0.015 0.045 TYP 0.10 TYP 0.300 0.300 0.014 0 ~ 15° MAX 0.180 MIN 0.0200.120 0.292 0.398 0.713 0.104 0.0138 TYP 0.050 0.004 0.009 0 ~ 8° 0.016 unit: inch MAX MIN 1.355 0.021 0.140 0.055 0.008 0.275 0.419 0.299 0.697 0.093 0.020 0.042 0.0125 0.0118

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 5 5. PIN FUNCTION V DD : Supply voltage. V SS: Circuit ground. RESET : Reset the MCU. X IN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. X OUT : Output from the inverting oscillator amplifier. RA0~RA7 : RA is an 8-bit, CMOS, bidirectional I/O port. RA pins can be used as outputs or inputs according to “1” or “0” written the their Port Direction Register(RAIO). In addition, RA serves the functions of the various special features in Table 5-1 . RB0~RB7 : RB is a 8-bit, CMOS, bidirectional I/O port. RB pins can be used as outputs or inputs according to “1” or “0” written the their Port Direction Register(RBIO). RB serves the functions of the various following special features in Table 5-2 RC3~RC6 : RC is a 4-bit, CMOS, bidirectional I/O port. RC pins can be used as outputs or inputs according to “1” or “0” written the their Port Direction Register(RCIO). RC serves the functions of the serial interface following special features in Table 5-3 . RD0~RD2 : RD is a 3-bit, CMOS, bidirectional I/O port. RC pins can be used as outputs or inputs according to “1” or “0” written the their Port Direction Register(RDIO). RD serves the functions of the external interrupt following special features in Table 5-4 Port pin Alternate function RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 EC0 ( Event Counter Input Source ) AN1 ( Analog Input Port 1 ) AN2 ( Analog Input Port 2 ) AN3 ( Analog Input Port 3 ) AN4 ( Analog Input Port 4 ) AN5 ( Analog Input Port 5 ) AN6 ( Analog Input Port 6 ) AN7 ( Analog Input Port 7 ) Table 5-1 RA Port Port pin Alternate function RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 AN0 ( Analog Input Port 0 ) AVref ( External Analog Reference Pin ) BUZ ( Buzzer Driving Output Port ) INT0 ( External Interrupt Input Port 0 ) INT1 ( External Interrupt Input Port 1 ) PWM0 (PWM0 Output) COMP0 (Timer1 Compare Output) PWM1 (PWM1 Output) COMP1 (Timer3 Compare Output) EC1 (Event Counter Input Source) TMR2OV (Timer2 Overflow Output) Table 5-2 RB Port Port pin Alternate function RC3 RC4 RC5 RC6 SRDYIN (SPI Ready Input) SRDYOUT (SPI Ready Output) SCKI (SPI CLK Input) SCKO (SPI CLK Output) SIN (SPI Serial Data Input) SOUT (SPI Serial Data Output) Table 5-3 RC Port Port pin Alternate function RD0 RD1 RD2 INT2 (External Interrupt Input Port 2) INT3 (External Interrupt Input Port 3) Table 5-4 RD Port

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 6 Oct. 1999 Ver 1.0 PIN NAME Pin No. In/Out Function VDD 5 - Supply voltage VSS 22 - Circuit ground RESET 21 I Reset signal input XIN 19 I XOUT 20 O RA0 (EC0) 25 I/O (Input) 8-bit general I/O ports External Event Counter input 0 RA1 (AN1) 26 I/O (Input) Analog Input Port 1 RA2 (AN2) 27 I/O (Input) Analog Input Port 2 RA3 (AN3) 28 I/O (Input) Analog Input Port 3 RA4 (AN4) 1 I/O (Input) Analog Input Port 4 RA5 (AN5) 2 I/O (Input) Analog Input Port 5 RA6 (AN6) 3 I/O (Input) Analog Input Port 6 RA7 (AN7) 4 I/O (Input) Analog Input Port 7 RB0 (AVref/AN0) 6 I/O (Input) 8-bit general I/O ports Analog Input Port 0 / Analog Reference RB1 (INT0) 7 I/O (Input) External Interrupt Input 0 RB2 (INT1) 8 I/O (Input) External Interrupt Input 1 RB3 (BUZ) 9 I/O (Output) Buzzer Driving Output RB4 (PWM0/COMP0) 10 I/O (Output/Output) PWM0 Output or Timer1 Compare Output RB5 (PWM1/COMP1) 11 I/O (Output/Output) PWM1 Output or Timer3 Compare Output RB6 (EC1) 12 I/O (Output/Output) External Event Counter input 1 RB7 (TMR2OV) 13 I/O (Output/Output) Timer2 Overflow Output RC3 (SRDYIN /SRDYOUT )1 4 I/O (Input/Output) 4-bit general I/O ports SPI READY Input/Output RC4 (SCK) 15 I/O (Input/Output) SPI CLK Input/Output RC5 (SIN) 16 I/O (Input) SPI DATA Input RC6 (SOUT) 17 I/O (Output) SPI DATA Output RD0 (INT2) 23 I/O (Input) 3-bit general I/O ports External Interrupt Input 2 RD1 (INT3) 24 I/O (Input) External Interrupt Input 3 RD2 18 I/O Table 5-5 Pin Description

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 7 6. PORT STRUCTURES

• RESET
• Xin, Xout
• RA0/EC0, RB6/EC1 VSS Internal RESET VSS Xout Xin STOP To System CLK VDD Data Bus Data Bus Data Bus Data Reg. Direction Reg. Read EC0 EC1

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 8 Oct. 1999 Ver 1.0

• RA1/AN1 ~ RA7/AN7
• RB0 / AN0 / AVref VDD VSS Data Bus Data Bus Data Bus Read To A/D Converter Analog Input Mode (ANSEL7 ~ 1) Analog CH. Selection (ADCM.4 ~ 2) Data Reg. Direction Reg. VDD VSS Data Bus Data Bus Data Bus Read To A/D Converter Analog Input Mode (ANSEL0) Analog CH0 Selection (ADCM.4 ~ 2) AVREFS AVREFS Internal VDD To Vref of A/D Data Reg. Direction Reg.

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 9

• RB1/BUZ, RB4/PWM0/COMP0, RB5/PWM1/COMP1, RB7/TMR2OV, RC6/SOUT
• RB2/INT0, RB3/INT1, RD0/INT2, RD1/INT3
• R D 2 VDD VSS Data Bus Data Bus Data Bus Read Function Select PWM/COMP BUZ,TMR2OV,SOUT Data Reg. Direction Reg. VDD VSS Data Bus Data Bus Data Bus Read Function Select Pull-up Select INT0, INT1 Schmitt Trigger Weak Pull-up Data Reg. Direction Reg. INT2, INT3 VDD VSS Data Bus Data Bus Data Bus Read Data Reg. Direction Reg.

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 10 Oct. 1999 Ver 1.0

• RC5/SIN
• RC3 / SRDYIN / SRDYOUT , RC4 / SCKIN / SCKOUT VDD VSS Data Bus Data Bus Data Bus Read Function Select Schmitt Trigger Data Reg. Direction Reg. SIN VDD VSS Data Bus Data Bus Function Select SRDYOUT SCKOUT Data Reg. Direction Reg. Data Bus Read Schmitt TriggerSCKIN SRDYIN

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 11 7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Voltage on any pin with respect to Ground (VSS) Maximum output current sourced by (IOH per I/O Pin) Note: Stresses above those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional op- eration of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

7.2 Recommended Operating Conditions

7.3 A/D Converter Characteristics

(TA =25°C, VSS=0V, VDD =5.12V @ fXIN =8MHz, VDD =3.072V @ fXIN =4MHz) Parameter Symbol Condition Specifications Unit Min. Max. Supply Voltage VDD fXIN=8MHz 4.5 5.5 V fXIN=4.2MHz 2.5 5.5 V Operating Frequency fXIN VDD =4.5~5.5V 18 M H z VDD =2.5~5.5V 1 4.2 kHz Operating Temperature TOPR -20 85 °C Parameter Symbol Condition Specifications Unit Min. Typ. Max. Analog Input Voltage Range VAIN AVREFS=0 VSS - VDD V AVREFS=1 VSS - VREF Analog Power Supply Input Voltage Range VREF AVREFS=1 3 - VDD V Overall Accuracy N ACC - ±1.0 ±1.5 LSB Non-Linearity Error N NLE - ±1.0 ±1.5 LSB Differential Non-Linearity Error N DNLE - ±1.0 ±1.5 LSB Zero Offset Error N ZOE - ±0.5 ±1.5 LSB Full Scale Error N FSE - ±0.25 ±0.5 LSB Gain Error N NLE - ±1.0 ±1.5 LSB Conversion Time TCONV fXIN=8MHz -- 1 0 µS fXIN=4MHz -- 2 0 AV REF Input Current I REF AVREFS=1 - 0.5 1.0 mA

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 12 Oct. 1999 Ver 1.0

7.4 DC Electrical Characteristics

(TA =-20~85°C, VDD =2.5~5.5V, V SS=0V), Parameter Symbol Pin Condition Specifications Unit Min. Typ. Max. Input High Voltage VIH1 XIN, RESET 0.9 VDD - VDD VVIH2 Hysteresis Input1 0.8 VDD - VDD VIH3 Normal Input 0.7 VDD - VDD Input Low Voltage VIL1 XIN, RESET 0- 0.1 VDD VVIL2 Hysteresis Input1 0- 0.2 VDD VIL3 Normal Input 0 - 0.3 VDD Output High Voltage VOH All Output Port VDD =5V, IOH =-5mA V DD -1 -- V Output Low Voltage VOL All Output Port VDD =5V, IOL =10mA - -1 V Input Pull-up CurrentIP RB2, RB3, RD0, RD1 VDD =5V -550 -420 -200 µA Input High Leakage Current IIH1 All Pins (except XIN)V DD =5V --5 µA IIH2 XIN VDD =5V -- 1 5 µA Input Low Leakage Current IIL1 All Pins (except XIN)V DD =5V -5 - - µA IIL2 XIN VDD =5V -15 - - µA Hysteresis | VT | Hysteresis Input1 VDD =5V 0.5 - - V PFD Voltage VPFD1 VDD PFDM=0 2.5 3.0 3.5 V VPFD2 VDD PFDM =1 2.0 2.5 3.0 Internal RC WDT Period TRCWDT VDD =5V 40 120 µS VDD =3V 95 280 Operating Current IDD VDD VDD =5.5V, fXIN=8MHz -56 mA VDD =3.0V, fXIN=4MHz -23 Wake-up Timer Mode Current IWKUP VDD VDD =5.5V, fXIN=8MHz -12 mA VDD =3.0V, fXIN=4MHz -0 . 51 RCWDT Mode Current at STOP Mode I RCWDT VDD VDD =5.5V, fXIN=8MHz -- 2 0 0 µA VDD =3.0V, fXIN=4MHz -- 1 0 0 Stop Mode Current ISTOP VDD VDD =5.5V, fXIN=8MHz -0 . 53 µA VDD =3.0V, fXIN=4MHz -0 . 21 1. Hysteresis Input: RA0, RB2, RB3, RB6, RC3, RC4, RC5, RD0, RD1

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 13

7.5 AC Characteristics

(TA =-20~+85°C, VDD =5V ±10% , V SS=0V) Figure 7-1 Timing Chart Parameter Symbol Pins Specifications Unit Min. Typ. Max. Operating Frequency fCP XIN 1-8 M H z External Clock Pulse Width tCPW XIN 80 - - nS External Clock Transition TimetRCP, tFCP XIN -- 2 0 n S Oscillation Stabilizing Time tST XIN, XOUT -- 2 0 m S External Input Pulse Width tEPW INT0, INT1, INT2, INT3 EC0, EC1 2-- tSYS External Input Pulse Transi- tion Time tREP,tFEP INT0, INT1, INT2, INT3 EC0, EC1 -- 2 0 n S RESET Input Width tRST RESET 8-- tSYS tRCP tFCP XIN INT0, INT1 INT2, 0.5V VDD -0.5V 0.2VDD RESET tREP tFEP 0.2VDD 0.8VDD EC0, tRST tEPWtEPW 1/fCP tCPW tCPW tSYS INT3 EC1

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 14 Oct. 1999 Ver 1.0

7.6 Typical Characteristics

This graphs and tables provided in this section are for de- sign guidance only and are not tested or guaranteed. In some graphs or tables the data presented are out- side specified operating range (e.g. outside specified V DD range). This is for information only and devices are guaranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean − 3σ) respectively where σ is standard deviation /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 Ta= 25°C Ta=25°C IDD −VDD (mA) IDD 23 45 6 VDD (V) Normal Operation (MHz) fXIN 23 45 6 VDD (V) Operating Area fXIN = 8MHz 4MHz IWKUP −VDD 2.0 1.5 1.0 0.5 (mA) IDD 23 45 6 VDD (V) Wake-up Timer Mode IRCWDT −VDD (µA) IDD 23 45 6 VDD (V) RC-WDT in Stop Mode Ta=25°C fXIN = 8MHz 4MHz fXIN = 8MHz 4MHz Ta=25°C ISTOP −VDD 0.8 0.6 0.4 0.2 (µA) IDD 23 45 6 VDD (V) STOP Mode fXIN = 8MHz -25°C 85°C 25°C

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 15 IOL −VOL , VDD =5V (mA) IOL VOL (V) IOH −VOH , VDD =5V -20 -15 -10 (mA) IOH 23 45 6 VOH (V)12 34 5 fXIN=4MHz VDD −VIH1 (V) VIH1 23 45 6 VDD (V) VDD −VIH2 (V) VIH2 23 45 6 VDD (V) Ta=25°C fXIN =4kHz Ta=25°C XIN, RESET Hysteresis input -25°C 85°C 25°C -25°C 85°C 25°C VDD −VIH3 (V) VIH3 23 45 6 VDD (V) fXIN =4kHz Ta=25°C Normal input fXIN=4MHz VDD −VIL1 (V) VIL1 23 45 6 VDD (V) VDD −VIL2 (V) VIL2 23 45 6 VDD (V) Ta=25°C fXIN =4kHz Ta=25°C XIN, RESET Hysteresis input VDD −VIL3 (V) VIL3 23 45 6 VDD (V) fXIN =4kHz Ta=25°C Normal input

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 16 Oct. 1999 Ver 1.0 8. MEMORY ORGANIZATION The GMS87C1404 and GMS87C1408 have separate ad- dress spaces for Program memory and Data Memory. Pro- gram memory can only be read, not written to. It can be up to 4K /8K bytes of Program memory. Data memory can be read and written to up to 192 bytes including the stack area.

8.1 Registers

This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register. Figure 8-1 Configuration of Registers Accumulator: The Accumulator is the 8-bit general pur- pose register, used for data operation such as transfer, tem- porary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below. Figure 8-2 Configuration of YA 16-bit Register X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the spec- ified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have in- crement, decrement, comparison and data transfer func- tions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed (save or restore). Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 00 H to BFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initial- ization routine. Normally, the initial value of “BFH ” is used. Note: The Stack Pointer must be initialized by software be- cause its value is undefined after RESET. Example: To initialize the SP LDX #0BFH TXSP ; SP ← BFH Program Counter : The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset rou- tine address (PC H :0FFH , PCL:0FEH ). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3 . It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is “0” and is cleared by any other result. A ACCUMULATOR X REGISTER Y REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD X Y SP PCLPCH PSW Two 8-bit Registers can be used as a “YA” 16-bit Register Y A Y A SP0 Stack Address (000H ~ 0BFH ) 15 0 87 Hardware fixed

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 17 Figure 8-3 PSW (Program Status Word) Register [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All inter- rupts are disabled when cleared to “0”. This flag immedi- ately becomes “0” when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector ad- dress. [Overflow flag V] This flag is set to “1” when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction ex- ceeds +127(7F H ) or -128(80H ). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the re- sult of a data or arithmetic operation. When the BIT in- struction is executed, bit 7 of memory is copied to this flag. N NEGATIVE FLAG V - B H I Z C MSB LSB RESET VALUE: 00 HPSW OVERFLOW FLAG BRK FLAG CARRY FLAG RECEIVES ZERO FLAG INTERRUPT ENABLE FLAG CARRY OUT HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 18 Oct. 1999 Ver 1.0

8.2 Program Memory

A 16-bit program counter is capable of addressing up to 64K bytes, but these devices have 4K/8K bytes program memory space only physically implemented. Accessing a location above FFFF H will cause a wrap-around to 0000H . Figure 8-4 , shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFE H and FFFFH as shown in Figure 8-5 . As shown in Figure 8-4 , each area is assigned a fixed lo- cation in Program Memory. Program Memory area con- tains the user program. Figure 8-4 Program Memory Map Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL in- stead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0 H for TCALL15, 0FFC2 H for TCALL14, etc., as shown in Figure 8-6 . Example: Usage of TCALL The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to loca- tion 0FFFA H . The interrupt service locations spaces 2-byte interval: 0FFF8H and 0FFF9H for External Interrupt 1, 0FFFA H and 0FFFBH for External Interrupt 0, etc. As for the area from 0FF00H to 0FFFFH , if any area of them is not going to be used, its service location is avail- able as general purpose Program Memory. Figure 8-5 Interrupt Vector Area PROGRAM MEMORY TCALL AREA INTERRUPT VECTOR AREA E000H FEFFH FF00H FFC0H FFDFH FFE0H FFFFH PCALL AREA F000H GMS87C1404 GMS87C1408 LDA #5 TCALL 0FH ;1BYTE INSTRUCTION :; INSTEAD OF 3 BYTES :; NORMAL CALL ;TABLE CALL ROUTINE FUNC_A: LDA LRG0 RET FUNC_B: LDA LRG1 RET ;TABLE CALL ADD. AREA ORG 0FFC0H ; TCALL ADDRESS AREA DW FUNC_A DW FUNC_B 0FFE0 H Address Vector Area Memory EA EC EE FA FC FE Serial Peripheral Interface Interrupt Vector Area Basic Interval Interrupt Vector Area A/D Converter Interrupt Vector Area Timer/Counter 3 Interrupt Vector Area Timer/Counter 2 Interrupt Vector Area External Interrupt 2 Vector Area Timer/Counter 1 Interrupt Vector Area Timer/Counter 0 Interrupt Vector Area External Interrupt 0 Vector Area RESET Vector Area External Interrupt 1 Vector Area External Interrupt 3 Vector Area Watchdog Timer Interrupt Vector Area “-” means reserved area. NOTE:

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 19 Figure 8-6 PCALL and TCALL Memory Area PCALL → → → → rel 4F35 PCALL 35H TCALL → → → → n 4A TCALL 4 0FFC0 H Address Program Memory 0FF00 H Address PCALL Area Memory 0FFFF H PCALL Area (256 Bytes) * means that the BRK software interrupt is using same address with TCALL0. NOTE: TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK * CA CB CC CD CE CF DA DB DC DD DE DF ~~ ~ NEXT 0FF35H 0FF00H 0FFFFH 11111111 11010110 01001010 PC: FH FH D H 6H ~~ ~ 250FFD6H 0FF00H 0FFFFH NEXT 0FFD7H 0F125H Reverse

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 20 Oct. 1999 Ver 1.0 Example: The usage software example of Vector address and the initialize part. ORG 0FFE0H DW NOT_USED ; (0FFEO) DW NOT_USED ; (0FFE2) DW SPI_INT ; (0FFE4) Serial Peripheral Interface DW BIT_INT ; (0FFE6) Basic Interval Timer DW WDT_INT ; (0FFE8) Watchdog Timer DW AD_INT ; (0FFEA) A/D DW TMR3_INT ; (0FFEC) Timer-3 DW TMR2_INT ; (0FFEE) Timer-2 DW INT3 ; (0FFF0) Int.3 DW INT2 ; (0FFF2) Int.2 DW TMR1_INT ; (0FFF4) Timer-1 DW TMR0_INT ; (0FFF6) Timer-0 DW INT1 ; (0FFF8) Int.1 DW INT0 ; (0FFFA) Int.0 DW NOT_USED ; (0FFFC) DW RESET ; (0FFFE) Reset ORG 0F000H ; MAIN PROGRAM * RESET: DI ;Disable All Interrupts LDX #0 RAM_CLR:LDA #0 ;RAM Clear(!0000H->!00BFH) STA {X}+ CMPX #0C0H BNE RAM_CLR LDX #0BFH ;Stack Pointer Initialize TXSP CALL INITIAL ; LDM RA, #0 ;Normal Port A LDM RAIO,#1000_0010B ;Normal Port Direction LDM RB, #0 ;Normal Port B LDM RBIO,#1000_0010B ;Normal Port Direction LDM PFDR,#0 ;Enable Power Fail Detector

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 21

8.3 Data Memory

Figure 8-7 shows the internal Data Memory space availa- ble. Data Memory is divided into two groups, a user RAM (including Stack) and control registers. Figure 8-7 Data Memory Map User Memory The GMS87C1404 and GMS87C1408 has 192 × 8 bits for the user memory (RAM). Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0 H to 0FFH . Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in gen- eral return random data, and write accesses will have an in- determinate effect. More detailed informations of each register are explained in each peripheral section. Note: Write only registers can not be accessed by bit ma- nipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction. Example; To write at CKCTLR LDM CKCTLR,#09H ;Divide ratio ÷16 USER MEMORY CONTROL REGISTERS 0000H 00BFH 00C0H 00FFH PAGE0(including STACK) Address Symbol R/W RESET Value Addressing mode 0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H 0C7H 0CAH 0CBH 0CCH 0CDH RA RAIO RB RBIO RC RCIO RD RDIO RAFUNC RBFUNC PUPSEL RDFUNC R/W R/W R/W R/W R/W R/W R/W W W W W W Undefined 0000_0000 Undefined 00000000 Undefined -000_0--- Undefined ----_-000 0000_0000 0000_0000 ----_0000 ----_--00 byte, bit byte2 byte, bit byte byte, bit byte byte, bit byte byte byte byte byte 0D0H 0D1H 0D1H 0D1H 0D2H 0D3H 0D3H 0D4H 0D4H 0D4H 0D5H TM0 TDR0 CDR0 TM1 TDR1 T1PPR CDR1 T1PDR PWM0HR R/W R W R R/W W W R R R/W W --00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000 ----_0000 byte, bit byte byte byte byte, bit byte byte byte byte byte, bit byte 0D6H 0D7H 0D7H 0D7H 0D8H 0D9H 0D9H 0DAH 0DAH 0DAH 0DBH TM2 TDR2 CDR2 TM3 TDR3 T3PPR CDR3 T3PDR PWM1HR R/W R W R R/W W W R R R/W W --00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000 ----_0000 byte, bit byte byte byte byte, bit byte byte byte byte byte, bit byte 0DEH 0E0H 0E1H BUR SIOM SIOR W R/W R/W 1111_1111 0000_0001 Undefined byte byte, bit byte, bit 0E2H 0E3H 0E4H 0E5H 0E6H 0EAH 0EBH 0ECH 0ECH 0EDH 0EDH 0EFH IENH IENL IRQH IRQL IEDS ADCM ADCR BITR CKCTLR WDTR WDTR PFDR R/W R/W R/W R/W R/W R/W R R W R W R/W 0000_0000 0000_---- 0000_0000 0000_---- 0000_0000 --00_0001 Undefined 0000_0000 -001_0111 0000_0000 0111_1111 ----_-100 byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte byte byte byte, bit Table 8-1 Control Registers

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 22 Oct. 1999 Ver 1.0 Note: Several names are given at same address. Refer to below table. Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the pro- gram counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. 1. “byte, bit” means that register can be addressed by not only bit but byte manipulation instruction. 2. “byte” means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit. Addr. When read When write Timer Mode Capture Mode PWM Mode Timer Mode PWM Mode D1H T0 CDR0 - TDR0 - D3H - TDR1 T1PPR D4H T1 CDR1 T1PDR - T1PDR D7H T2 CDR2 - TDR2 - D9H - TDR3 T3PPR DAH T3 CDR3 T3PDR - T3PDR ECH BITR CKCTLR Table 8-2 Various Register Name in Same Address

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 23 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C0H RA RA Port Data Register C1H RAIO RA Port Direction Register C2H RB RB Port Data Register C3H RBIO RB Port Direction Register C4H RC RC Port Data Register C5H RCIO RC Port Direction Register C6H RD RD Port Data Register C7H RDIO RD Port Direction Register CAH RAFUNC ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 CBH RBFUNC TMR2OV EC1I PWM1O PWM0O INT1I INT0I BUZO AVREFS CCH PUPSEL - - - - PUPSEL3 PUPSEL2 PUPSEL1 PUPSEL0 CDH RDFUNC - - - - - - INT3I INT2I D0H TM0 - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST D1H T0/TDR0/ CDR0 Timer0 Register / Timer0 Data Register / Capture0 Data Register D2H TM1 POL 16BIT PWM0E CAP1 T1CK1 T1CK0 T1CN T1ST D3H TDR1/ T1PPR Timer1 Data Register / PWM0 Period Register D4H T1/CDR1/ T1PDR Timer1 Register / Capture1 Data Register / PWM0 Duty Register D5H PWM0HR PWM0 High Register D6H TM2 - - CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST D7H T2/TDR2/ CDR2 Timer2 Register / Timer2 Data Register / Capture2 Data Register D8H TM3 POL 16BIT PWM1E CAP3 T3CK1 T3CK0 T3CN T3ST D9H TDR3/ T3PPR Timer3 Data Register / PWM1 Period Register DAH T3/CDR3/ T3PDR Timer3 Register / Capture3 Data Register / PWM1Duty Register DBH PWM1HR PWM1 High Register DEH BUR BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0 E0H SIOM POL SRDY SM1 SM0 SCK1 SCK0 SIOST SIOSF E1H SIOR SPI DATA REGISTER E2H IENH INT0E INT1E T0E T1E INT2E INT3E T2E T3E E3H IENL ADE WDTE BITE SPIE - - - - E4H IRQH INT0IF INT1IF T0IF T1IF INT2IF INT3IF T2IF T3IF E5H IRQL ADIF WDTIF BITIF SPIF - - - - E6H IEDS IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0L Table 8-3 Control Registers of GMS87C1408 and GMS87C1404 These registers of shaded area can not be accessed by bit manipulation instruction as “SET1, CLR1”, but should be accessed by register operation instruction as “LDM dp,#imm”.

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 24 Oct. 1999 Ver 1.0 EAH ADCM - - ADEN ADS2 ADS1 ADS0 ADST ADSF EBH ADCR ADC Result Data Register ECH BITR1 Basic Interval Timer Data Register ECH CKCTLR 1 - WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0 EDH WDTR WDTCL 7-bit Watchdog Counter Register EFH PFDR 2 ----- P F D I S P F D M P F D S 1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR. 2.The register PFDR only be implemented on devices, not on In-circuit Emulator. Table 8-3 Control Registers of GMS87C1408 and GMS87C1404 These registers of shaded area can not be accessed by bit manipulation instruction as “SET1, CLR1”, but should be accessed by register operation instruction as “LDM dp,#imm”.

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 25

8.4 Addressing Mode

The GMS87C1404 and GMS87C1408 uses six addressing modes;

• Register addressing
• Immediate addressing
• Direct page addressing
• Absolute addressing
• Indexed addressing
• Register-indirect addressing (1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. (2) Immediate Addressing → → → → #imm In this mode, second byte (operand) is accessed as a data immediately. Example:

0435 ADC #35H

E45535 LDM 35H,#55H (3) Direct Page Addressing → → → → dp In this mode, a address is specified within direct page. Example; C535 LDA 35H ;A ← RAM[35H] (4) Absolute Addressing → → → → !abs Absolute addressing sets corresponding memory data to Data, i.e. second byte(Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example; 0735F0 ADC !0F035H ;A ← ROM[0F035H] A+35H+C → A04 MEMORY E40F100H data ← 55H ~~ ~ data0035H 350F102H 550F101H data 0035H 0F551H data → A ➊~~ ~ ~C50F550H 070F100H ~~ ~ data0F035H F00F102H 350F101H A+data+C → A address: 0F035

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 26 Oct. 1999 Ver 1.0 The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H . 983500 INC !0035H ;A ← RAM[035H] (5) Indexed Addressing X indexed direct page (no offset) → → → → {X} In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15 H D4 LDA {X} ;ACC← RAM[X]. X indexed direct page, auto increment→ → → → {X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; X=35 H DB LDA {X}+ X indexed direct page (8 bit offset) → → → → dp+X This address value is the second byte (Operand) of com- mand plus the data of -register. And it assigns the mem- ory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; X=015H C645 LDA 45H+X 980F100H ~~ ~ data0035H 000F102H 350F101H data+1 → data address: 0035 data 15H 0E550H data → A ~~ ~ data DB 35H data → A ~~ ~ 36H → X data 5AH 0E551H data → A➋ ~~ ~ ~C60E550 H 45H+15H=5AH

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 27 Y indexed direct page (8 bit offset) → → → → dp+Y This address value is the second byte (Operand) of com- mand plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. Y indexed absolute →→→→ !abs+Y Sets the value of 16-bit absolute address plus Y-register data as Memory. This addressing mode can specify mem- ory in whole area. Example; Y=55 H D500FA LDA !0FA00H+Y (6) Indirect Addressing Direct page indirect → → → → [dp] Assigns data address to use for accomplishing command which sets memory data(or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL Example; 3F35 JMP [35H] X indexed indirect → → → → [dp+X] Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plusX-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; X=10 H

1625 ADC [25H+X]

data → A ~~ ~ data0FA55 H 0FA00H+55H=0FA55H FA0F102H 000F101H 0A35H jump to address 0E30AH ~~ ~ 0FA00 H E336H 0E30A H NEXT ~~ ~ 0535H 0E005 H~~ ~ 0FA00 H E036H 0E005 H data ~~ ~ ➌ A + data + C → A 25 + X(10) = 35H➊

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 28 Oct. 1999 Ver 1.0 Y indexed indirect → → → → [dp]+Y Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Di- rect pageplus Y-register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; Y=10 H

1725 ADC [25H]+Y

Absolute indirect → → → → [!abs] The program jumps to address specified by 16-bit absolute address. JMP Example; 1F25E0 JMP [!0C025H] 0525H 0E005 H + Y(10) = 0E015H ~~ ~ 0FA00 H E026H 0E015H data ~~ ~ ➌ A + data + C → A 250E025 H jump to~~ ~ 0FA00 H E70E026 H 0E725H NEXT ~~ ~ ~1F PROGRAM MEMORY address 0E30AH

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 29 9. I/O PORTS The GMS87C1408 and GMS87C1404 has four ports, RA, RB, RC and RD. These ports pins may be multiplexed with an alternate function for the peripheral features on the de- vice. In general, when a initial reset state, all ports are used as a general purpose input port. All pins have data direction registers which can set these ports as output or input. A “1” in the port direction register defines the corresponding port pin as output. Conversely, write “0” to the corresponding bit to specify as an input pin. For example, to use the even numbered bit of RA as output ports and the odd numbered bits as input ports, write “55 H ” to address C1H (RA direction register) during initial setting as shown in Figure 9-1 . Reading data register reads the status of the pins whereas writing to it will write to the port latch. Figure 9-1 Example of port I/O assignment

9.1 RA and RAIO registers

RA is an 8-bit bidirectional I/O port (address C0H ). Each port can be set individually as input and output through the RAIO register (address C1H ). RA7~RA1 ports are multiplexed with Analog Input Port (AN7~AN1) and RA0 port is multiplexed with Event Counter Input Port (EC0) Figure 9-2 Registers of Port RA The control register RAFUNC (address CAH ) controls to select alternate function. After reset, this value is “0”, port may be used as general I/O ports. To select alternate func- tion such as Analog Input or External Event Counter Input, write “1” to the corresponding bit of RAFUNC.Regardless of the direction register RAIO, RAFUNC is selected to use as alternate functions, port pin can be used as a correspond- ing alternate features (RA0/EC0 is controlled by RB- FUNC) I: INPUT PORT WRITE “55H” TO PORT RA DIRECTION REGISTER 0 1 0 1 0 1 0 1 I O I O I O I O RA DATA RB DATA RA DIRECTION RB DIRECTION C0H C1H C2H C3H

76543210 B I T

76543210 P O R T

O: OUTPUT PORT RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 INPUT / OUTPUT DATA 0 : INPUT PORT 1 : OUTPUT PORT DIRECTION SELECT RA Data Register RA ADDRESS : C0H RESET VALUE : Undefined RA Direction Register RAIO ADDRESS : C1H RESET VALUE : 00000000 ANSEL0 RA Function Selection Register RAFUNC ADDRESS : CAH RESET VALUE : 00000000 ANSEL7 ANSEL1ANSEL2ANSEL3ANSEL4ANSEL5ANSEL6 0 : RB0 1 : AN0 0 : RA1 1 : AN1 0 : RA2 1 : AN2 0 : RA3 1 : AN3 0 : RA4 1 : AN4 0 : RA5 1 : AN5 0 : RA6 1 : AN6 0 : RA7 1 : AN7 PORT RAFUNC.7~0 Description RA7/AN7

0 RA7 (Normal I/O Port)

1 AN7 (ADS2~0=111)

0 RA6 (Normal I/O Port)

1 AN6 (ADS2~0=110)

0 RA5 (Normal I/O Port)

1 AN5 (ADS2~0=101)

0 RA4 (Normal I/O Port)

1 AN4 (ADS2~0=100)

0 RA3 (Normal I/O Port)

1 AN3 (ADS2~0=011)

0 RA2 (Normal I/O Port)

1 AN2 (ADS2~0=010)

0 RA1 (Normal I/O Port)

1 AN1 (ADS2~0=001)

1. This port is not an Analog Input port, but Event Counter clock source input port. ECO is controlled by setting TOCK2~0 = 111. The bit RAFUNC.0 (ANSEL0) controls the RB0/AN0/AVref port (Refer to Port RB). RA0 (Normal I/O Port) EC0 (T0CK2~0=111)

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 30 Oct. 1999 Ver 1.0

9.2 RB and RBIO registers

RB is a 5-bit bidirectional I/O port (address C2H ). Each pin can be set individually as input and output through the RBIO register (address C3H ). In addition, Port RB is mul- tiplexed with various special features. The control register RBFUNC (address CB H ) controls to select alternate func- tion. After reset, this value is “0”, port may be used as gen- eral I/O ports. To select alternate function such as External interrupt or Timer compare output, write “1” to the corre- sponding bit of RBFUNC. Figure 9-3 Registers of Port RB Regardless of the direction register RBIO, RBFUNC is se- lected to use as alternate functions, port pin can be used as a corresponding alternate features. RB5 RB4 RB3 RB2 RB1 RB0 INPUT / OUTPUT DATA 0 : INPUT PORT 1 : OUTPUT PORT DIRECTION SELECT RB Data Register RB ADDRESS : C2H RESET VALUE : Undefined RB Direction Register RBIO ADDRESS : C3H RESET VALUE : 00000000 AVREFS RB Function Selection Register RBFUNC ADDRESS : CBH RESET VALUE : 00000000 BUZOINT0IINT1IPWM0O 0 : RB0 when ANSEL0 = 0 1 : AVref 0 : RB1 1 : BUZ Output 0 : RB4 1 : PWM0 Output or 0 : RB2 1 : INT0 0 : RB3 1 : INT1 PUP0 Pull-up Selection Register PUPSEL ADDRESS : CCH RESET VALUE : ----0000 - PUP1-- - 0 : No Pull-up 1 : With Pull-up 0 : No Pull-up 1 : With Pull-up IED0L Interrupt Edge Selection Register IEDS ADDRESS : E6H RESET VALUE : 00000000 IED0HIED1LIED1H External Interrupt Edge Select INT0INT1 00 : Normal I/O port 01 : Falling (1-to-0 transition) 10 : Rising (0-to-1 transition) 11 : Both (Rising & Falling) Compare Output RB0 / INT0 Pull-up RB1 / INT1 Pull-up AN0 when ANSEL0 = 1 RB6RB7 PWM1OTMR2OV EC1I IED2LIED2HIED3LIED3H INT2INT3 0 : RB5 1 : PWM1 Output or Compare Output 0 : RB6 1 : EC1 0 : RB7 1 : TMR2OV PUP2PUP3

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 31 PORT RBFUNC.4~0 Description RB7/ TMR2OV

0 RB7 (Normal I/O Port)

1 Timer2 Overflow Output

0 RB6 (Normal I/O Port)

1 Event Counter 1 Input

0 RB5 (Normal I/O Port)

1 PWM1 Output /

0 RB4 (Normal I/O Port)

1 PWM0 Output /

0 RB3 (Normal I/O Port)

1 External Interrupt Input 1

0 RB2 (Normal I/O Port)

1 External Interrupt Input 0

0 RB1 (Normal I/O Port)

1 Buzzer Output

1. When ANSEL0 = “0”, this port is defined for normal I/O port (RB0). When ANSEL0 = “1” and ADS2~0 = “000”, this port can be used Analog Input Port (AN0). RB0 (Normal I/O Port)/ AN0 (ANSEL0=1) 2. When this bit set to “1”, this port defined for AVref, so it can not be used Analog Input Port AN0 and Normal I/O Port RB0. External Analog Reference Voltage

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 32 Oct. 1999 Ver 1.0

9.3 RC and RCIO registers

RC is an 4-bit bidirectional I/O port (address C4H ). Each pin can be set individually as input and output through the RCIO register (address C5H ). In addition, Port RC is multiplexed with Serial Peripheral Interface (SPI). The control register SIOM (address E0H ) controls to select Serial Peripheral Interface function. After reset, the RCIO register value is “0”, port may be used as general I/O ports. To select Serial Peripheral Inter- face function, write “1” to the corresponding bit of SIOM. Figure 9-4 Registers of Port RC Table 9-1 Serial Communication Functions in RC Port PORT Function SIOM

Description

SRDY SM [1:0] SCK [1:0] RC6/ SOUT RC6 X X:0 X:X RC6 (Normal I/O Port) SOUT X X:1 X:X SPI Serial Data Output RC5/ SIN RC5 X 0:X X:X RC5 (Normal I/O Port) SIN X 1:X X:X SPI Serial Data Input RC4/ SCK RC4 X 0:0 X:X RC4 (Normal I/O Port) SCKO X 0:0 00, 01, 10 SPI Synchronous Clock Output SCKI X 0:0 1:1 SPI Synchronous Clock Input RC3/ SRDY RC3 0 X:X X:X RC3 (Normal I/O Port) SRDYIN 1 X:X 00, 01, 10 SPI Ready Input (Master Mode) SRDYOUT 1 X:X 1:1 SPI Ready Output (Slave Mode) - - - INPUT / OUTPUT DATA 0 : INPUT PORT 1 : OUTPUT PORT DIRECTION SELECT RC Data Register RC ADDRESS : C4H RESET VALUE : Undefined RC Direction Register RCIO ADDRESS : C5H RESET VALUE : -0000--- -RC6 RC5 RC4 RC3

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 33

9.4 RD and RDIO registers

RD is a 3-bit bidirectional I/O port (address C6H ). Each pin can be set individually as input and output through the RDIO register (address C7H ). Figure 9-5 Registers of Port RD In addition, Port RD is multiplexed with external interrupt input function. The control register RDFUNC (address CD H ) controls to select alternate function. After reset, this value is “0”, port may be used as general I/O ports. To se- lect alternate function, write “1” to the corresponding bit of RDFUNC. Regardless of the direction register RDIO, RDFUNC is se- lected to use as external interrupt input function, port pin can be used as a interrupt input feature. RD2 RD1 RD0 INPUT / OUTPUT DATA 0 : INPUT PORT 1 : OUTPUT PORT DIRECTION SELECT RD Data Register RD ADDRESS : C6H RESET VALUE : Undefined RD Direction Register RDIO ADDRESS : C7H RESET VALUE : -----000 INT2I RD Function Selection Register RDFUNC ADDRESS : CDH RESET VALUE : 00000000 INT3I 0 : RD0 1 : INT2 0 : RD1 1 : INT3 PUP0 Pull-up Selection Register PUPSEL ADDRESS : CCH RESET VALUE : ----0000 - PUP1-- - 0 : No Pull-up 1 : With Pull-up 0 : No Pull-up 1 : With Pull-up IED0L Interrupt Edge Selection Register IEDS ADDRESS : E6H RESET VALUE : 00000000 IED0HIED1LIED1H External Interrupt Edge Select INT0INT1 00 : Normal I/O port 01 : Falling (1-to-0 transition) 10 : Rising (0-to-1 transition) 1 1: Both (Rising & Falling) RD0 / INT2 Pull-up RD1 / INT3 Pull-up IED2LIED2HIED3LIED3H INT2INT3 PUP2PUP3

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 34 Oct. 1999 Ver 1.0 10. CLOCK GENERATOR The clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and pe- ripheral hardware. The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator connected to the Xin and Xout pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the Xin pin and open the Xout pin. Figure 10-1 Block Diagram of Clock Pulse Generator

10.1 Oscillation Circuit

X IN and XOUT are the input and output, respectively, a in- verting amplifier which can be set for use as an on-chip os- cillator, as shown in Figure 10-2 . Figure 10-2 Oscillator Connections To drive the device from an external clock source, Xout should be left unconnected while Xin is driven as shown in Figure 10-3 . There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. Oscillation circuit is designed to be used either with a ce- ramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. Figure 10-3 External Clock Connections Note: When using a system clock oscillator, carry out wir- ing in the broken line area in Figure 10-2 to prevent any effects from wiring capacities. - Minimize the wiring length. - Do not allow wiring to intersect with other signal conductors. - Do not allow wiring to come near changing high current. - Set the potential of the grounding position of the oscillator capacitor to that of VSS . Do not ground to any ground pattern where high current is present. - Do not fetch signals from the oscillator. Internal system clock PRESCALER CLOCK PULSE Peripheral clock GENERATOR ÷2048 STOP WAKEUP fxinOSCILLATION CIRCUIT /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 Xout Xin Vss Recommended: C1, C2 = 30pF±10pF for Crystals R1 = 1MΩ Xout Xin Vss OPEN External Clock Source

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 36 Oct. 1999 Ver 1.0 12. TIMER / COUNTER The GMS87C1408 and GMS87C1404 has four Timer/ Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and Timer 1 can be used either the two 8-bit Tim- er/Counter or one 16-bit Timer/Counter by combining them. Also Timer 2 and Timer 3 are same. In this docu- ment, explain Timer 0 and Timer 1 because Timer2 and Timer3 same with Timer 0 and Timer 1. In the “timer” function, the register is increased every in- ternal clock input. Thus, one can think of it as counting in- ternal clock input. Since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the oscillator frequency in Timer0. And Timer1 can use the same clock source too. In addition, Timer1 has more fast clock source (1/1 to 1/8). In the “counter” function, the register is increased in re- sponse to a 0-to-1 (rising edge) transition at its correspond- ing external input pin, EC0(Timer 0) or EC1(Timer 2). In addition the “capture” function, the register is increased in response external interrupt same with timer function. When external interrupt edge input, the count register is captured into capture data register CDRx. Timer1 and Timer 3 are shared with “PWM” function and “Compare output” function It has seven operating modes: “8-bit timer/counter”, “16- bit timer/counter”, “8-bit capture”, “16-bit capture”, “8-bit compare output”, “16-bit compare output” and “10-bit PWM” which are selected by bit in Timer mode register TMx as shown in Figure 12-1 and Table 12-1 . Figure 12-1 Timer Mode Register (TMx, x = 0~3) Timer 0(2) Mode Register TM0(2) ADDRESS : D0H (D6H for TM2) RESET VALUE : --000000- - CAPx TxCK2 TxCK1 TxCK0 TxCN TxST Timer 1(3) Mode Register TM1(3) ADDRESS : D2H (D8H for TM3) RESET VALUE : 00000000POL 16BIT PWMxE CAPx TxCK1 TxCK0 TxCN TxST CAP0 CAP2 Capture mode selection bit. 0 : Disables Capture 1 : Enables Capture T0CN T2CN Continue control bit 0 : Stop counting 1 : Start counting continuously T0CK[2:0] T2CK[2:0] Input clock selection 000 : fxin ÷ 2, 100 : fxin ÷ 128 001 : fxin ÷ 4, 101 : fxin ÷ 512 010 : fxin ÷ 8, 110 : fxin ÷ 2048 011 : fxin ÷ 32, 111 : External Event ( EC0 ) T0ST T2ST Start control bit 0 : Stop counting 1 : Counter register is cleared and start again POL PWM Output Polarity 0 : Duty active low 1 : Duty active high T1CK[2:0] T3CK[2:0] Input clock selection 00 : fxin 10 : fxin ÷ 8 01 : fxin ÷ 2 11 : using the Timer 0 clock 16BIT 16-bit mode selection 0 : 8-bit mode 1 : 16-bit mode T1CN T3CN Continue control bit 0 : Stop counting 1 : Start counting continuously PWM0E PWM1E PWM enable bit 0 : Disables PWM 1 : Enables PWM T1ST T3ST Start control bit 0 : Stop counting 1 : Counter register is cleared and start again CAP1 CAP3 Capture mode selection bit. 0 : Disables Capture 1 : Enables Capture

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 37 12.1 8-bit Timer/Counter Mode The GMS87C1408 and GMS87C1404 has four 8-bit Tim- er/Counters, Timer 0, Timer 1, Timer 2 and Timer 3, as shown in Figure 12-2 . The “timer” or “counter” function is selected by mode reg- isters TMx as shown in Figure 12-1 and Table 12-1 . To use as an 8-bit timer/counter mode, bit CAP0 of TM0 is cleared to “0” and bits 16BIT of TM1 should be cleared to “0”(Table 12-1 ). Figure 12-2 8-bit Timer / Counter Mode 16BIT CAP0 CAP1 PWME T0CK[2:0] T1CK[1:0] PWMO TIMER 0 TIMER1 0 0 0 0 XXX XX 0 8-bit Timer 8-bit Timer 0 0 1 0 111 XX 0 8-bit Event Counter 8-bit Capture 0 1 0 0 XXX XX 1 8-bit Capture 8-bit Compare output 0 X 1 0 1 XXX XX 1 8-bit Timer/Counter 10-bit PWM 1000X X X 11 0 16-bit Timer 10001 1 1 11 0 16-bit Event Counter 1 1 X 0 XXX 11 0 16-bit Capture 1000X X X 11 1 16-bit Compare output Table 12-1 Operating Modes of Timer 0 and Timer 1 1. X: The value “0” or “1” corresponding your operation. ÷ 1 ÷ 2 ÷ 8 TM0 ADDRESS : D0H RESET VALUE : --000000- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST TM1 ADDRESS : D2H RESET VALUE : 00000000POL 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST -- 0 XXXXX X 000 XXXX ÷ 2 ÷ 4 ÷ 128 ÷ 512 ÷ 8 ÷ 32fxin EC0 Edge Detector MUX MUX T0 (8-bit) TDR0 (8-bit) T0IF CLEAR COMPARATOR TIMER 0 INTERRUPT T1 (8-bit) TDR1 (8-bit) T1IF CLEAR COMPARATOR TIMER 1 INTERRUPT T0ST 0 : Stop 1 : Clear and Start T1ST 0 : Stop 1 : Clear and Start T0CN T1CN T0CK[2:0] T1CK[1:0] F/F COMP0 PIN ÷ 2048 X: The value “0” or “1” corresponding your operation.

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 39 12.2 16-bit Timer/Counter Mode The Timer register is being run with 16 bits. A 16-bit timer/ counter register T0, T1 are increased from 0000H until it matches TDR0, TDR1 and then resets to 0000H . The match output generates Timer 0 interrupt not Timer 1 in- terrupt. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK2, T0CK1 and T0SL0. In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1 should be set to “1” respectively. Figure 12-5 16-bit Timer / Counter Mode 12.3 8-bit Compare Output (16-bit) The GMS87C1408 and GMS87C1404 has a function of Timer Compare Output. To pulse out, the timer match can goes to port pin(COMP0) as shown in Figure 12-2 and Fig- ure 12-5 . Thus, pulse out is generated by the timer match. These operation is implemented to pin, RB4/COMP0/ PWM. This pin output the signal having a 50: 50 duty square wave, and output frequency is same as below equation. In this mode, the bit PWMO of RB function register (RB- FUNC) should be set to “1”, and the bit PWME of timer1 mode register (TM1) should be set to “0”. In addition, 16-bit Compare output mode is available, also. 12.4 8-bit Capture Mode The Timer 0 capture mode is set by bit CAP0 of timer mode register TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as shown in Figure 12-6 . As mentioned above, not only Timer 0 but Timer 1 can also be used as a capture mode. The Timer/Counter register is increased in response inter- nal or external input. This counting function is same with normal timer mode, and Timer interrupt is generated when TM0 ADDRESS : D0H RESET VALUE : --000000- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST TM1 ADDRESS : D2H RESET VALUE : 00000000POL 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST -- 0 XXXXX X 10011 XX ÷ 2 ÷ 4 ÷ 128 ÷ 512 ÷ 8 ÷ 32fxin EC0 Edge Detector MUX T1 (8-bit) TDR1 (8-bit) T0IF CLEAR COMPARATOR TIMER 0 INTERRUPT T0 (8-bit) TDR0 (8-bit) T0ST 0 : Stop 1 : Clear and Start T0CN T0CK[2:0] F/F COMP0 PIN ÷ 2048 X: The value “0” or “1” corresponding your operation. /G01/G02/G03/G04 /G09/G0A /G0D/G0D/G09 /G0D/G0D

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 40 Oct. 1999 Ver 1.0 timer register T0 (T1) increases and matches TDR0 (TDR1). This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer. For example, in Figure 12-8 , the pulse width of captured signal is wider than the timer data value (FFH ) over 2 times. When external interrupt is occurred, the captured value (13H ) is more little than wanted value. It can be ob- tained correct value by counting the number of timer over- flow occurrence. Timer/Counter still does the above, but with the added fea- ture that a edge transition at external input INTx pin causes the current value in the Timer x register (T0,T1), to be cap- tured into registers CDRx (CDR0, CDR1), respectively. After captured, Timer x register is cleared and restarts by hardware. It has three transition modes: “falling edge”, “rising edge”, “both edge” which are selected by interrupt edge selection register IEDS (Refer to External interrupt section). In ad- dition, the transition at INTx pin generate an interrupt. Note: The CDRx, TDRx and Tx are in same address. In the capture mode, reading operation is read the CDRx, not Tx because path is opened to the CDRx, and TDRx is only for writing operation. Figure 12-6 8-bit Capture Mode ÷ 1 ÷ 2 ÷ 8 TM0 ADDRESS : D0H RESET VALUE : --000000- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST TM1 ADDRESS : D2H RESET VALUE : 00000000POL 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST -- 1 XXXXX X 001 XXXX ÷ 2 ÷ 4 ÷ 128 ÷ 512 ÷ 8 ÷ 32fxin EC0 Edge Detector MUX MUX T0 (8-bit) CDR0 (8-bit) T0IF CLEAR COMPARATOR TIMER 0 INTERRUPT T0ST 0 : Stop 1 : Clear and Start T0CN T1CN T0CK[2:0] T1CK[1:0] TDR0 (8-bit) INT0IF INT 0 INTERRUPT INT0 T1 (8-bit) CDR1 (8-bit) T1IF CLEAR COMPARATOR TIMER 1 INTERRUPT TDR1 (8-bit) INT1IF INT 1 INTERRUPT INT1 T0ST 0 : Stop 1 : Clear and StartIEDS[1:0] IEDS[3:2] CAPTURE CAPTURE ÷ 2048

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 42 Oct. 1999 Ver 1.0 12.5 16-bit Capture Mode 16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK2, T0CK1 and T0CK0. In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1 should be set to “1” respectively. Figure 12-9 16-bit Capture Mode

12.6 PWM Mode

The GMS87C1408 and GMS87C1404 has a two high speed PWM (Pulse Width Modulation) functions which shared with Timer1 (Timer 3). In this document, it will be explained only PWM0. In PWM mode, pin RB4/COMP0/PWM0 outputs up to a 10-bit resolution PWM output. This pin should be config- ure as a PWM output by setting “1” bit PWM0O in RB- FUNC register. (PWM1 output by setting “1” bit PWM1O in RBFUNC) The period of the PWM output is determined by the T1PPR (PWM0 Period Register) and PWM0HR[3:2] (bit3,2 of PWM0 High Register) and the duty of the PWM output is determined by the T1PDR (PWM0 Duty Regis- ter) and PWM0HR[1:0] (bit1,0 of PWM0 High Register). The user writes the lower 8-bit period value to the T1PPR and the higher 2-bit period value to the PWM0HR[3:2]. And writes duty value to the T1PDR and the PWM0HR[1:0] same way. The T1PDR is configure as a double buffering for glitch- less PWM output. In Figure 12-10 , the duty data is trans- ferred from the master to the slave when the period data matched to the counted value. (i.e. at the beginning of next duty cycle) PWM Period = [PWM0HR[3:2]T1PPR] X Source Clock PWM Duty = [PWM0HR[1:0]T1PDR] X Source Clock The relation of frequency and resolution is in inverse pro- portion. Table 12-2 shows the relation of PWM frequency vs. resolution. TM0 ADDRESS : D0H RESET VALUE : --000000- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST TM1 ADDRESS : D2H RESET VALUE : 00000000POL 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST -- 1 XXXXX X 10 X 11 XX ÷ 2 ÷ 4 ÷ 128 ÷ 512 ÷ 8 ÷ 32fxin EC0 Edge Detector MUX T0 + T1 (16-bit) TDR1 T0IF CLEAR COMPARATOR TIMER 0 INTERRUPT T0ST 0 : Stop 1 : Clear and Start T0CN T0CK[2:0] TDR0 INT0IF INT 0 INTERRUPT INT0 IEDS[1:0] CAPTURE CDR1 CDR0 (8-bit)(8-bit)(8-bit) (8-bit)÷ 2048 X: The value “0” or “1” corresponding your operation.

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 44 Oct. 1999 Ver 1.0 Figure 12-11 Example of PWM at 8MHz Figure 12-12 Example of Changing the Period in Absolute Duty Cycle (@8MHz) fxin PWM ~~~ 01 02 03 04 05 7F 80 81 3FF 02 03 ~~ ~ POL=1 PWM POL=0 Duty Cycle [80H x 125nS = 16uS] Period Cycle [3FFH x 125nS = 127.875uS, 7.8KHz] PWM0HR = 0CH T1PPR = FFH T1PDR = 80H T1CK[1:0] = 00 (fxin) PWM0HR3 PWM0HR2 PWM0HR1 PWM0HR0 T1PPR (8-bit) T1PDR (8-bit) Period Duty

11 F F H

POL=1 Duty Cycle Period Cycle [0EH x 1uS = 14uS, 71KHz] PWM0HR = 00H T1PPR = 0EH T1PDR = 05H T1CK[1:0] = 10 (1uS) 01 02 03 04 05 06 08 09 0B 0C 0D 0E 01 02 03 04 05 06 07 08 09 0A 01 02 03 0407 0A 05 [05H x 1uS = 5uS] Duty Cycle [05H x 1uS = 5uS] Period Cycle [0AH x 1uS = 10uS, 100KHz] Duty Cycle [05H x 1uS = 5uS] Write T1PPR to 0AH Period changed clock

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 45 13. Serial Peripheral Interface The Serial Peripheral Interface (SPI) module is a serial in- terface useful for communicating with other peripheral of microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D con- verters, etc. Figure 13-1 SPI Registers and Block Diagram External Clock SCK[1:0] MSB LSB SOUT SIN SCK Polarity SIOR fxin ÷ 4 fxin ÷ 16 TMR2OV SCK1 SCK0 SM1 SM0 SRDY SM1 SM0 POL Octal Counter SPIF (Interrupt Request) SRDY Q R S SIOST From Control Circuit To Control Circuit SPI Mode Control Register SIOM ADDRESS : E0H RESET VALUE : 00000001POL SRDY SM1 SM0 SCK1 SCK0 SIOST SIOSF POL Serial Clock Polarity Selection bit. 0 : Data Transmission at falling edge (Received data latch at rising edge) 1 : Data Transmission at rising edge (Received data latch at falling edge) SCK[1:0] Serial Clock Selection bits 00 : fxin ÷ 4 01 : fxin ÷ 16 10 : TMR2OV (Overflow of Timer 2) 11 : External Clock SRDY Serial Ready Enable bit 0 : Disable (RC3) 1 : Enable (SRDYIN / SRDYOUT ) SIOST Serial Transmit Start bit 0 : Disable 1 : Start (After one SCK, becomes “0”) SM[1:0] Serial Operation Mode Selection bits 00 : Normal Port (RC4, RC5, RC6) 01 : Transmit Mode (SCK, RC5, SOUT) 10 : Receive Mode (SCK, SIN, RC6) 11 : Transmit & Receive Mode (SCK, SIN, SOUT) SIOSF Serial Transmit Status bit 0 : During Transmission 1 : Finished SPI Data Register SIOR ADDRESS : E1H RESET VALUE : Undefined

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 47 14. Buzzer Output function The buzzer driver consists of 6-bit binary counter, the buzzer register BUR and the clock selector. It generates square-wave which is very wide range frequency (480 Hz~250 KHz at fxin = 4 MHz) by user programmable counter. Pin RB1 is assigned for output port of Buzzer driver by set- ting the bit BUZO of RBFUNC to “1”. The 6-bit buzzer counter is cleared and start the counting by writing signal to the register BUR. It is increased from 00H until it matches 6-bit register BUR. Also, it is cleared by counter overflow and count up to out- put the square wave pulse of duty 50%. The bit 0 to 5 of BUR determines output frequency for buzzer driving. Frequency calculation is following as shown below. The bits BUCK1, BUCK0 of BUR selects the source clock from prescaler output. Figure 14-1 Buzzer Driver /G05/G06/G07 () Oscillator Frequency BUR ADDRESS : DEH RESET VALUE : 11111111BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0 ÷ 64 ÷ 16 ÷ 32 fxin MUX COUNTER (6-bit) BUR (6-bit) F/F COMPARATORBUCK[1:0] RB1/BUZ PIN ÷ 8 Input clock selection 00 : fxin ÷ 8 01 : fxin ÷ 16 10 : fxin ÷ 32 11 : fxin ÷ 64 Buzzer Period Data BUZO [RBFUNC.1] Bit Manipulation Not Available

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 48 Oct. 1999 Ver 1.0 15. ANALOG TO DIGITAL CONVERTER The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/D module has eight analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which gen- erates the result via successive approximation. The analog reference voltage is selected to V DD or AVref by setting of the bit AVREFS in RBFUNC register. If ex- ternal analog reference AVref is selected, the bit ANSEL0 should not be set to “1”, because this pin is used to an an- alog reference of A/D converter. The A/D module has two registers which are the control register ADCM and A/D result register ADCR. The ADCM register, shown in Figure 15-2 , controls the oper- ation of the A/D converter module. The port pins can be configure as analog inputs or digital I/O. To use analog inputs, each port is assigned analog input port by setting the bit ANSEL[7:0] in RAFUNC register. And selected the corresponding channel to be converted by setting ADS[2:0]. The processing of conversion is start when the start bit ADST is set to “1”. After one cycle, it is cleared by hard- ware. The register ADCR contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCR, the A/D conversion status bit ADSF is set to “1”, and the A/D interrupt flag ADIF is set. The block diagram of the A/D module is shown in Figure 15-1 . The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conver- sion is in process. The conversion time takes maximum 10 uS (at fxin=8 MHz). Figure 15-1 A/D Converter Block Diagram RB0/AN0/AVref ANSEL0 (RAFUNC.0) RA1/AN1 ANSEL1 RA2/AN2 ANSEL2 RA3/AN3 ANSEL3 RA4/AN4 ANSEL4 RA5/AN5 ANSEL5 RA6/AN6 ANSEL6 RA7/AN7 ANSEL7 000 001 010 011 100 101 110 111 VDD Pin AVREFS (RBFUNC.0) ADEN S/H Successive Approximation Circuit ADIF Resistor Ladder Circuit ADS[2:0] ADCR(8-bit) Sample & Hold A/D Interrupt ADDRESS : EBH RESET VALUE : Undefined A/D Result Register

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 50 Oct. 1999 Ver 1.0 (3) Pins AN0/RB0 and AN1/RA1 to AN7/RA7 The analog input pins AN0 to AN7 also function as input/ output port (PORT RA and RB0) pins. When A/D conver- sion is performed with any of pins AN0 to AN7 selected, be sure not to execute a PORT input instruction while con- version is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. (4) AVref pin input impedance A series resistor string of approximately 10KΩ is connected be- tween the AVref pin and the VSS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the AVref pin and the VSS pin, and there will be a large reference voltage error.

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 51 16. INTERRUPTS The GMS87C1408 and GMS87C1404 interrupt circuits consist of Interrupt enable register (IENH, IENL), Inter- rupt request flags of IRQH, IRQL, Interrupt Edge Selec- tion Register (IEDS), priority circuit and Master enable flag(“I” flag of PSW). The configuration of interrupt cir- cuit is shown in Figure 16-1 and Interrupt priority is shown in Table 16-1 . The External Interrupts INT0, INT1, INT2 and INT3 can each be transition-activated (1-to-0, 0-to-1 and both transi- tion). The flags that actually generate these interrupts are bit INT0IF, INT1IF, INT2IF and INT3IF in Register IRQH. When an external interrupt is generated, the flag that gen- erated it is cleared by the hardware when the service rou- tine is vectored to only if the interrupt was transition- activated. The Timer 0, Timer 1, Timer 2 and Timer 3 Interrupts are generated by T0IF, T1IF, T2IF and T3IF, which are set by a match in their respective timer/counter register. The AD converter Interrupt is generated by ADIF which is set by finishing the analog to digital conversion. The Watch dog timer Interrupt is generated by WDTIF which set by a match in Watch dog timer register (when the bit WDTON is set to “0”). The Basic Interval Timer Interrupt is gener- ated by BITIF which is set by a overflowing of the Basic Interval Timer Register(BITR). Figure 16-1 Block Diagram of Interrupt Function BIT BITIF WDTIFWDT A/D Converter Timer 1 Timer 0 External Int. 1 External Int. 0 IENH Interrupt Enable Interrupt Enable IRQH IRQL Interrupt Vector Address Generator Internal bus line Register (Lower byte) Internal bus line Register (Higher byte) Release STOP To CPU Interrupt Master Enable Flag I Flag IENL Priority Control I-flag is in PSW, it is cleared by “DI”, set by “EI” instruction.When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by “RETI” instruction, I-flag is set to “1” by hardware. INT0IF INT1IF T0IF T1IF ADIF IEDS Timer 3 Timer 2 External Int. 3 External Int. 2 INT2IF INT3IF T2IF T3IF IEDS SPI SPIF 5

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 52 Oct. 1999 Ver 1.0 The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL) and the interrupt request flags (in IRQH, IRQL) except Power-on reset and software BRK interrupt. Interrupt enable registers are shown in Figure 16-2 . These registers are composed of interrupt enable flags of each in- terrupt source, these flags determines whether an interrupt will be accepted or not. When enable flag is “0”, a corre- sponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once. Figure 16-2 Interrupt Enable Registers and Interrupt Request Registers When an interrupt is occurred, the I-flag is cleared and dis- able any further interrupt, the return address and PSW are pushed into the stack and the PC is vectored to. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt request flag bits. The interrupt request flag bit(s) must be cleared by soft- ware before re-enabling interrupts to avoid recursive inter- rupts. The Interrupt Request flags are able to be read and written. Reset/Interrupt Symbol Priority Vector Addr. Hardware Reset External Interrupt 0 External Interrupt 1 Timer 0 Timer 1 External Interrupt 2 External Interrupt 3 Timer 2 Timer 3 A/D Converter Watch Dog Timer Basic Interval Timer Serial Interface RESET INT0 INT1 Timer 0 Timer 1 INT2 INT3 Timer 2 Timer 3 A/D C WDT BIT SPI FFFE H FFFA H FFF8 H FFF6 H FFF4 H FFF2 H FFF0 H FFEE H FFEC H FFEA H FFE8 H FFE6 H Table 16-1 Interrupt Priority IENH ADDRESS : E2H RESET VALUE : 00000000INT0E INT1E T0E T1E INT2E INT3E T2E T3E Interrupt Enable Register High IENL ADDRESS : E3H RESET VALUE : 0000----ADE WDTE BITE SPIE - - - - Interrupt Enable Register Low IRQH ADDRESS : E4H RESET VALUE : 00000000INT0IF INT1IF T0IF T1IF INT2IF INT3IF T2IF T3IF Interrupt Request Register High IRQL ADDRESS : E5H RESET VALUE : 0000----ADIF WDTIF BITIF SPIF - - - - Interrupt Request Register Low 0 : Disable 1 : Enable Enables or disables the interrupt individually If flag is cleared, the interrupt is disabled. 0 : Not occurred 1 : Interrupt request is occurred Shows the interrupt occurrence

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 53

16.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to “0” by a reset or an in- struction. Interrupt acceptance sequence requires 8 f OSC (2 µs at fXIN =4MHz) after the completion of the current in- struction execution. The interrupt service task is terminat- ed upon execution of an interrupt return instruction [RETI]. Interrupt acceptance 1. The interrupt master enable flag (I-flag) is cleared to “0” to temporarily disable the acceptance of any follow- ing maskable interrupts. When a non-maskable inter- rupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. Interrupt request flag for the interrupt source accepted is cleared to “0”. 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the inter- rupt service program is executed. Figure 16-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction A interrupt request is not accepted until the I-flag is set to “1” even if a requested interrupt has higher priority than that of the current interrupt being serviced. When nested interrupt service is required, the I-flag should be set to “1” by “EI” instruction in the interrupt service program. In this case, acceptable interrupt sources are se- lectively enabled by the individual interrupt enable flags. Saving/Restoring General-purpose Register During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. These registers are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. V.L. System clock Address Bus PC SP SP-1 SP-2 V.H. New PC V.L.Data Bus Not used PCH PCL PSW ADL OP codeADH Instruction Fetch Internal Read Internal Write Interrupt Processing Step Interrupt Service Task ADL and ADH are start addresses of interrupt service routine as vector contents. Basic Interval Timer 012H 0E3H 0FFE6 H 0FFE7 H 0EH 2EH 0E312 H 0E313H Entry Address Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program. Vector Table Address

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 54 Oct. 1999 Ver 1.0 The following method is used to save/restore the general- purpose registers. Example: Register save using push and pop instructions General-purpose register save/restore using push and pop instructions;

16.2 BRK Interrupt

Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distin- guish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 16-4 . Figure 16-4 Execution of BRK/TCALL0

16.3 Multi Interrupt

If two requests of different priority levels are received si- multaneously, the request of higher priority level is ser- viced. If requests of the interrupt are received at the same time simultaneously, an internal polling sequence deter- mines by hardware which request is serviced. However, multiple processing through software for special features is possible. Generally when an interrupt is accept- ed, the I-flag is cleared to disable any further interrupt. But as user sets I-flag in interrupt routine, some further inter- rupt can be serviced even if certain interrupt is in progress. INTxx: PUSH A PUSH X PUSH Y ;SAVE ACC. ;SAVE X REG. ;SAVE Y REG. interrupt processing POP Y POP X POP A RETI ;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return B-FLAG BRK INTERRUPT ROUTINE RETI TCALL0 ROUTINE RET BRK or TCALL0

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 55 Figure 16-5 Execution of Multi Interrupt Example: Even though Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend. TIMER1: PUSH A PUSH X PUSH Y LDM IENH,#80H;Enable INT0 only LDM IENL,#0;Disable other EI ;Enable Interrupt LDM IENH,#0FFH;Enable all interrupts LDM IENL,#0F0H POP Y POP X POP A RETI enable INT0 TIMER 1 service INT0 service Main Program service Occur TIMER1 interrupt Occur INT0 EI disable other enable INT0 enable other In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable “EI” in the TIMER1 routine.

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 56 Oct. 1999 Ver 1.0

16.4 External Interrupt

The external interrupt on INT0, INT1, INT2 and INT3 pins are edge triggered depending on the edge selection register IEDS (address 0E6 H ) as shown in Figure 16-6 . The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. Figure 16-6 External Interrupt Block Diagram Example: To use as an INT0 and INT2 ;** Set port as an input port RB2,RD0 LDM RBIO,#1111_1011B LDM RDIO,#1111_1110B ; Set port as an interrupt port LDM RBFUNC,#04H LDM RDFUNC,#01H ;** Set Falling-edge Detection LDM IEDS,#0001_0001B Response Time The INT0, INT1,INT2 and INT3 edge are latched into INT0IF, INT1IF, INT2IF and INT3IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and con- ditions are right for it to be acknowledged, a hardware sub- routine call to the requested service routine will be the next instruction to be executed. The DIV itself takes twelve cy- cles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. INT0IFINT0 pin INT0 INTERRUPT INT1IFINT1 pin INT1 INTERRUPT INT2IFINT2 pin INT2 INTERRUPT IEDS [0E6H ] edge selection INT3IFINT3 pin INT3 INTERRUPT INT0 edge select Ext. Interrupt Edge Selection IESR ADDRESS : 0E6 H RESET VALUE : 00000000 00 : Int. disable W WWW W W 01 : falling 10 : rising 11 : both INT1 edge selectINT3 edge select 00 : Int. disable 01 : falling 10 : rising 11 : both 00 : Int. disable 01 : falling 10 : rising 11 : both Register WW INT2 edge select 00 : Int. disable 01 : falling 10 : rising 11 : both

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 57 shows interrupt response timings. Figure 16-7 Interrupt Response Timing Diagram Interrupt goes active Interrupt latched Interrupt processing Interrupt routine 8 fOSCmax. 12 fOSC

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 58 Oct. 1999 Ver 1.0 17. WATCHDOG TIMER The purpose of the watchdog timer is to detect the mal- function (runaway) of program due to external noise or other causes and return the operation to the normal condi- tion. The watchdog timer has two types of clock source. The first type is an on-chip RC oscillator which does not require any external components. This RC oscillator is sep- arate from the external oscillator of the Xin pin. It means that the watchdog timer will run, even if the clock on the Xin pin of the device has been stopped, for example, by en- tering the STOP mode. The other type is a prescaled system clock. The watchdog timer consists of 7-bit binary counter and the watchdog timer data register. When the value of 7-bit binary counter is equal to the lower 7 bits of WDTR, the interrupt request flag is generated. This can be used as WDT interrupt or reset the CPU in accordance with the bit WDTON. Note: Because the watchdog timer counter is enabled af- ter clearing Basic Interval Timer, after the bit WD- TON set to “1”, maximum error of timer is depend on prescaler ratio of Basic Interval Timer. The 7-bit binary counter is cleared by setting WDTCL(bit7 of WDTR) and the WDTCL is cleared automatically after 1 machine cycle. The RC oscillated watchdog timer is activated by setting the bit RCWDT as shown below. The RC oscillation period is vary with temperature, VDD and process variations from part to part (approximately, 40~120uS). The following equation shows the RC oscillat- ed watchdog timer time-out. T RCWDT =CLK RC ×28×[WDTR.6~0]+(CLK RC ×28)/2 where, CLK RC = 40~120uS In addition, this watchdog timer can be used as a simple 7- bit timer by interrupt WDTIF. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is as below. T WDT = [WDTR.6~0] ×××× Interval of BIT Figure 17-1 Block Diagram of Watchdog Timer LDM CKCTLR,#3FH ; enable the RC-osc WDT LDM WDTR,#0FFH ; set the WDT period STOP ; enter the STOP mode NOP NOP ; RC-osc WDT running ÷ 8 ÷ 16 ÷ 128 ÷ 256 ÷ 512 ÷ 1024 ÷ 32 ÷ 64 0 MUX fxin BITR (8-bit) BTS[2:0] RCWDT Internal RC OSC Basic Interval Timer Interrupt BTCL Clear Watchdog Timer BITIF 7-bit Counter WDTR (8-bit) OFD WDTCL WDTON Interrupt Request CPU RESET Clock Control Register CKCTLR ADDRESS : ECH RESET VALUE : -0010111- WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0 - 0X1 XXXX Watchdog Timer Register WDTR ADDRESS : EDH RESET VALUE : 01111111WDTCL 7-bit Watchdog Counter Register Overflow Detection Bit Manipulation Not Available Bit Manipulation Not Available

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 59 18. Power Saving Mode For applications where power consumption is a critical factor, device provides two kinds of power saving func- tions, STOP mode and Wake-up Timer mode. The power saving function is activated by execution of STOP instruction after setting the corresponding status (WAKEUP) of CKCTLR. Table 18-1 shows the status of each Power Saving Mode.

18.1 Stop Mode

In the Stop mode, the on-chip oscillator is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port di- rection registers. Oscillator stops and the systems internal operations are all held up.

• The states of the RAM, registers, and latches valid immediately before the system is put in the STOP state are all held.
• The program counter stop the address of the instruction to be executed after the instruction “STOP” which starts the STOP operating mode. The Stop mode is activated by execution of STOP in- struction after clearing the bit WAKEUP of CKCTLR to “0”. (This register should be written by byte opera- tion. If this register is set by bit manipulation instruc- tion, for example “set1” or “clr1” instruction, it may be undesired operation) In the Stop mode of operation, V DD can be reduced to min- imize power consumption. Care must be taken, however, to ensure that VDD is not reduced before the Stop mode is invoked, and that VDD is restored to its normal operating level, before the Stop mode is terminated. The reset should not be activated before VDD is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. Note: After STOP instruction, at least two or more NOP in- struction should be written Ex) LDM CKCTLR,#0000_1110B STOP NOP NOP In the STOP operation, the dissipation of the power asso- ciated with the oscillator and the internal hardware is low- ered; however, the power dissipation associated with the pin interface (depending on the external circuitry and pro- gram) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (V DD /VSS ); however, when the input level gets high- er than the power voltage level (by approximately 0.3 to 0.5V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means. Peripheral STOP Wake-up Timer RAM Retain Retain Control Registers Retain Retain I/O Ports Retain Retain CPU Stop Stop Timer0, Timer2 Stop Operation Oscillation Stop Oscillation Prescaler Stop ÷ 2048 only Entering Condition [WAKEUP] 01 Release Sources RESET, RCWDT, INT0~3, EC0~1, SPI RESET, RCWDT, INT0~3, EC0~1, SPI, TIMER0, TIMER2 Table 18-1 Power Saving Mode

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 61 Figure 18-3 Timing of STOP Mode Release by RESET

18.2 STOP Mode using Internal RCWDT

In the STOP mode using Internal RC-Oscillated Watchdog Timer, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in this mode. The on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port di- rection registers. The Internal RC-Oscillated Watchdog Timer mode is activated by execution of STOP instruction after set- ting the bit RCWDT of CKCTLR to “1”. ( This register should be written by byte operation. If this register is set by bit manipulation instruction, for example “set1” or “clr1” instruction, it may be undesired operation ) Note: After STOP instruction, at least two or more NOP in- struction should be written Ex) LDM WDTR ,#1111_1111B LDM CKCTLR ,#0010_1110B STOP NOP NOP Release the STOP mode using internal RCWDT The exit from STOP mode using Internal RC-Oscillated Watchdog Timer is hardware reset or external interrupt. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. In this case, if the bit WDTON of CKCTLR is set to “0” and the bit WDTE of IENH is set to “1”, the device will exe- cute the watchdog timer interrupt service routine.(Figure 18-4 ) However, if the bit WDTON of CKCTLR is set to “1”, the device will generate the internal RESET signal and execute the reset processing. (Figure 18-5 ) If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.( refer to Figure 18-1 ) When exit from STOP mode using Internal RC-Oscillated Watchdog Timer by external interrupt, the oscillation sta- bilization time is required to normal operation. Figure 18- 4 shows the timing diagram. When release the Internal RC-Oscillated Watchdog Timer mode, the basic interval timer is activated on wake-up. It is increased from 00 H un- til FFH . The count overflow is set to start normal opera- tion. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from STOP mode using internal RC-Oscillat- ed Watchdog Timer is shown in Figure 18-5 . STOP Mode Time can not be control by software Oscillator (XIN pin) ~~~ STOP Instruction Execution Stabilizing Time tST = 64mS @4MHz Internal Clock Internal ~~ ~ RESET RESET

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 62 Oct. 1999 Ver 1.0 Figure 18-4 STOP Mode Releasing by External Interrupt or WDT Interrupt(using RCWDT) Figure 18-5 STOP Mode Releasing by RESET(using RCWDT)

18.3 Wake-up Timer Mode

In the Wake-up Timer mode, the on-chip oscillator is not stopped. Except the Prescaler(only 2048 devided ratio), Timer0 and Timer2, all functions are stopped, but the on- chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. The Wake-up Timer mode is activated by execution of STOP instruction after setting the bit WAKEUP of CKCTLR to “1”. (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example “set1” or “clr1” instruction, it may be undesired operation) STOP Mode Normal Operation Oscillator (XIN pin) /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 ~~~ N+1NN + 2 00 01 FE FF 00 00N-1N-2 ~~~ ~~ ~ Clear Basic Interval TimerSTOP Instruction Execution Normal Operation Stabilizing Time tST > 20mS Internal Clock External Interrupt BIT Counter Internal RC Clock (or WDT Interrupt) Oscillator (XIN pin) ~~ ~ Internal Clock Internal RC Clock Time can not be control by software STOP Instruction Execution Stabilizing Time tST = 64mS @4MHz Internal RESET by WDT RESET RESET STOP Mode

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 63 Note: After STOP instruction, at least two or more NOP in- struction should be written Ex) LDM TDR0,#0FFH LDM TM0,#0001_1011B LDM CKCTLR,#0100_1110B STOP NOP NOP In addition, the clock source of timer0 and timer2 should be selected to 2048 devided ratio. Otherwise, the wake-up function can not work. And the timer0 and timer2 can be operated as 16-bit timer with timer1 and timer3(refer to timer function). The period of wake-up function is varied by setting the timer data register0, TDR0 or timer data register2, TDR2. Release the Wake-up Timer mode The exit from Wake-up Timer mode is hardware reset, Timer0(Timer2) overflow or external interrupt. Reset re- defines all the Control registers but does not change the on- chip RAM. External interrupts and Timer0(Timer2) over- flow allow both on-chip RAM and Control registers to re- tain their values. If I-flag = 1, the normal interrupt response takes place. If I- flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vec- tor to interrupt service routine.(refer to Figure 18-1 ) When exit from Wake-up Timer mode by external inter- rupt or timer0(Timer2) overflow, the oscillation stabilizing time is not required to normal operation. Because this mode do not stop the on-chip oscillator shown as Figure 18-6 . Figure 18-6 Wake-up Timer Mode Releasing by External Interrupt or Timer0(Timer2) Interrupt

18.4 Minimizing Current Consumption

The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. Note: In the STOP operation, the power dissipation asso- ciated with the oscillator and the internal hardware is lowered; however, the power dissipation associat- ed with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD /VSS ); however, when the input level becomes higher than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means. It should be set properly that current flow through port doesn't exist. First conseider the setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn’t flow. But input voltage level should be V SS or VDD . Be careful that if unspecified voltage, i.e. if uncertain voltage level (not VSS or VDD ) is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up re- sistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low. Wake-up Timer Mode Oscillator (XIN pin) /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 STOP Instruction Normal Operation Normal Operation CPU Clock Request Interrupt ~~~ Execution Do not need Stabilizing Time(stop the CPU clock)

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 65 19. RESET The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, while the oscillator running. After reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 19-1 . Internal RAM is not affected by reset. When V DD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before reading or testing it. Initial state of each register is shown as Table 8-1 . Figure 19-1 Timing Diagram after RESET MAIN PROGRAM Oscillator (XIN pin) /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 ? ? FFFE FFFF Stabilizing Time tST = 64mS at 4MHz RESET ADDRESS DATA 1 2 3 4 5 6 7 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 ?? Start ? ?? FE? ADL ADH OP /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 BUS BUS RESET Process Step ~~ ~ ~~~ ~~~

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 67 Figure 20-3 Power Fail Processor Situations Internal RESET Internal RESET Internal RESET VDD VDD VDD PFV DD MAX PFV DD MIN PFV DD MAX PFV DD MIN PFV DD MAX PFV DD MIN 64mS 64mS t < 64mS 64mS When PFDM = 1 VDD VDD PFV DD MAX PFV DD MIN PFV DD MAX PFV DD MIN When PFDM = 0 System Clock System Clock

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 68 Oct. 1999 Ver 1.0 21. OTP PROGRAMMING

21.1 DEVICE CONFIGURATION AREA

The Device Configuration Area can be programmed or left unprogrammed to select device configuration such as secu- rity bit. Ten memory locations (0F50 H ~ 0FE0H ) are designated as Customer ID recording locations where the user can store check-sum or other customer identification numbers. This area is not accessible during normal execution but is readable and writable during program / verify. Figure 21-1 Device Configuration Area Figure 21-2 Pin Assignment DEVICE 0F50H 0F50H 0FF0 H 0FF0H ID CONFIG CONFIGURATION AREA 0F60HID 0F70HID 0F80HID 0F90HID 0FA0 HID 0FB0 HID 0FC0 HID 0FD0 HID 0FE0 HID Configuration Register CONFIG ADDRESS : 0FF0H- LOCK---- PFD

0 Allow Code Read Out

1 : Prohibit Code Read Out SECURITY BIT LEVEL 0 : PFD Level High (2.5~3.5V) 1 : PFD Level Low (2.0~3.0V) PFD Level Select VDD VPP A_D0 A_D1 A_D2 A_D3 EPROM Enable A_D7 A_D6 A_D5 A_D4 CTL2 CTL1 CTL0 VSS NC

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 69 Pin No. User Mode EPROM MODE Pin Name Pin Name Description 1R A 4 ( A N 4 ) A _ D 4 Address Input Data Input/Output A12 A4 D4

2 RA5 (AN5) A_D5 A13 A5 D5

3 RA6 (AN6) A_D6 A14 A6 D6

4 RA7 (AN7) A_D7 A15 A7 D7

DD VDD Connect to VDD (6.0V)

6 RB0 (AVref/AN0) CTL0

Address/Data Control7 RB1 (INT0) CTL1

8 RB2 (INT1) CTL2

9~18 RB3~7, RC3~6, RD2 V DD Connect to VDD (6.0V)

19 XIN EPROM Enable High Active, Latch Address in falling edge

20 XOUT NC No connection

21 RESET VPP Programming Power (0V, 12.75V)

22 VSS VSS Connect to VSS (0V)

23, 24 RC0, 1 VDD Connect to VDD (6.0V)

25 RA0 (EC0) A_D0

26 RA1 (AN1) A_D1 A9 A1 D1

27 RA2 (AN2) A_D2 A10 A2 D2

28 RA3 (AN3) A_D3 A11 A3 D3

Table 21-1 Pin Description in EPROM Mode

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 71 Parameter Symbol MIN TYP MAX Unit Programming Supply Current IVPP -- 5 0 m A Supply Current in EPROM Mode IVDDP -- 2 0 m A VPP Level during Programming V IHP 11.5 12.0 12.5 V VDD Level in Program Mode V DD1H 56 6 . 5 V VDD Level in Read Mode V DD2H -2 . 7-V CTL2~0 High Level in EPROM Mode VIHC 0.8VDD -- V CTL2~0 Low Level in EPROM Mode VILC -- 0.2VDD V A_D7~A_D0 High Level in EPROM Mode VIHAD 0.9VDD -- V A_D7~A_D0 Low Level in EPROM Mode VILAD -- 0.1VDD V VDD Saturation Time T VDDS 1-- m S VPP Setup Time T VPPR --1 m S VPP Saturation Time T VPPS 1-- m S EPROM Enable Setup Time after Data Input TSET1 200 nS EPROM Enable Hold Time after TSET1 THLD1 500 nS EPROM Enable Delay Time after THLD1 TDLY1 200 nS EPROM Enable Hold Time in Write Mode THLD2 100 nS EPROM Enable Delay Time after THLD2 TDLY2 200 nS CTL2,1 Setup Time after Low Address input and Data input TCD1 100 nS CTL1 Setup Time before Data output in Read and Verify ModeTCD2 100 nS Table 21-2 AC/DC Requirements for Program/Read Mode

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 72 Oct. 1999 Ver 1.0 Figure 21-5 Programming Flow Chart START Set VDD =V DD1H Set VPP =V IHP Verify blank First Address Location EPROM Write N=1 Verify pass Last address Apply 3N program cycle 100uS program time Next address location Verify pass Report Programming failure Report Programming failure Verify for all address Verify OK Report Verify failure Report Programming OK VDD =V pp=0v END NO YES YES YES YES YES NO NO NO NO

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 73 Figure 21-6 Reading Flow Chart START Set VDD =V DD2H Set VPP =V IHP Last address First Address Location VDD =0V Report Read OK VPP =0V Next address location Verify for all address END NO YES

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics 74 Oct. 1999 Ver 1.0

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 i A. INSTRUCTION MAP LOW HIGH 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 000 - SET1 dp.bit BBS A.bit,rel BBS dp.bit,rel ADC #imm ADC dp ADC dp+X ADC !abs ASL A ASL dp TCALL SETA1 .bit BIT dp POP A PUSH A BRK

001 CLRC SBC

#imm SBC dp SBC dp+X SBC !abs ROL A ROL dp TCALL CLRA1 .bit COM dp POP X PUSH X BRA rel

010 CLRG CMP

#imm CMP dp CMP dp+X CMP !abs LSR A LSR dp TCALL NOT1 M.bit TST dp POP Y PUSH Y PCALL Upage

011 DI OR

#imm OR dp OR dp+X OR !abs ROR A ROR dp TCALL OR1 OR1B CMPX dp POP PSW PUSH PSW RET

100 CLRV AND

#imm AND dp AND dp+X AND !abs INC A INC dp TCALL AND1 AND1B CMPY dp CBNE dp+X TXSP INC X

101 SETC EOR

#imm EOR dp EOR dp+X EOR !abs DEC A DEC dp TCALL EOR1 EOR1B DBNE dp XMA dp+X TSPX DEC X

110 SETG LDA

#imm LDA dp LDA dp+X LDA !abs TXA LDY dp TCALL LDC LDCB LDX dp LDX dp+Y XCN DAS

111 EI LDM

dp,#imm STA dp STA dp+X STA !abs TAX STY dp TCALL STC M.bit STX dp STX dp+Y XAX STOP LOW HIGH 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111

000 BPL

dp.bit BBC A.bit,rel BBC dp.bit,rel ADC {X} ADC !abs+Y ADC [dp+X] ADC [dp]+Y ASL !abs ASL dp+X TCALL JMP !abs BIT !abs ADDW dp LDX #imm JMP [!abs]

001 BVC

{X} SBC !abs+Y SBC [dp+X] SBC [dp]+Y ROL !abs ROL dp+X TCALL CALL !abs TEST !abs SUBW dp LDY #imm JMP [dp]

010 BCC

{X} CMP !abs+Y CMP [dp+X] CMP [dp]+Y LSR !abs LSR dp+X TCALL

5 MUL TCLR1

!abs CMPW dp CMPX #imm CALL [dp]

011 BNE

{X} OR !abs+Y OR [dp+X] OR [dp]+Y ROR !abs ROR dp+X TCALL DBNE Y CMPX !abs LDYA dp CMPY #imm RETI

100 BMI

{X} AND !abs+Y AND [dp+X] AND [dp]+Y INC !abs INC dp+X TCALL

9 DIV CMPY

!abs INCW dp INC Y TAY

101 BVS

{X} EOR !abs+Y EOR [dp+X] EOR [dp]+Y DEC !abs DEC dp+X TCALL XMA {X} XMA dp DECW dp DEC Y TYA

110 BCS

{X} LDA !abs+Y LDA [dp+X] LDA [dp]+Y LDY !abs LDY dp+X TCALL LDA {X}+ LDX !abs STYA dp XAY DAA

111 BEQ

{X} STA !abs+Y STA [dp+X] STA [dp]+Y STY !abs STY dp+X TCALL STA {X}+ STX !abs CBNE dp XYX NOP

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics ii Oct. 1999 Ver 1.0 B. INSTRUCTION SET 1. ARITHMETIC/ LOGIC OPERATION NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC 1 ADC #imm 04 2 2 Add with carry.

2 ADC dp 05 2 3 A ← ( A ) + ( M ) + C

3 ADC dp + X 06 2 4

4 ADC !abs 07 3 4 NV--H-ZC 5 ADC !abs + Y 15 3 5

6 ADC [ dp + X ] 16 2 6

7 ADC [ dp ] + Y 17 2 6

8 ADC { X } 14 1 3

9 AND #imm 84 2 2 Logical AND

10 AND dp 85 2 3 A ← ( A ) ∧ ( M )

11 AND dp + X 86 2 4

12 AND !abs 87 3 4 N-----Z- 13 AND !abs + Y 95 3 5

14 AND [ dp + X ] 96 2 6

15 AND [ dp ] + Y 97 2 6

16 AND { X } 94 1 3

17 ASL A 08 1 2 Arithmetic shift left

18 ASL dp 09 2 4 N-----ZC

19 ASL dp + X 19 2 5

20 ASL !abs 18 3 5

21 CMP #imm 44 2 2 Compare accumulator contents with memory contents

22 CMP dp 45 2 3 ( A ) - ( M )

23 CMP dp + X 46 2 4

24 CMP !abs 47 3 4 N-----ZC 25 CMP !abs + Y 55 3 5

26 CMP [ dp + X ] 56 2 6

27 CMP [ dp ] + Y 57 2 6

28 CMP { X } 54 1 3

29 CMPX #imm 5E 2 2 Compare X contents with memory contents

30 CMPX dp 6C 2 3 ( X ) - ( M ) N-----ZC

31 CMPX !abs 7C 3 4

32 CMPY #imm 7E 2 2 Compare Y contents with memory contents

33 CMPY dp 8C 2 3 ( Y ) - ( M ) N-----ZC

34 CMPY !abs 9C 3 4

35 COM dp 2C 2 4 1’S Complement : ( dp ) ← ~( dp ) N-----Z-

36 DAA DF 1 3 Decimal adjust for addition N-----ZC

37 DAS CF 1 3 Decimal adjust for subtraction N-----ZC

38 DEC A A8 1 2 Decrement N-----Z-

39 DEC dp A9 2 4 M ← ( M ) - 1

40 DEC dp + X B9 2 5 N-----Z-

41 DEC !abs B8 3 5

42 DEC X AF 1 2

43 DEC Y BE 1 2

44 DIV 9B 1 12 Divide : YA / X Q: A, R: Y NV--H-Z-

“0” C 7654321

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 iii NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC

45 EOR #imm A4 2 2 Exclusive OR

46 EOR dp A5 2 3 A ← ( A ) ⊕ ( M )

47 EOR dp + X A6 2 4

48 EOR !abs A7 3 4 N-----Z- 49 EOR !abs + Y B5 3 5

50 EOR [ dp + X ] B6 2 6

51 EOR [ dp ] + Y B7 2 6

52 EOR { X } B4 1 3

53 INC A 88 1 2 Increment N-----Z-

54 INC dp 89 2 4 M ← ( M ) + 1

55 INC dp + X 99 2 5 N-----Z-

56 INC !abs 98 3 5

57 INC X 8F 1 2

58 INC Y 9E 1 2

59 LSR A 48 1 2 Logical shift right

60 LSR dp 49 2 4 N-----ZC

61 LSR dp + X 59 2 5

62 LSR !abs 58 3 5

63 MUL 5B 1 9 Multiply : YA ← Y × A N-----Z-

64 OR #imm 64 2 2 Logical OR

65 OR dp 65 2 3 A ← ( A ) ∨ ( M )

66 OR dp + X 66 2 4

67 OR !abs 67 3 4 N-----Z- 68 OR !abs + Y 75 3 5

69 OR [ dp + X ] 76 2 6

70 OR [ dp ] + Y 77 2 6

71 OR { X } 74 1 3

72 ROL A 28 1 2 Rotate left through carry

73 ROL dp 29 2 4 N-----ZC

74 ROL dp + X 39 2 5

75 ROL !abs 38 3 5

76 ROR A 68 1 2 Rotate right through carry

77 ROR dp 69 2 4 N-----ZC

78 ROR dp + X 79 2 5

79 ROR !abs 78 3 5

80 SBC #imm 24 2 2 Subtract with carry

81 SBC dp 25 2 3 A ← ( A ) - ( M ) - ~( C )

82 SBC dp + X 26 2 4

83 SBC !abs 27 3 4 NV--HZC 84 SBC !abs + Y 35 3 5

85 SBC [ dp + X ] 36 2 6

86 SBC [ dp ] + Y 37 2 6

87 SBC { X } 34 1 3

88 TST dp 4C 2 3 Test memory contents for negative or zero

( dp ) - 00 H N-----Z-

89 XCN CE 1 5 Exchange nibbles within the accumulator

A7~A 4 ↔ A3~A 0 N-----Z- “0” C7654321 0C 7654321 0C7654321

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics iv Oct. 1999 Ver 1.0 2. REGISTER / MEMORY OPERATION NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC

1 LDA #imm C4 2 2 Load accumulator

2 LDA dp C5 2 3 A ← ( M )

3 LDA dp + X C6 2 4

4 LDA !abs C7 3 4 5 LDA !abs + Y D5 3 5 N-----Z-

6 LDA [ dp + X ] D6 2 6

7 LDA [ dp ] + Y D7 2 6

8L D A { X } D 4 1 3

9 LDA { X }+ DB 1 4 X- register auto-increment : A ← ( M ) , X ← X + 1

11 LDX #imm 1E 2 2 Load X-register

12 LDX dp CC 2 3 X ← ( M ) N-----Z-

13 LDX dp + Y CD 2 4

14 LDX !abs DC 3 4

15 LDY #imm 3E 2 2 Load Y-register

16 LDY dp C9 2 3 Y ← ( M ) N-----Z-

17 LDY dp + X D9 2 4

18 LDY !abs D8 3 4

19 STA dp E5 2 4 Store accumulator contents in memory

20 STA dp + X E6 2 5 ( M ) ← A

21 STA !abs E7 3 5

23 STA [ dp + X ] F6 2 7

24 STA [ dp ] + Y F7 2 7

25 STA { X } F4 1 4

26 STA { X }+ FB 1 4 X- register auto-increment : ( M ) ← A, X ← X + 1

27 STX dp EC 2 4 Store X-register contents in memory

29 STX !abs FC 3 5

30 STY dp E9 2 4 Store Y-register contents in memory

32 STY !abs F8 3 5

33 TAX E8 1 2 Transfer accumulator contents to X-register : X ← A N-----Z-

34 TAY 9F 1 2 Transfer accumulator contents to Y-register : Y ← A N-----Z-

35 TSPX AE 1 2 Transfer stack-pointer contents to X-register : X ← sp N-----Z-

36 TXA C8 1 2 Transfer X-register contents to accumulator: A ← X N-----Z-

37 TXSP 8E 1 2 Transfer X-register contents to stack-pointer: sp ← X N-----Z-

38 TYA BF 1 2 Transfer Y-register contents to accumulator: A ← Y N-----Z-

41 XMA dp BC 2 5 Exchange memory contents with accumulator

42 XMA dp+X AD 2 6 ( M ) ↔ A N-----Z-

43 XMA {X} BB 1 5

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 v 3. 16-BIT OPERATION 4. BIT MANIPULATION NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC

1 ADDW dp 1D 2 5 16-Bits add without carry

YA ← ( YA ) + ( dp +1 ) ( dp ) NV--H-ZC 2C M P W d p 5 D 2 4 Compare YA contents with memory pair contents : (YA) − (dp+1)(dp) N-----ZC

3 DECW dp BD 2 6 Decrement memory pair

4 INCW dp 9D 2 6 Increment memory pair

5L D Y A d p 7 D 2 5 Load YA YA ← ( dp +1 ) ( dp ) N-----Z-

6 STYA dp DD 2 5 Store YA

7S U B W d p 3 D 2 5 16-Bits substact without carry YA ← ( YA ) - ( dp +1) ( dp) NV--H-ZC NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC

3 BIT dp 0C 2 4 Bit test A with memory : MM----Z-

4 BIT !abs 1C 3 5 Z ← ( A ) ∧ ( M ) , N ← ( M7 ) , V ← ( M6 )

8 CLRG 40 1 2 Clear G-flag : G ← “0” --0-----

9 CLRV 80 1 2 Clear V-flag : V ← “0” -0--0---

20 SETG C0 1 2 Set G-flag : G ← “1” --1-----

22 TCLR1 !abs 5C 3 6 Test and clear bits with A : 23 TSET1 !abs 3C 3 6 Test and set bits with A :

GMS87C1404/GMS87C1408 HYUNDAI MicroElectronics vi Oct. 1999 Ver 1.0 5. BRANCH / JUMP OPERATION NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC 2 BBC dp.bit,rel y3 3 5/7 if ( bit ) = 0 , then pc ← ( pc ) + rel 4 BBS dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ← ( pc ) + rel

5 BCC rel 50 2 2/4 Branch if carry bit clear

6 BCS rel D0 2 2/4 Branch if carry bit set

7 BEQ rel F0 2 2/4 Branch if equal

8 BMI rel 90 2 2/4 Branch if minus

9 BNE rel 70 2 2/4 Branch if not equal

10 BPL rel 10 2 2/4 Branch if minus

11 BRA rel 2F 2 4 Branch always

12 BVC rel 30 2 2/4 Branch if overflow bit clear

13 BVS rel B0 2 2/4 Branch if overflow bit set

14 CALL !abs 3B 3 8 Subroutine call

15 CALL [dp] 5F 2 8 M( sp)← ( pcH ), sp← sp - 1, M(sp)← (pcL), sp ← sp - 1,

17 CBNE dp+X,rel 8D 3 6/8 if ( A ) ≠ ( M ) , then pc ← ( pc ) + rel. 19 DBNE Y,rel 7B 2 4/6 if ( M ) ≠ 0 , then pc ← ( pc ) + rel. 20 JMP !abs 1B 3 3 Unconditional jump

22 JMP [dp] 3F 2 4

23 PCALL upage 4F 2 6

M(sp) ← ( pcH ), sp ← sp - 1, M(sp) ← ( pcL ), sp ← sp - 1, pcL ← ( upage ), pcH ← ”0FFH ” .

24 TCALL n nA 1 8

Table call : (sp) ← ( pcH ), sp ← sp - 1, M(sp) ← ( pcL ),sp ← sp - 1, pcL ← (Table vector L), pcH ← (Table vector H)

HYUNDAI MicroElectronics GMS87C1404/GMS87C1408 Oct. 1999 Ver 1.0 vii 6. CONTROL OPERATION & etc. NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC

1 BRK 0F 1 8

Software interrupt : B ← ”1”, M(sp) ← (pcH ), sp ← sp-1, M(s) ← (pcL), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, pcL ← ( 0FFDEH ) , pcH ← ( 0FFDFH ) . ---1-0--

2 DI 60 1 3 Disable interrupts : I ← “0” -----0--

3 EI E0 1 3 Enable interrupts : I ← “1” -----1--

5 POP A 0D 1 4 sp ← sp + 1, A ← M( sp )

7 POP Y 4D 1 4 sp ← sp + 1, Y ← M( sp )

8 POP PSW 6D 1 4 sp ← sp + 1, PSW ← M( sp ) restored

9 PUSH A 0E 1 4 M( sp ) ← A , sp ← sp - 1

11 PUSH Y 4E 1 4 M( sp ) ← Y , sp ← sp - 1

12 PUSH PSW 6E 1 4 M( sp ) ← PSW , sp ← sp - 1

13 RET 6F 1 5 Return from subroutine

14 RETI 7F 1 6

sp ← sp +1, PSW ← M( sp ), sp ← sp + 1, pcL ← M( sp ), sp ← sp + 1, pcH ← M( sp ) restored