GMK325BJ225MN

SIC401A VISHAY | Alldatasheet

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SiC401A, SiC401BCD Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com

15 A microBUCK® SiC401A/B

Integrated Buck Regulator with Programmable LDO

DESCRIPTION

The Vishay Siliconix SiC401A/B an advanced stand-alone synchronous buck regulator featuring integrated power MOSFETs, bootstrap switch, and a programmable LDO in a space-saving PowerPAK MLP55-32L pin packages. The SiC401A/B is capable of operating with all ceramic solutions and switching frequencies up to 1 MHz. The programmable frequency, synchronous operation and selectable power-save allow operation at high efficiency across the full range of load current. The internal LDO may be used to supply 5 V for the gate drive circuits or it may be bypassed with an external 5 V for optimum efficiency and used to drive external n-channel MOSFETs or other loads. Additional feat ures include cycle-by-cycle current limit, voltage soft-start, under-voltage protection, programmable over-current protection, soft shutdown and selectable power-save. The Vishay Siliconix SiC401A/B also provides an enable input and a power good output.

FEATURES

• High efficiency > 93 %  15 A continuous output current capability  Integrated bootstrap switch  Programmable 200 mA LDO with bypass logic  Temperature compensated current limit  All ceramic solution enabled  Pseudo fixed-frequency adaptive on-time control  Programmable input UVLO threshold  Independent enable pin for switcher and LDO  Selectable ultra-sonic power-save mode (SiC401A)  Selectable power-save mode (SiC401B)  Programmable soft-start and soft-shutdown  1 % internal reference voltage  Power good output  Over-voltage and under-voltage protections  Material categorization: For definitions of compliance please see www.vishay.com/doc?99912

APPLICATIONS

 Notebook, desktop and server computers  Digital HDTV and digital consumer applications  Networking and telecommunication equipment  Printers, DSL, and STB applications  Embedded applications  Point of load power supplies TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTIONS PRODUCT SUMMARY Input Voltage Range 3 V to 17 V Output Voltage Range 0.6 V to 5.5 V Operating Frequency 200 kHz to 1 MHz Continuous Output Current 15 A Peak Efficiency 93 % Typical Application Circuit for SiC401A/B (PowerPAK MLP5x5-32L) PAD 1 AGND LX PAD 3 LX PAD 2 VIN PGND LX PGND PGND PGND PGND PGND TON AGND EN\\PSV LX ILIM PGOOD BST VIN FBL AGND VDD VOUT FB 1 SS PGND VIN VIN VIN NC LX NC 24 LX ENL VIN VOUT VOUT PGOOD EN/PSV (Tri-State) LDO_EN PGND 31 30 29 25 26272832

www.vishay.com Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 Vishay Siliconix SiC401A, SiC401BCD This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION SiC401A/B Functional Block Diagram Reference Soft Start FB AGND On- time Generator Control & Status PGOOD Gate Drive Control VIN PGND TON VOUT Zero Cross Detector Valley Current Limit ILIM ENL FBL VLDO Switchover MUX A Y B LDO VDD BST FB Comparator LX EN/PSV Bypass ComparatorBypass Comparator NC NC A 26 29 A = connected to pins 6, 9-11, PAD 2 B = connected to pins 23-25, PAD 3 C = connected to pins 15-22 D = connect to pins 4, 30, PAD 1 B C D VIN VDD VDD VIN Bootstrap Switch Lo-side MOSFET Hi-side MOSFET LXBST13 LXS28 DL DL VDD VDD VDD SS 7 SiC401A/B Pin Configuration (Top View) PAD 1 AGND LX PAD 3 LX PAD 2 VIN PGND LX PGND PGND PGND PGND PGND tON AGND EN\\PSV LX ILIM PGOOD BST VIN FBL AGND VDD VOUT FB 1 SS PGND VIN VIN VIN NC LX NC 16PGND 24 LX ENL 31 30 29 25 26272832

Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 www.vishay.com Vishay Siliconix SiC401A, SiC401BCD This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com Format: LINE 1: P/N LINE 2: Siliconix logo + Lot code + ESD symbol LINE 3: Factory code + Year code + Work week code PIN DESCRIPTION Pin Number Symbol Description 1F B Feedback input for switching regulator used to program the output voltage - connect to an external resistor divider from V OUT to AGND. 2V OUT Switcher output voltage sense pin - also the input to the internal switch-over between V OUT and VLDO. The voltage at this pin must be less than or equal to the voltage at the VDD pin. 3V DD Bias supply for the IC - when using the internal LDO as a bias power supply, VDD is the LDO output. When using an external power supply as the bias for the IC, the LDO output should be disabled. 4, 30, PAD 1 A GND Analog ground 5F B L Feedback input for the internal LDO - used to program the LDO output. Connect to an external resistor divider from V DD to AGND. 6, 9 to 11, PAD 2 V IN Input supply voltage 7 SS The soft start ramp will be programmed by an internal current source charging a capacitor on this pin. 8B S T Bootstrap pin - connect a capacitor of at least 100 nF from BST to LX to develop the floating supply for the high-side gate drive. 12, 14 NC No connection 13 LXBST LX Boost - connect to the BST capacitor. 23 to 25, PAD3 LX Switching (phase) node 15 to 22 P GND Power ground

26 P GOOD

Open-drain power good indicator - high impedance in dicates power is good. An external pull-up resistor is required. 27 I LIM Current limit sense pin - used to program the current limit by connecting a resistor from ILIM to LXS.

28 LXS LX sense - connects to R ILIM

29 EN/PSV

Enable/power save input for the switching regulator - connect to A GND to disable the switching regulator, connect to VDD to operate with power-save mode and float to operate in forced continuous mode. 31 t ON On-time programming input - set the on-time by connecting through a resistor to AGND 32 ENL Enable input for the LDO - connect ENL to AGND to disable the LDO. Drive with logic signal for logic control, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND.

ORDERING INFORMATION

Part Number Package Marking (Line 1: P/N) SiC401ACD-T1-GE3 PowerPAK MLP55-32L SiC401A SiC401BCD-T1-GE3 PowerPAK MLP55-32L SiC401B SiC401DB Reference board

www.vishay.com Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 Vishay Siliconix SiC401A, SiC401BCD This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com Stresses beyond those listed under "Absol ute Maximum Ratings" may cause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Electrical Parameter Conditions Limits Unit V IN to PGND - 0.3 to + 20 V VIN to VDD - 0.4 max. LX to P GND - 0.3 to + 20 LX (Transient < 100 ns) to P GND - 2 to + 20 VDD to PGND - 0.3 to + 6 EN/PSV, PGOOD, ILIM Reference to PGND - 0.3 to + (VDD + 0.3) tON to PGND - 0.3 to + (VDD - 1.5) BST to LX - 0.3 to + 6 to PGND - 0.3 to + 25 ENL - 0.3 to VIN AGND to PGND - 0.3 to + 0.3 Temperature Maximum Junction Temperature 150 Storage Temperature - 65 to 150 Power Dissipation Junction to Ambient Thermal Impedance (R thJA)(b) IC Section 50 °C/W Maximum Power Dissipation Ambient Temperature = 25 °C 3.4 W Ambient Temperature = 100 °C 1.3 ESD Protection HBM 2 kV RECOMMENDED OPERATING CONDITIONS (all voltages referenced to GND = 0 V) Parameter Symbol Min. Typ. Max. Unit Input Voltage V IN 31 7 VVDD to PGND 35 . 5 Output Voltage VOUT 0.6 5.5 Temperature Ambient Temperature - 40 to 85 °C

Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 www.vishay.com Vishay Siliconix SiC401A, SiC401BCD This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com ELECTRICAL SPECIFICATIONS Parameter Symbol Test Conditions Unless Specified VIN = 12 V, VDD = 5 V, TA = + 25 °C for typ., - 40 °C to + 85 °C for min. and max., TJ = < 125 °C, typical application circuit Min. Typ. Max. Unit Input Power Supplies Input Supply Voltage V IN 31 7 V VDD VDD 35 . 5 VIN UVLO Threshold (a) VUVLO Sensed at ENL pin, rising 2.4 2.6 2.95 Sensed at ENL pin, falling 2.23 2.4 2.57 VIN UVLO Hysteresis VUVLO, HYS 0.25 VDD UVLO Threshold V UVLO Measured at VDD pin, rising 2.5 3 Measured at VDD pin, falling 2.4 2.9 VDD UVLO Hysteresis V UVLO, HYS 0.2 VIN Supply Current IIN ENL, EN/PSV = 0 V , VIN = 17 V 10 20 µAStandby mode; ENL= VDD, EN/PSV = 0 V 130 VDD Supply Current IDD ENL, EN/PSV = 0 V 190 300 SiC401A, EN/PSV = VDD, no load (fSW = 25 kHz), VFB > 0.6 V (b) 0.3 mA SiC401B, EN/PSV = VDD, no load, VFB > 0.6 V (b) 0.7 VDD = 5 V, fSW = 250 kHz, EN/PSV = floating, no load (b) 9 VDD = 3 V, fSW = 250 kHz, EN/PSV = floating, no load (b) 5.5 FB On-Time Threshold Static V IN and load 0.594 0.600 0.606 V Frequency Range fSW Continuous mode operation 1000 kHzMinimum fSW, (SiC401A only) 25 Bootstrap Switch Resistance 10  Timing On-Time t ON Continuous mode operation VIN = 12 V, VOUT = 5 V, fSW = 300 kHz, Rton = 133 k 999 1110 1220 nsMinimum On-Time (b) tON, min. 80 Minimum Off-Time (b) tOFF , min. VDD = 5 V 250 VDD = 3 V 370 Soft Start Soft Start Current (b) ISS 3µ A Soft Start Voltage (b) VSS When VOUT reaches regulation 1.5 V Analog Inputs/Outputs V OUT Input Resistance R O-IN 500 k  Current Sense Zero-Crossing Detector Threshold Voltage V Sense-th LX-PGND - 3 + 3 mV Power Good Power Good Threshold PG_V TH_UPPER Upper limit, VFB > internal 600 mV reference ± 20 %PG_VTH_LOWER Lower limit, VFB < internal 600 mV reference - 10 Start-Up Delay Time (between PWM enable and P GOOD high) PG_Td VDD = 5 V, CSS = 10 nF 12 msVDD = 3 V, CSS = 10 nF 7 Fault (noise-immunity) Delay Time (b) PG_ICC 5µ s Leakage Current PG_I LK 1µ A Power Good On-Resistance PG_R DS_ON 10  Fault Protection Valley Current Limit I LIM VDD = 5 V, RILIM = 3945, TJ = 0 °C to +125 °C 12.75 15 17.25 AVDD = 3.3 V, RILIM = 3945 13.5 ILIM Source Current 10 µA

www.vishay.com Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 Vishay Siliconix SiC401A, SiC401BCD This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com Notes: a. V IN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference. b. Typical value measured on standard evaluation board. c. SiC401A/B has first order temperature compensation for over current. Results vary based upon the PCB thermal layout d. The switch-over threshold is the maximum voltage diff erential between the V LDO and V OUT pins which ensures that V LDO will internally switch-over to VOUT. The non-switch-over threshold is the minimum voltage diff erential between the VLDO and VOUT pins which ensures that VLDO will not switch-over to VOUT. e. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point. ILIM Comparator Offset Voltage V ILM-LK With respect to AGND - 10 0 + 10 mV Output Under-Voltage Fault V OUV_Fault VFB with respect to Internal 600 mV reference, 8 consecutive clocks - 25 %Smart Power-Save Protection Threshold Voltage b PSave_VTH VFB with respect to internal 600 mV + 10 Over-Voltage Protection Threshold V FB with respect to internal 600 mV + 20 Over-Voltage Fault Delayb tOV-Delay 5µ s Over Temperature Shutdownb TShut 10 °C hysteresis 150 °C Logic Inputs/Outputs Logic Input High Voltage V IH 1 V Logic Input Low Volatge V IL 0.4 EN/PSV Input for P-Save Operation (b) VDD = 5 V 2.2 5 EN/PSV Input for Forced Continuous Operation (b) 12 EN/PSV Input for Disabling Switcher 00 . 4 EN/PSV Input Bias Current I EN - 10 + 10 µAENL Input Bias Current I ENL 81 5 FBL, FB Input Bias Current FBL_I LK - 1 + 1 Linear Dropout Regulator FBL (b) VLDO ACC 0.75 V LDO Current Limit LDO_I LIM Short-circuit protection, VIN = 12 V, VDD < 0.75 V 65 mAStart-up and foldback, VIN = 12 V, 0.75 < VDD < 90 % of final VDD value 115 Operating current limit, VIN = 12 V, VDD > 90 % of final VDD value 135 200 VLDO to VOUT Switch-over Threshold (d) VLDO-BPS - 130 + 130 mVVLDO to VOUT Non-switch-over Threshold (d) VLDO-NBPS - 500 + 500 VLDO to VOUT Switch-over Resistance R LDO VOUT = 5 V 2  LDO Drop Out Voltage (e) From VIN to VDD, VDD = + 5 V, IVLDO = 100 mA 1.2 V ELECTRICAL SPECIFICATIONS Parameter Symbol Test Conditions Unless Specified VIN = 12 V, VDD = 5 V, TA = + 25 °C for typ., - 40 °C to + 85 °C for min. and max., TJ = < 125 °C, typical application circuit Min. Typ. Max. Unit

SiC401A, SiC401BCD Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com

ELECTRICAL CHARACTERISTICS

Effiency/Power Loss vs. Load P-Save (VDD = 3.3 V, VOUT = 1.5 V, SiC401B) Effiency/Power Loss vs. Load P-Save (VDD = 5 V, VOUT = 1.5 V, SiC401B) Effiency/Power Loss vs. Load FCM (VDD = 5 V, VOUT = 1.5 V, SiC401B) 0.5 1.5 2.5 3.5 4.5 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PLoss(W) Efficiency(%) IOUT (A) VIN=5V VIN=12V VIN=12V VIN=5V VIN=17V VIN=17V 0.5 1.5 2.5 3.5 4.5 100 0 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 5 PLOSS(W) Efficiency(%) IOUT (A) VIN=12V VIN=5V VIN=17V VIN=12V VIN=5VVIN=5VVIN=5V VIN=5V VIN=5VVIN=5V VIN=17V PLOSS(W) 0.5 1.5 2.5 3.5 4.5 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Efficiency(%) IOUT (A) VIN=5V VIN=12V VIN=12V VIN=5V VIN=17V VIN=17V Effiency/Power Loss-P-Save vs. FCM (VDD = 3.3 V, VOUT = 1.5 V, VIN = 12 V, SiC401B) Effiency/Power Loss-P-Save vs. FCM (VDD = 5 V, VOUT = 1.5 V, VIN = 12 V, SiC401B) Effiency/Power Loss-P-Save (VOUT = 1.5 V, VIN = 12 V, SiC401B) -0.1 -0.05 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 5 PLOSS(W) Efficiency(%) IOUT (A) PSAVE FCM FCM minus PSM -0.1 -0.05 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 100 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 PLOSS(W) Efficiency(%) IOUT (A) PSAVE FCM FCM minus PSM -0.15 -0.05 0.05 0.15 0.25 0.35 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PLOSS (W) Efficiency(%) IOUT (A) 3.3V Bias 5V Bias 3.3V minus 5V

www.vishay.com Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 Vishay Siliconix SiC401A, SiC401BCD This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com (VDD = 5 V, VOUT = 1.5 V, SiC401B) Load Regulation - P-Save (VDD = 5 V, VOUT = 1.5 V, SiC401B) Switching Frequency - P-Save Mode vs. FCM (VDD = 5 V, VOUT = 1.5 V, VIN = 12 V, SiC401B) 1.4 1.41 1.42 1.43 1.44 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 1.53 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VOUT(V) IOUT (A) VIN=5V =12VINV 1.4 1.41 1.42 1.43 1.44 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 1.53 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 VOUT(V) IOUT (A) VIN=5V VIN=12V 100 150 200 250 300 350 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Switching Frequency(KHz) IOUT (A) FCM PSAVE Load Regulation - FCM (VDD = 3.3 V, VOUT = 1.5 V, SiC401B) Load Regulation - P-Save (VDD = 3.3 V, VOUT = 1.5 V, SiC401B) Switching Frequency - P-Save vs. FCM (VDD = 3.3 V, VOUT = 1.5 V, VIN = 12 V, SiC401B) 1.4 1.41 1.42 1.43 1.44 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 1.53 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VOUT(V) T (A) VIN=5V VIN=12V 1.4 1.41 1.42 1.43 1.44 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 1.53 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VOUT(V) IOUT (A) VIN=5V VIN=12V 100 150 200 250 300 350 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Switching Frequency(KHz) IOUT (A) FCM PSAVE FCM PSAVE

SiC401A, SiC401BCD Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com Load Regulation vs. Temperature - FCM (VDD = 5 V, VOUT = 1.5 V, SiC401B) Load Regulation vs. Temperature - P-Save (VDD = 5 V, VOUT = 1.5 V, SiC401B) Effiency Variation with VOUT - P-Save (VDD = 5 V, VIN = 12 V, L = 2.2 µH (4.6 m) for VOUT = 2.5 V, 3.3 V and 5 V, SiC401B) 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 1.53 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 VOUT(V) IOUT (A) VIN=12V,TA=25 VIN=5V,TA=25C VIN=12V,TA=-40C VIN=5V,TA=-40C VIN=12V,TA=85C VIN=5V,TA=85C 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 1.53 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VOUT(V) IOUT (A) VIN=12V,TA=25 VIN=5V,TA=25C VIN=12V,TA=-40C VIN=5V,TA=-40C VIN=12V,TA=85C VIN=5V,TA=85C 100 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 Efficiency(%) IOUT (A) VOUT= 1.5V VOUT=1V VOUT=3.3VVOUT=5V VOUT=2.5V Load Regulation vs. Temperature - P-Save (VDD = 3.3 V, VOUT = 1.5 V, SiC401B) Load Regulation vs. Temperature - FCM (VDD = 3.3 V, VOUT = 1.5 V, SiC401B) Efficiensy/Power Loss vs. P-Save (VOUT = 1.5 V, VIN = 12 V, SiC401B) 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 1.53 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VOUT(V) IOUT (A) VIN=12V,TA=25 VIN=5V,TA=25C VIN=12V,TA=-40C VIN=5V,TA=-40C VIN=12V,TA=85C VIN=5V,TA=85C 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VOUT(V) IOUT (A) VIN=12V,TA=25 VIN=5V,TA=25C VIN=12V,TA=-40C VIN=5V,TA=-40C VIN=12V,TA=85C VIN=5V,TA=85C 0.05 0.1 0.15 0.2 0.001 0.01 0.1 1 10 100 PLOSS(W) Efficiency(%) IOUT(A) External Bias LDO Bias LDO minus External

www.vishay.com Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 Vishay Siliconix SiC401A, SiC401BCD This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com Effiency/Power Loss vs. Load - P-Save (VDD = 3.3 V, VOUT = 1.5 V, SiC401A) Effiency/Power Loss - P-Save vs. FCM (VDD = 5 V, VOUT = 1.5 V, VIN = 12 V, SiC401A) Effiency/Power Loss vs. Load - P-Save (VDD = 5 V, VOUT = 1.5 V, SiC401A) PLOSS(W) 0.5 1.5 2.5 3.5 4.5 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Efficiency(%) IOUT(A) VIN=5V VIN=12V VIN=17V VIN=17V VIN=12V VIN=5V -0.1 -0.05 0.05 0.1 0.15 0.2 0.25 0.3 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Efficiency(%) Iout(A) PSAVE FCM FCM minus PSM PLOSS(W) 0.5 1.5 2.5 3.5 4.5 100 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 PLOSS(W) Efficiency(%) IOUT(A) VIN-5V VIN=12V VIN=17V VIN=5V VIN=12V VIN=17V Effiency/Power Loss - P-Save vs. FCM (VDD = 3.3 V, VOUT = 1.5 V, VIN = 12 V, SiC401A) Effiency/Power Loss - P-Save (VOUT = 1.5 V, VIN = 12 V, SiC401A) Load Regulation - P-Save (VDD = 5 V, VOUT = 1.5 V, SiC401A) -0.1 -0.05 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PLOSS(W) Efficiency(%) IOUT(A) PSAVE FCM FCM minus PSM -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 0.25 0.3 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PLOSS(W) Efficiency(%) IOUT(A) 3.3V Bias 3.3V minus 5V 5V Bias 1.445 1.455 1.465 1.475 1.485 1.495 1.505 1.515 1.525 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 VOUT(V) IOUT(A) VIN=12V VIN=5V

SiC401A, SiC401BCD Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com (VDD = 3.3 V, VOUT = 1.5 V, SiC401A) Load Regulation vs. Temperature - P-Save (VDD = 5 V, VOUT = 1.5 V, SiC401A) Start-up - EN/PSV (VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A, SiC401B) 1.445 1.455 1.465 1.475 1.485 1.495 1.505 1.515 1.525 1.535 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VOUT(V) IOUT(A) VIN=12V VIN=5V 1.445 1.455 1.465 1.475 1.485 1.495 1.505 1.515 1.525 1.535 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VOUT(V) IOUT(A) VIN=12V,TA=25C VIN=5V,TA=25C VIN=5V,TA=-40C VIN=5V,TA=85C VIN=12V,TA=85C VIN=12V,TA=-40C Time(1ms/div) (5V/div) (1V/div) (500mV/div) (5V/div) EN/PSV VOUT SS LX Load Regulation vs. Temperature - P-Save (VDD = 5 V, VOUT = 1.5 V, SiC401A) Shutdown - EN/PSV (VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 5 A, SiC401B) 1.445 1.455 1.465 1.475 1.485 1.495 1.505 1.515 1.525 1.535 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VOUT(V) IOUT(A) VIN=12V,TA=25C VIN=5V,TA=25CVIN=5V,TA=-40C VIN=5V,TA=85C VIN=12V,TA=85C VIN=12v,TA=-40C (5V/div) (1V/div) (500mV/div) (5V/div) Time(50µs/div) SS LX VOUT EN/PSV

www.vishay.com Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 Vishay Siliconix SiC401A, SiC401BCD This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com Start-up (Pre-Bias) - EN/PSV (VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A, SiC401B) Power-Save Mode (VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A, SiC401A) Transient Response - P-Save Load Rising (VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A to 11 A, SiC401B, dI/dt = 1 A/µs) Time(1ms/div) (5V/div) (1V/div) (500mV/div) (5V/div) EN/PSV VOUT SS LX (5V/div) (100 mV/div) Time (20µs/div) VOUT RIPPLE LX (5V/div) (50mV/div) IOUT :0A-11A VOUT RIPPLE LX (4A/div) Time(10µs/div) Power-Save Mode (VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A, SiC401B) Forced Continuous Mode (VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 15 A, SiC401B) Transient Response - P-Save Load Falling (VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 11 A to 0 A, SiC401B, dI/dt = 1 A/µs) (5V/div) (50mV/div) Time(10ms/div) VOUT RIPPLE LX (5V/div) (50mV/div) VOUT RIPPLE LX SWITCHING MODE Time(5µs/div) (5V/div) (4A/div) (50mV/div) Time(10µs/div) LX IOUT :11A to 0A VOUT RIPPLE

SiC401A, SiC401BCD Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com (VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A to 11 A, SiC401B, dI/dt = 1 A/µs) Transient Response - P-Save Load Rising (VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A to 11 A, SiC401A, dI/dt = 1 A/µs) Over Current Protection-Under Voltage Prodection (VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, SiC401B) (5V/div) (4A/div) (50mV/div) IOUT :0A to 11A LX Time(20µs/div) VOUT RIPPLE (5V/div) (100mV/div) VOUT RIPPLE IOUT:0A to 11A LX (4A/div) Time(10µs/div) Time(100µs/div) (5V/div) (5V/div)(5V/div) (500mV/div) (5A/div) Pgood VOUT Inductor LX Over Temperature Shutdown at 133.4 °C (VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A, LDO Mode, SiC401B) Transient Response - P-Save Load Falling (VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 11 A to 0 A, SiC401A, dI/dt = 1 A/µs) (5V/div) (2V/div) Pgood LX Time(500µs/div) (5V/div) VOUT RIPPLE Time(20µs/div) (4A/div) (100mV/div) LX IOUT:0A to 11A

www.vishay.com Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 Vishay Siliconix SiC401A, SiC401BCD www.vishay.com Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com Pre-Bias Start-Up The SiC401A/B can start up normally even when there is an existing output voltage present. The soft start time is still the same as normal start up (when the output voltage starts from zero). The output voltage starts to ramp up when 40 % of the voltage at SS pin meets the existing FB voltage level. Pre-bias startup is achieved by turning off the lower gate when the inductor current falls below zero. This method prevents the output voltage from discharging. Power Good Output The P GOOD (power good) output is an open-drain output which requires a pull-up resistor. When the voltage at the FB pin is 10 % below the nominal voltage, P GOOD is pulled low. It is held low until the output voltage returns above - 8 % of nominal. P GOOD will transition low if the V FB pin exceeds + 20 % of nominal, which is also the over-voltage shutdown threshold. P GOOD also pulls low if the EN/PSV pin is low when V DD is present. Output Over-Voltage Protection Over-voltage protection becomes active as soon as the device is enabled. The threshold is set at 600 mV + 20 % (720 mV). When V FB exceeds the OVP threshold, DL latches high and the low-side MOSFET is turned on. DL remains high and the controller remains off, until the EN/PSV input is toggled or VDD is cycled. There is a 5 µs delay built into the OVP detector to prevent false transitions. PGOOD is also low after an OVP event. Output Under-Voltage Protection When V FB falls 25 % below its nominal voltage (falls to 450 mV) for eight consecutive clock cycles, the switcher is shut off and the DH and DL drives are pulled low to tristate the MOSFETs. The controller stays off until EN/PSV is toggled or V DD is cycled. VDD UVLO, and POR UVLO (Under-Voltage Lock-Out) circuitry inhibits switching and tri-states the DH/DL drivers until V DD rises above 3 V. An internal POR (Power-On Reset) occurs when V DD exceeds

3 V, which resets the fault latch and a soft-start counter cycle

begins which prepares for soft-start. The SiC401A/B then begins a soft-start cycle. The PWM will shut off if V DD falls below 2.4 V. LDO Regulator SiC401A/B has an option to bias the switcher by using an internal LDO from V IN. The LDO output is connected to VDD internally. The output of the LDO is programmable by using external resistors from the VDD pin to AGND (see figure 10). The feedback pin (FBL) for the LDO is regulated to 750 mV. The LDO output voltage is set by the following equation. A minimum capacitance of 1 µF referenced to A GND is normally required at the output of the LDO for stability. Note that if the LDO voltage is set lower than 4.5 V, the minimum output capacitance for the LDO is 10 µF. LDO ENL Functions The ENL input is used to enable/disable the internal LDO. When ENL is a logic low, the LDO is off. When ENL is above the V IN UVLO threshold, the LDO is enabled and the switcher is also enabled if the EN/PSV and VDD are above their threshold. The table below summarizes the function of ENL and EN/PSV pins. The ENL pin also acts as the switcher under-voltage lockout for the V IN supply. When SiC401A/B is self-biased from the LDO and runs from the VIN power source only, the VIN UVLO Figure 9 - Soft-start Timing Diagram Figure 10- LDO Output Voltage Selection EN/PSV ENL LDO Switcher Disabled Low, < 0.4 V Off Off Enabled Low, < 0.4 V Off On Disabled 1 V < High < 2.6 V On Off Enabled 1 V < High < 2.6 V On Off Disabled High, > 2.6 V On Off Enabled High, > 2.6 V On On VLDO = 750 mV x 1 + RLDO1 RLDO2

SiC401A, SiC401BCD Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com feature can be used to prevent false UV faults for the PWM output by programming with a resistor divider at the VIN, ENL and A GND pins. When SiC401A/B has an external bias voltage at VDD and the ENL pin is used to program the V IN UVLO feature, the voltage at FBL needs to be higher than 750 mV to force the LDO off. Timing is important when driving ENL with logic and not implementing V IN UVLO. The ENL pin must transition from high to low within 2 switching cycles to avoid the PWM output turning off. If ENL goes below the V IN UVLO threshold and stays above 1 V, then the switch er will turn off but the LDO will remain on. LDO Start-up Before start-up, the LDO che cks the status of the following signals to ensure proper operation can be maintained. 1. ENL pin 2. V LDO output When the ENL pin is high and VIN is above the UVLO point, the LDO will begin start-up. During the initial phase, when the V DD voltage (which is the LDO output voltage) is less than

0.75 V, the LDO initiates a current-limited start-up (typically

65 mA) to charge the output capacitors while protecting from a short circuit event. When V DD is greater than 0.75 V but still less than 90 % of its final value (as sensed at the FBL pin), the LDO current limit is increased to ~115 mA. When V DD has reached 90 % of the final value (as sensed at the FBL pin), the LDO current limit is increased to ~ 200 mA and the LDO output is quickly driven to the nominal value by the internal LDO regulator. It is recommended that during LDO start-up to hold the PWM switching off until the LDO has reached 90 % of the final val ue. This prevents overloading the current-limited LDO output during the LDO start-up. Due to the initial current limitations on the LDO during power up (figure 11), any external load attached to the V DD pin must be limited to less than the start up current before the LDO has reached 90 % of its final regulation value. LDO Switch-Over Poeration The SiC401A/B includes a switch-over function for the LDO. The switch-over function is designed to increase efficiency by using the more efficient DC/DC converter to power the LDO output, avoiding the less efficient LDO regulator when possible. The switch-over function connects the V DD pin directly to the V OUT pin using an internal switch. When the switch-over is complete the LDO is turned off, which results in a power savings and maximi zes efficiency. If the LDO output is used to bias the SiC401A/B, then after switch-over the device is self-powered from the switching regulator with the LDO turned off. The switch-over starts 32 switching cycles after P GOOD output goes high. The voltages at the VDD and VOUT pins are then compared; if the two voltages are within ± 300 mV of each other, the V DD pin connects to the V OUT pin using an internal switch, and the LDO is turned off. To avoid unwanted switch-over, the minimum di fference between the voltages for V OUT and VDD should be ± 500 mV. It is not recommended to use the switch-over feature for an output voltage less than V DD UVLO threshold since the SiC401A/B is not operational below that threshold. Switch-Over MOSFET Parasitic Diodes The switch-over MOSFET contains parasitic diodes that are inherent to its construction, as shown in figure 12. If the voltage at the V OUT pin is higher than V DD, then the respective diode will turn on and the current will flow through this diode. This has the potential of damaging the device. Therefore, V OUT must be less than VDD to prevent damaging the device. Design Procedure When designing a switch mode supply the input voltage range, load current, switching frequency, and inductor ripple current must be specified. The maximum input voltage (V IN max.) is the highest specified input voltage. The minimum input voltage (V IN min. ) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and PCB traces. The following parameters define the design:  Nominal output voltage (V OUT)  Static or DC output tolerance  Transient response  Maximum load current (I OUT) There are two values of load current to evaluate - continuous load current and peak load current. Continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. Peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. The following values are used in this design:  V IN = 12 V ± 10 % Figure 11 - LDO Start-Up Figure 12 - Switch-over MOSFET Parasitic Diodes VOUTLDO Parastic diode Switchover MOSFET Switchover control VDD

www.vishay.com Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 Vishay Siliconix SiC401A, SiC401BCD www.vishay.com Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com  VOUT = 1.5 V ± 4 %  fSW = 300 kHz  Load = 15 A max. Frequency Selection Selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and output capacitor) and the power conversion efficiency. The desired switching frequency is 300 kHz which results from using component selected for optimum size and cost. A resistor (R tON) is used to program the on-time (indirectly setting the frequency) using the following equation. To select R tON, use the maximum value for VIN, and for tON use the value associated with maximum VIN. Substituting for RtON results in the following solution. RtON = 133.3 k, use RtON = 130 k. Inductor Selection In order to determine the inductance, the ripple current must first be defined. Low inductor values result in smaller size but create higher ripple current which can reduce efficiency. Higher inductor values will reduce the ripple current/voltage and for a given DC resistance are more efficient. However, larger inductance translates directly into larger packages and higher cost. Cost, size, output ripple, and efficiency are all used in the selection process. The ripple current will also set the boundary for P Save operation. The switchin g will typically enter P Save mode when the load current decreases to 1/2 of the ripple current. For example, if ripple current is 4 A then P Save operation will typically start for loads less than 2 A. If ripple current is set at 40 % of maximum load current, then P Save will start for loads less than 20 % of maximum current. The inductor value is typically selected to provide a ripple current that is between 25 % to 50 % of the maximum load current. This provides an optimal trade-off between cost, efficiency, and transient performance. During the on-time, voltage across the inductor is IN - V OUT). The equation for determining inductance is shown next. Example In this example, the inductor ripple current is set equal to 30 % of the maximum load current. Thus ripple current will be 30 % x 15 A or 4.5 A. To find the minimum inductance needed, use the V IN and t ON values that correspond to VINmax. A slightly larger value of 1 µH is selected. This will decrease the maximum IRIPPLE to 4.43 A. Note that the inductor must be rated for the maximum DC load current plus 1/2 of the ripple current. The ripple current under minimum V IN conditions is also checked using the following equations. Capacitor Selection The output capacitors are chosen based upon required ESR and capacitance. The maximum ESR requirement is controlled by the output ri pple requirement and the DC tolerance. The output voltage has a DC value that is equal to the valley of the output ripple plus 1/2 of the peak-to-peak ripple. A change in the output ripple voltage will lead to a change in DC voltage at the output. The design goal for output voltage ripple is 3 % of 1.5 V or 45 mV. The maximum ESR value allowed is shown by the following equations. The output capacitance is usua lly chosen to meet transient requirements. A worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capacitance. If the load release is instantaneous (load changes from maximum to zero in < 1 µs), the output capacitor must absorb all the inductor's stored energy. This will cause a peak voltage on the capacitor according to the following equation. Assuming a peak voltage V PEAK of 1.65 V (150 mV rise upon load release), and a 15 A load release, the required capacitance is shown by the next equation. Rton = 25 pF x fSW k tON = VOUT VINmax. x fSW L = (VIN - VOUT) x tON IRIPPLE L = (13.2 - 1.5) x 379 ns 4.5 A = 0.99 µH tON_VINmin. = 25 pF x RtON x VOUT VINmin. IRIPPLE = (VIN - VOUT) x tON L IRIPPLE_VINmin. = (10.8 - 1.5) x 451 ns 1 µH = 4.19 A = 451 ns ESRmax. = VRIPPLE IRIPPLEmax. ESRmax. = 10.2 mΩ = 45 mV 4.43 A COUT_min. = L (IOUT + x IRIPPLEmax.)2 (VPEAK)2 - (VOUT)2

SiC401A, SiC401BCD Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com During the load release time, the voltage cross the inductor is approximately - V OUT. This causes a down-slope or falling di/dt in the inductor. If the load dI/dt is not much faster than the dI/dt of the inductor, then the inductor current will tend to track the falling load current. This will reduce the excess inductive energy that must be absorbed by the output capacitor; therefore a smaller capacitance can be used. The following can be used to calculate the needed capacitance for a given dI LOAD/dt. Peak inductor current is shown by the next equation. I LPK = Imax. + 1/2 x IRIPPLEmax. ILPK = 10 + 1/2 x 4.43 = 12.215 A Imax. = maximum load release = 15 A Example This would cause the output current to move from 15 A to

0 A in 4 µs, giving the minimum output capacitance

requirement shown in the following equation. Note that C OUT is much smaller in this example, 169 µF compared to 316 µF based on a worst case load release. To meet the two design criteria of minimum 316 µF and maximum 10.2 m ESR, select one capacitor of 330 µF and 9 m ESR. Stability Considerations Unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or ESR loop instability. Double-pulsing occurs due to switching noise seen at the FB input or because the FB ripple voltage is too low. This causes the FB comparator to trigger prematurely after the 250 ns minimum off-time has expired. In extreme cases the noise can cause three or more successive on-times. Double- pulsing will result in higher ripple voltage at the output, but in most applications it will not affect operation. This form of instability can usually be avoided by providing the FB pin with a smooth, clean ripple signal that is at least 10 mVp-p, which may dictate the need to increase the ESR of the output capacitors. It is also imperative to provide a proper PCB layout as discussed in the Layout Guidelines section. Another way to eliminate doubling-pulsing is to add a small (~ 10 pF) capacitor across the upper feedback resistor, as shown in figure 13. This capacitor should be left unpopulated until it can be confirmed that double-pulsing exists. Adding the C TOP capacitor will couple more ripple into FB to help eliminate the problem. An optional connection on the PCB should be available for this capacitor. ESR loop instability is caused by insufficient ESR. The details of this stability issue are discussed in the ESR Requirements section. The best method for checking stability is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. Ringing for more than one cycle after the initial step is an indication that the ESR should be increased. ESR Requirements A minimum ESR is required for two reasons. One reason is to generate enough output ripple voltage to provide 10 mVp-p at the FB pin (after the resistor divider) to avoid double-pulsing. The second reason is to prevent instability due to insufficient ESR. The on-time control regula tes the valley of the output ripple voltage. This ripple voltage is the sum of the two voltages. One is the ripple generated by the ESR, the other is the ripple due to capacitive charging and discharging during the switching cycle. For most applic ations the minimum ESR ripple voltage is dominated by the output capacitors, typically SP or POSCAP devices. For stability the ESR zero of the output capac itor should be lower than approximately one-third t he switching frequency. The formula for minimum ESR is shown by the following equation. COUT_min. = 1 µH (10 + x 4.43)2 (1.65)2 - (1.5)2 COUT_min. = 316 µF Rate of change of load current = dILOAD dt COUT = ILPK x L x - x dt 2 (VPK - VOUT) ILPK VOUT Imax. dlLOAD dlLOAD dt = 2.5 A 1 µs COUT = 12.215 x 1 µH x - x 1 µs 2 (1.65 - 1.5) 12.215 1.5 2.5 COUT = 169 µF Figure 13 - Capacitor Coupling to FB Pin VOUT To FB pin CTOP ESRmin. = 3 2 x π x COUT x fSW

SiC401A, SiC401BCD Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com Select CC by using the following equation. The resistor values (R1 and R2) in the voltage divider circuit set the VOUT for the switcher. The typical value for CC is from 10 pF to 1 nF. Dropout Performance The output voltage adjustment range for continuous conduction operation is limited by the fixed 250 ns (typical) minimum off-time of the one-shot. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The duty-factor limitation is shown by the next equation. The inductor resistance and MOSFET on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. System DC Accuracy (V OUT Controller) Three factors affect V OUT accuracy: the trip point of the FB error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. The error comparator offset is trimmed so that under static conditions it trips when the feedback pin is 600 mV, 1 %. The on-time pulse from the SiC401A/B in the design example is calculated to give a pseudo-fixed frequency of 300 kHz. Some frequency variation with line and load is expected. This variation changes the output ripple voltage. Because adaptive on-time converters regulate to the valley of the output ripple, ½ of t he output ripple appears as a DC regulation error. For example, if the output ripple is 50 mV with VIN = 6 V, then the measured DC output will be 25 mV above the comparator trip point. If the ripple increases to 80 mV with V IN = 17 V, then the measured DC output will be 40 mV above the comparator trip. The best way to minimize th is effect is to minimize the output ripple. The use of 1 % feedback resistors may result in up to 1 % error. If tighter DC accuracy is required, 0.1 % resistors should be used. The output inductor value may change with current. This will change the output ripple and therefore will have a minor effect on the DC output voltage. The output ESR also affects the output ripple and thus has a minor effect on the DC output voltage. Switching Frequency Variation The switching frequency varies with load current as a result of the power losses in the MOSFETs and DCR of the inductor. For a conventional PWM constant-frequency converter, as load increases the duty cycle also increases slightly to compensate for IR and switching losses in the MOSFETs and inductor. An adaptive on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from V IN as losses increase). The on -time is essentially constant for a given VOUT/VIN combination, to offset the losses the off- time will tend to reduce slightly as load increases. The net effect is that switching fr equency increases slightly with increasing load. RL = L DCR x CL CC ≈ 1 R1//R2 2 x π x fSW x DUTY = tON(min.) tON(min.) x tOFF(max.)

www.vishay.com Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 Vishay Siliconix SiC401A, SiC401BCD www.vishay.com Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com SIC401 (2) (3) EVALUATION REF BOARD Evaluation Board Schematic TON lxbst SOFT LX VDD Vo BST PGD ILIM VIN FBL EN_PSV VOUT FB VDD C27 1uF C27 1uF PGOOD PGOOD C30 68pF C30 68pF + C18 330uF + C18 330µF C12 150uF C12 150uF C26 1uF C26 1uF R39 0RR39 0R C25 68pF C25 68pF R14 R14 R10R10 5.11k M3M3 1 1 B3 VoB3 Vo R23 5.11k R23 C11 0.1uF C11 0.1uF R52 R52 C29 3.3nF C29 3.3nF C22 68uF+ C22 68uF ENL ENL L1 1.5 µH R8 4.64K M2M2 1 1 C20 68uF+ C20 68uF C15 10µF C15 P11 VO_GND P11 VO_GND M1M1 1 1 R15 10K R15 10K R7 0RR7 0R R30130K R30130K VDD VDD VIN VIN VIN_GND VIN_GND C28 0.1uF C28 0.1uF P10 VOUT P10 VOUT R13 100R13 100 C13 0.01uF C13 0.01uF + C16 330uF + C16 330µF 1uF 1uF B4 VO_GNDB4 VO_GND EN_PSV EN_PSV VIN_GND VIN_GND M4M4 1 1 C10 68uF+ C10 68uF VIN VIN U1U1 SiC403 FB 1 FBL5 VDD3 AGND30VOUT2 VIN6 SOFT7 BST8 VIN9 VIN10 VIN11 NC14 LX 23 NC12 PGND22PGND21 LX 25 LX 24 PGND20PGND19PGND18PGND17PGND16PGND15ENL32 TON 31 AGND35 EN/PSV29 LXBST 13 ILIM 27 PGD 26 LXS 28 LX 33 VIN34 AGND4

SiC401A, SiC401BCD Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com BILL OF MATERIALS Qty. Ref. Designator PCB Footprint Value Voltage Description Part Number Manufacturer 3 C6, C11, C14 SM0603 0.1 µF 50 V CAP , 0.1 µF , 50 V, 0603 Generic Component

3 C10, C20, C22 593D 68 µF 20 V 68 µF TAN, 20 V, 593D, 20 % 593D686X0020D2TE3

1 C12 Radial 150 µF 35 V CAP , Radial, 150 µF , 35 V EU-FM1V151

1 C13 SM0402 0.01 µF 50 V CAP , 0.01 µF , 50 V, 0402 Generic Component 1 C21 SM1206 10 µF 16 V 10 µF , 16 V.X7R.B, 1206 Generic Component 3 C16, C17, C18 SM593D 330 µF 6.3 V 330 µF , 6.3 V, D 593D337X06R3E2

2 C25, C30 SM0402 68 pF 50 V CAP , 68 pF , 50 V, 0402 Generic Component

2 C26, C27 SM0805 1 µF 10 V 4.7 µF , 10 V, 0805 Generic Component 1 C28 SM0402 0.1 µF 10 V CAP , 0.1 µF , 10 V, 0402 Generic Component 1 C15 SM1210 2.2 µF 35 V CAP , 2.2 µF , 35 V, 1210 GMK325BJ225MN 1 C29 SM0603 3.3 nF 25 V CAP , CER, 22 nF , 25 V Generic Component

1 L1 IHLP4040 1 µH 0 1 µH IHLP4040DZER1R0M01

4 M1, M2, M3, M4 0 0 0 Nylonon Standoff 8834

8 P1, P2, P6, P7, P8,

P9, P10, P11 Terminal 0 0 Test Points 1573-3

1 R7 SM0603 0  50 V Res, 0  Generic Component

1 R8 SM0603 3.92K 50 V Res, 12.4K, 0603 Generic Component 1 R10 SM0603 5.11K 50 V Res, 5.11K, 0603 Generic Component

1 R13 SM0402 100  50 V 100 R, 50 V, 0402 Generic Component

1 R14 SM0402 0  50 V 100 R, 50 V, 0402 Generic Component

1 R15 SM0603 10K 50 V Res, 10K, 50 V, 0603 Generic Component

1 R23 SM0603 7.15K 50 V Res, 5.11K, 0603 Generic Component 1 R30 SM0603 130K 50 V Res, 69.8K, 0603 Generic Component

1 R39 SM0402 0  50 V 0 R, 50 V, 0402 Generic Component

1 R52 SM0603 0  50 V RES, 31.6K, 50 V, 0603 Generic Component 1U 1 PowerPAK MLP55-32L 00 15A micro BUCK integrated Buck Regulator with Programmable LDO SiC401ACD-T1-GE3/ SiC401BCD-T1GE3

4 B1, B2, B3, B4 0 0 0 BANANA JACK 575-4

www.vishay.com Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 Vishay Siliconix SiC401A, SiC401BCD www.vishay.com Document Number: 63835 S12-2109-Rev. C, 03-Sep-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com PACKAGE DIMENSIONS Note: 1. Use millimeters as the primary measurement. 2. Dimensioning and tolerances conform to ASME Y1 4.5M - 1994. 3. N is the number of terminals Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction. 4. Dimensions applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body. 6. Exact shape and size of this feature is optional. 7. Package warpage max. 0.08 mm. 8. Applied only for terminals. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locatio ns. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?63835. Top View Side View Bottom View Dim. Millimeters Inches Note A1 0.00 - 0.05 0.00 - 0.002 8 A2 0.20 ref. 0.008 ref. D 5.00 BSC 0.196 BSC e 0.50 BSC 0.019 BSC E 5.00 BSC 0.196 BSC N3 2 3 23 Nd 8 8 3 Ne 8 8 3 Dim. Millimeters Inches D2-5 0.36 0.014 E2-4 0.45 0.018

Document Number: 64714 www.vishay.com Revision: 29-Dec-08 1

Package Information

PowerPAK® MLP55-32L CASE OUTLINE Notes 1. Use millimeters as the primary measurement. 2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994. 3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction. 4. Dimension b applies to plated terminal and is m easured between 0.20 mm and 0.25 mm from terminal tip. 5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body. 6. Exact shape and size of this feature is optional. 7. Package warpage max. 0.08 mm. 8. Applied only for terminals. by marking E Pin 1 dot Top View D (5 mm x 5 mm) 32L T/SLP E2 - 2 (Nd-1) Xe Ref. Bottom ViewSide View D2 - 1 R0.200 Pin #1 identification b e D2 - 4 D2 - 3 E2 - 3 25 32 A 0.10 C B 0.08 C C A B (Nd-1) Xe Ref. L 0.36 0.360 5 6 0.10 C A B D2 - 2 E2 - 1 0.10 C A 0.45 MILLIMETERS INCHES A2 0.20 REF. 0.008 REF. D 5.00 BSC 0.196 BSC e 0.50 BSC 0.019 BSC E 5.00 BSC 0.196 BSC N(3) 32 32 Nd(3) 88 Ne(3) 88 ECN: T-08957-Rev. A, 29-Dec-08 DWG: 5983

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