L7986TA STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 43
Technical content
Datasheet sections
- 1 Pin settings
- 1.1 Pin connection
- 1.2 Pin description
- 2 Maximum ratings
- 3 Thermal data
- 4 Electrical characteristics
- 5 Functional description
- 5.1 Oscillator and synchronization
- 5.2 Soft-start
- 5.3 Error amplifier and compensation
- 5.4 Overcurrent protection
- 5.5 Enable function
- 5.6 Hysteretic thermal shutdown
- 6 Application information
- 6.1 Input capacitor selection
- 6.2 Inductor selection
- 6.3 Output capacitor selection
- 6.4 Compensation network
- 6.4.1 Type III compensation network
- 6.4.2 Type II compensation network
- 6.5 Thermal considerations
- 6.6 Layout considerations
- 6.7 Application circuit
- 7 Application ideas
- 7.1 Positive buck-boost
- 7.2 Inverting buck-boost
Features
■ 3 A DC output current ■ 4.5 V to 38 V input voltage ■ Output voltage adjustable from 0.6 V ■ 250 kHz switching frequency, programmable up to 1 MHz ■ Internal soft-start and enable ■ Low dropout operation: 100% duty cycle ■ Voltage feed-forward ■ Zero load current operation ■ Overcurrent and thermal protection ■ HSOP8 package ■ Guarantee overtemperature range (-40 °C to 125 °C)
Applications
■ Automotive: – Car audio, car infotainment ■ Industrial: – PLD, PLA, FPGA, chargers ■ Networking: XDSL, modems, DC-DC modules ■ Computer: – Optical storage, hard disk drive, printers ■ LED driving
Description
The L7986TA is a step-down switching regulator with 3.7 A (min.) current limited embedded power MOSFET, so it is able to deliver up to 3 A current to the load depending on the application conditions. The input voltage can range from 4.5 V to 38 V, while the output voltage can be set starting from
0.6 V to V
IN. Requiring a minimum set of external components, the device includes an internal 250 kHz switching frequency oscillator that can be externally adjusted up to 1 MHz. The HSOP package with exposed pad allows the reduction of R thJA down to 40 °C/W. HSOP8 exposed pad
1 Pin settings
1.1 Pin connection
Figure 1. Pin connection (top view)
1.2 Pin description
Table 1. Pin description
1 OUT Regulator output
2 SYNCH
turn-ons have a phase shift of half a period. V the device is ON and with EN lower than 0.3 V the device is OFF . 4 COMP Error amplifier output to be used for loop frequency compensation. works at its free-running frequency of 250 kHz.
7 GND Ground
CC Unregulated DC input voltage.
2 Maximum ratings
3 Thermal data
Table 2. Absolute maximum ratings Table 3. Thermal data
- Package mounted on demonstration board.
4 Electrical characteristics
TJ=-40 °C to 125 °C, VCC=12 V, unless otherwise specified. Table 4. Electrical characteristics
Table 4. Electrical characteristics (continued)
5 Functional description
- A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the synchronization signal. Its switching frequency can be adjusted by an external resistor. The voltage and frequency feed-forward are implemented.
- The soft-start circuitry to limit inrush current during the startup phase.
- The voltage mode error amplifier.
- The pulse width modulator and the relative logic circuitry necessary to drive the internal power switch.
- The high-side driver for embedded P-channel power MOSFET switch.
- The peak current limit sensing block, to handle overload and short-circuit conditions.
- A voltage regulator and internal reference. It supplies internal circuitry and provides a fixed internal reference.
- A voltage monitor circuitry (UVLO) that checks the input and internal voltages.
- A thermal shutdown block, to prevent thermal runaway.
Figure 2. Block diagram
5.1 Oscillator and synchronization
shown in Figure 5 by an external resistor connected to ground. according to the input voltage change (see Figure 4.a). through the input capacitor (see the L5988D datasheet). Figure 3. Oscillator circuit block diagram sawtooth negligible, due to the external synchronization.
5.2 Soft-start
avoids inrush current surge and makes the output voltage increase monothonically. the soft-start time and then the output voltage slew rate depend on the switching frequency. Figure 6. Soft-start scheme.
5.3 Error amplifier and compensation
mode operational amplifier, therefore, with high DC gain and low output impedance. Table 5. Uncompensated error amplifier characteristics
L7986TA Functional description Doc ID 022098 Rev 3 13/43
5.4 Overcurrent protection
The L7986TA implements overcurrent protection by sensing current flowing through the power MOSFET. Due to the noise created by the switching activity of the power MOSFET, the current sensing is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as “masking time” or “blanking time”. The masking time is about 200 ns. If the overcurrent limit is reached, the power MOSFET is turned off implementing pulse-by- pulse overcurrent protection. In the overcurrent condition, the device can skip turn-on pulses in order to keep the output current constant and equal to the current limit. If, at the end of the “masking time”, the current is higher than the overcurrent threshold, the power MOSFET is turned off and one pulse is skipped. If, at the following switching on, when the “masking time” ends, the current is still higher than the overcurrent threshold, the device skips two pulses. This mechanism is repeated and the device can skip up to seven pulses. While, if at the end of the “masking time”, the current is lower than the overcurrent threshold, the number of skipped cycles is decreased by one unit (see Figure 7). So, the overcurrent/short-circuit protection acts by switching off the power MOSFET and reducing the switching frequency down to one eighth of the default switching frequency, in order to keep constant the output current around the current limit. This kind of overcurrent protection is effective if the output current is limited. To prevent the current from diverging, the current ripple in the inductor during the on-time must not be higher than the current ripple during the off-time. That is: Equation 3 If the output voltage is shorted, VOUT≅ 0, IOUT=ILIM, D/FSW=TON_MIN, (1-D)/FSW≅ 1/FSW. So, from Equation 3, the maximum switching frequency that guarantees to limit the current results: Equation 4 With RDSon=300 mΩ, DRC=0.08 Ω, the worst condition is with VIN=38 V , ILIM=3.7 A; the maximum frequency to keep the output current limited during the short-circuit results 88 kHz. The pulse-by-pulse mechanism, which reduces the switching frequency down to one eighth the maximum F SW, adjusted by the FSW pin, that assures a full effective output current limitation, is 88 kHz*8 = 706 kHz. VIN V– OUT RDSON IOUT⋅ DCR I OUT⋅–– VOUT VF RDSON IOUT⋅ DCR I OUT⋅++ + FSW * VF DCR I⋅+ LIM() TON_MIN
where FSW* is 800 kHz divided by eight. Figure 7. Overcurrent protection
5.5 Enable function
5.6 Hysteretic thermal shutdown
so ensuring an accurate and fast temperature detection.
6 Application information
6.1 Input capacitor selection
The capacitor connected to the input must be capable of supporting the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency. So, the input capacitor must have an RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency. The maximum RMS input current flowing through the capacitor can be calculated as: Equation 6 where Io is the maximum DC output current, D is the duty cycle, η is the efficiency. Considering η=1, this function has a maximum at D=0.5 and it is equal to Io/2. In a specific application, the range of possible duty cycles must be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as: Equation 7 and Equation 8 where V F is the forward voltage on the freewheeling diode and VSW is the voltage drop across the internal PDMOS. The peak-to-peak voltage across the input capacitor can be calculated as: Equation 9 where ESR is the equivalent series resistance of the capacitor. IRMS IO D 2D 2⋅ DMAX VOUT VF+ DMIN VOUT VF+ VPP IO η----–⎝⎠ ⎛⎞ D D η---- 1D–()⋅+⋅ ESR I O⋅+⋅=
neglecting the small ESR of ceramic capacitors. In Table 6 some multi-layer ceramic capacitors suitable for this device are reported.
6.2 Inductor selection
minimum inductance value, in order to have the expected current ripple, must be selected. The rule to fix the current ripple value is to have a ripple at 20%-40% of the output current. Table 6. Input MLCC capacitors
where FSW is the switching frequency, 1/(TON + TOFF). value to have ΔIL=30% of IO is about 18 μH. output current that can be delivered, without triggering the overcurrent protection. In Table 7 some inductor part numbers are listed.
6.3 Output capacitor selection
Table 7. Inductors
the drop dominates and the voltage ripple is 28 mV. must be chosen in order to sustain the load transient. In Table 8 some capacitor series are listed.
6.4 Compensation network
E/A is considered as ideal, that is, its bandwidth is much larger than the system one. Table 8. Output capacitors
and how to keep it constant in spite of the external synchronization). Figure 8. The error amplifier, the PWM modulator, and the LC output filter
Application information L7986TA 20/43 Doc ID 022098 Rev 3 Equation 20 Equation 21 As seen in Section 5.3, two different kinds of network can compensate the loop. In the following two paragraphs the guidelines to select the type II and type III compensation network are illustrated.
6.4.1 Type III compensation network
The methodology to stabilize the loop consists of placing two zeroes to compensate the effect of the LC double pole, therefore increasing phase margin; then, to place one pole in the origin to minimize the dc error on regulated output voltage; and finally, to place other poles far from the zero dB frequency. If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency higher than the desired bandwidth (that is: 2π∗ESR∗COUT<1/BW), the type III compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low ESR (<1 mΩ), with very high frequency zero, so a type III network is adopted to compensate the loop. In Figure 9 the type III compensation network is shown. This network introduces two zeroes Z1, fZ2) and three poles (fP0, fP1, fP2). They are expressed as: Equation 22 Equation 23 fLC 2π LC OUT⋅ 1 ESR ROUT Q ROUT LC OUT ROUT ESR+()⋅⋅ ⋅ VOUT IOUT fZ1 fP0 0= fP1 2π R4 C4 C5⋅
Application information L7986TA 22/43 Doc ID 022098 Rev 3 Equation 25 4. Calculate C 5 by placing the second pole at four times the system bandwidth (BW): Equation 26 5. Set also the first pole at four times the system bandwidth and also the second zero at the output filter double pole: Equation 27 The suggested maximum system bandwidth is equal to the switching frequency divided by 3.5 (FSW/3.5), anyway, lower than 100 kHz if the FSW is set higher than 500 kHz. For example, with VOUT=5 V , VIN=24 V, IO=3 A, L=18 μH, COUT=22 μF , and ESR<1 mΩ, the type III compensation network is: Equation 28 In Figure 11 the module and phase of the open-loop gain is shown. The bandwidth is about 58 kHz and the phase margin is 50 °. 4B W⋅ fLC R1 4.99k Ω= R2 680Ω= R3 200Ω= R4 2k Ω= C3 3.3nF= C4 22nF= C5 220pF=,, , , ,,
Figure 11. Open-loop gain Bode diagram with ceramic output capacitor
6.4.2 Type II comp ensation network
In Figure 12 the type II network is shown. Figure 12. Type II compensation network and the open-loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEII(f)) are drawn.
Figure 13. Open-loop gain: module Bode diagram
- Choose a value for R 1, usually between 1 kΩ and 5 kΩ, in order to have values of C4
and C5 not comparable with parasitic capacitance of the board.
- Choose a gain (R 4/R1) in order to have the required bandwidth (BW), that means:
and Vs is the sawtooth amplitude. The voltage feed-forward keeps the ratio Vs/Vin constant.
- Calculate C 4 by placing the zero one decade below the output filter double pole:
Application information L7986TA 26/43 Doc ID 022098 Rev 3 4. Then calculate C 3 in order to place the second pole at four times the system bandwidth (BW): Equation 33 For example, with VOUT=5 V , VIN=24 V, IO=3 A, L=18 μH, COUT=330 μF , and ESR=35 mΩ, the type II compensation network is: Equation 34 In Figure 14 the module and phase of the open-loop gain is shown. The bandwidth is about 21 kHz and the phase margin is 45 °. R1 1.1k Ω= R2 150Ω= R4 4.99k Ω= C4 82nF= C5 68pF=,, ,,
Figure 14. Open-loop gain Bode diagram with electrolytic/tantalum output capacitor
6.5 Thermal considerations
Application information L7986TA 28/43 Doc ID 022098 Rev 3 where D is the duty cycle of the application and the maximum RDSon overtemperature is 220 mΩ. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN, but actually it is quite higher in order to compensate the losses of the regulator. So the conduction losses increase compared with the ideal case. b) switching losses due to power MOSFET turn-on and turn-off; these can be calculated as: Equation 36 where T RISE and TFALL are the overlap times of the voltage across the power switch (VDS) and the current flowing into it during turn-on and turn-off phases, as shown in Figure 15. TSW is the equivalent switching time. For this device the typical value for the equivalent switching time is 40 ns. c) quiescent current losses, calculated as: Equation 37 where IQ is the quiescent current (IQ=2.4 mA). The junction temperature TJ can be calculated as: Equation 38 where TA is the ambient temperature and PTOT is the sum of the power losses just seen. RthJA is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The Rth JA measured on the demonstration board described in the following paragraph is about 40 °C/W for the HSOP package. PSW VIN IOUT TRISE TFALL+() PQ VIN IQ⋅= TJ TA Rth JA PTOT⋅+=
Figure 15. Switching losses
6.6 Layout considerations
be placed very close to the device. close as possible to the input voltage pin of the device. of the converter allowing high power conversion. In Figure 16 a layout example is shown.
Figure 16. Layout example
6.7 Application circuit
In Figure 17 the demonstration board application circuit is shown. Figure 17. Demonstration board application circuit Table 9. Component list
7 Application ideas
7.1 Positive buck-boost
The L7986TA can implement the step-up/down converter with a positive output voltage. Figure 33. shows the schematic: one power MOSFET and one Schottky diode are added to Figure 33. Positive buck-boost regulator output current for the buck-boost topology can be calculated from the following equation.
where ISW is the average current in the embedded power MOSFET in the on-time. must be lower than the minimum current limit (3.7 A). input voltage from 4.5 V to 38 V. MOSFET are taken into account. Figure 34. Maximum output current according to max. DC switch current (3.0 A):
7.2 Inverting buck-boost
The L7986TA can implement the step-up/down converter with a negative output voltage. Figure 33. shows the schematic to regulate -5 V: no further external components are added to the standard buck topology. where the duty cycle is given by Equation 45 Equation 45. Figure 35. Inverting buck-boost regulator
power MOSFET are taken into account. Figure 36. Maximum output current according to switch max. peak current (3.0 A):
8 Package mechanical data
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 10. HSOP8 mechanical data
Figure 37. Package dimensions
9 Ordering information
Table 11. Order code
Table 12. Document revision history 25-Oct-2011 1 Initial release. 01-Mar-2012 2 Section 8: Package mechanical data has been updated.