GM2120

GM5110 ETC1 | Alldatasheet

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Genesis Microchip Inc. 2150 Gold Street, Alviso, P.O. Box 2150, CA USA 95002 Tel: (408) 262-6599 Fax: (408) 262-6365 165 Commerce Valley Dr. West, Thornhill, ON Canada L3T 7V8 Tel: (905) 889-5400 Fax: (905) 889-5422 1096, 12thA Main, Hal II Stage, Indira Nagar, Bangalore-560 008, India, Tel: (91)-80-526-3878, Fax: (91)-80-529-6245 4F, No. 24, Ln 123, Sec 6, Min-Chuan E. Rd., Taipei, Taiwan, ROC Tel: 886-2-2791-0118 Fax: 886-2-2791-0196 143-37 Hyundai Tower, #902, Samsung-dong, Kangnam-gu, Seoul, Korea 135-090 Tel 82-2-553-5693 Fax 82-2-552-4942 Rm2614-2618 Shenzhen Office Tower, 6007 Shennan Blvd, 518040, Shenzhen, Guandong, P.R.C., Tel (0755)386-0101, Fax (0755)386-7874 2-9-5 Higashigotanda, Shinagawa-ku, Tokyo, 141-0022, Japan, Tel 81-3-5798-2758, Fax 81-3-5798-2759 www.genesis-microchip.com / info@genesis-microchip.com Genesis Microchip Publication PRELIMINARY DATA SHEET gm5110/gm5110-H gm5120/gm5120-H XGA/SXGA LCD Controller * Genesis Microchip Confidential * NOTE: Sections in this data s heet that mention HDCP apply only to the HDCP-en abled chip versions (gm51 10-H and gm5 120-H). All oth er sect ions app ly to all chip v ersions (gm5 110, gm5110-H, gm5120, and gm5120-H). Publication number: C5110-DAT-01C Publication date: June 2002

* Genesis Microchip Confidential * gm5110/20 Preliminary Data Sheet

Revision History

C5110-DAT-01A • Initial release Aug 2001 C5110-DAT-01B • Added note on Front Cover regarding HDCP enabled versions.

• Added section 4.12 - Energy Spectrum Management (ESM).
• In section 4.15 clarified that ROM_ADDR[15:0] have internal 60KΩ pull-down resistor.
• Changes to Table 21– DC Characteristics: – Renamed parameters θJA_XGA, θJA_SXGA, θJC_XGA and θJC_SXGA to θJA_5110, θJA_5120, θJC_5110 and θJC_5120 and revised their values. – Added note (4) regarding the maximum case temperature.
• Changes to Table 22– Maximum Speed of Operation: – Renamed parameters P5110 and P5120 and revised their values. – Renamed parameters I5110, I5110_2.5_VDD, etc. – Added note (6).
• Removed the clock speed column from section 6 - Ordering Information and added the ordering information for gm5110-H and gm5120-H. Oct 2001 D5110-DAT-01C • Pins 143 ~ 146: changed xxx_SDDS or xxxx_SDDS to xxx_DDDS or xxxx_DDDS respectively
• Pins 138 ~ 141: changed xxx_DDDS or xxxx_DDDS to xxx_SDDS or xxxx_SDDS respectively
• Pins 147 ~ 148: changed xxx_DPLL to xxx_RPLL June 2002 Related documents Chip documents C5110-PBR-01 Preliminary Product Brief gm5110 C5120-PBR-01 Preliminary Product Brief gm5120 C5115-APB-01 gm5115 Product Family On-chip Microcontroller (OCM) Firmware Configurations C5115-APB-02 gm5115 Product Family Support for Standard RGB (sRGB) C5115-TOP-01 gm5115 Theory of Operation C5115-DSL-01 gm5115 Register Listing C5115-DSR-02 gm5115 Input Processing Programming Guide Reference design documents B0108-GUD-01 5110RD1 Reference Design Users Guide B0108-SCH-01 5110RD1 Reference Design Schematics B0108-BOM-01 5110RD1 Reference Design Bill of Materials Firmware / tools documents B0092-SWT-01 gm5115 Product Family Firmware Theory of Operation for Full Custom Configuration B0092-SUG-01 gm5115 Product Family Firmware User Guide for Full-Custom B0092-PRN-01 gm5115 Product Family Firmware Release Notes for Full-Custom B0108-SUG-01 gm5115 Product Family Firmware User Guide for Standalone B0108-PRN-01 gm5115 Product Family Firmware Release Notes for Standalone S0006-GUD-01 G-Probe Debug Software User Guide S0014-GUD-01 G-Wizard Software User Guide Trademarks: RealColor, Real Recovery, and Ultra-Reliable DVI are trademarks of Genesis Microchip Inc. © Copyright 2001, Genesis Microchip Inc. All Rights Reserved.

* Genesis Microchip Confidential * gm5110/20 Preliminary Data Sheet Genesis Microchip Inc. reserves the right to change or modify the information contained herein without notice. Please obtain the most recent revision of this document. Genesis Microchip Inc. makes no warranty for the use of its products and bears no responsibility for any errors or omissions that may appear in this document.

* Genesis Microchip Confidential * gm5110/20 Preliminary Data Sheet June 2002 C5110-DAT-01C iii Table Of Contents

* Genesis Microchip Confidential * gm5110/20 Preliminary Data Sheet June 2002 C5110-DAT-01C iv

* Genesis Microchip Confidential * gm5110/20 Preliminary Data Sheet June 2002 C5110-DAT-01C 2 11..22 ggmm55111100//2200 FFeeaattuurreess

FEATURES

• Zoom (from VGA) and shrink (from UXGA) scaling
• Integrated 8-bit triple-channel ADC / PLL
• Integrated Ultra-Reliable DVI 1.0-compliant receiver
• High-Bandwidth Digital Content Protection (HDCP)
• Embedded microcontroller with parallel ROM interface
• On-chip versatile OSD engine
• All system clocks synthesized from a single external crystal
• Programmable gamma correction (CLUT)
• RealColor controls provide sRGB compliance
• PWM back light intensity control
• 5-Volt tolerant inputs
• Low EMI and power saving features
• High-Quality Advanced Scaling
• Fully programmable zoom ratios
• High-quality shrink capability from UXGA resolution
• Real Recovery function provides full color recovery image for refresh rates higher than those supported by the LCD panel
• Moire cancellation
• Analog RGB Input Port
• Supports up to 162MHz (SXGA 75Hz / UXGA 60Hz)
• On-chip high-performance PLLs (only a single reference crystal required)
• Auto-Configuration / Auto-Detection
• Input format detection
• Phase and image positioning
• Ultra-Reliable DVI Compliant Input Port
• Operating up to 165 MHz (up to UXGA 60Hz)
• Direct connect to all DVI compliant digital transmitters
• High-bandwidth Digital Content Protection (HDCP)
• RealColor Technology
• Digital brightness and contrast controls
• TV color controls including hue and saturation controls
• Flesh-tone adjustment
• Full color matrix allows end-users to experience the same colors as viewed on CRTs and other displays (e.g. sRGB compliance)
• On-chip OSD Controller
• On-chip RAM for downloadable menus
• 1, 2 and 4-bit per pixel character cells
• Horizontal and vertical stretch of OSD menus
• Blinking, transparency and blending
• On-chip Microcontroller
• Requires no external micro-controller
• External parallel ROM interface allows firmware customization with little additional cost
• 21 general-purpose inputs/outputs (GPIO's) available for managing system devices (keypad, back-light, NVRAM, etc)
• Industry-standard firmware embedded on-chip, requires no external ROM (configuration settings stored in NVRAM)
• Programmable Output Format
• Single / double wide up to XGA 75Hz output for gm5110 and up to SXGA 75Hz output for gm5120
• Pin swap, odd / even swap and red / blue group swap of RGB outputs for flexibility in board layout
• Support for 8 or 6-bit panels (with high-quality dithering)
• Highly Integrated System-on-a-Chip Reduces Component Count for Highly Cost Effective Solution
• Stand-alone operation requires no external ROM and no firmware development for Fast Time to Market
• Pin and register compatible Family of Products: - gm5110/gm5120 Dual-Interface XGA/SXGA - gm3110/gm3120 Digital-Interface XGA/SXGA - gm2110/gm2120 Analog-Interface XGA/SXGA

Quad Flat Pack (PQFP) package. Figure 2 provides the pin locations for all signals. Figure 2. gm5110/20 Pin Out Diagram

Table 1. Analog Input Port AGND_RED pin on system board (as close as possible to the pin). RED+ 171 AI Positive analog input for Red channel. RED- 170 AI Negative analog input for Red channel. AGND_RED 169 AG Analog ground for the red channel. Must be directly connected to the analog system ground plane. AGND_GREEN pin on system board (as close as possible to the pin). GREEN+ 167 AI Positive analog input for Green channel. GREEN- 166 AI Negative analog input for Green channel. AGND_GREEN 165 AG Analog ground for the green channel. Must be directly connected to the analog system ground plane. AGND_BLUE pin on system board (as close as possible to the pin). BLUE+ 163 AI Positive analog input for Blue channel. BLUE- 162 AI Negative analog input for Blue channel. AGND_BLUE 161 AG Analog ground for the blue channel. Must be directly connected to the analog system ground plane. decoupling capacitor to AGND_ADC pin on system board (as close as possible to the pin). ADC_TEST 159 AO Analog test output for ADC Do not connect. gap reference, master biasing and full-scale adjust. Must be directly connected to analog system ground plane. SGND_ADC 157 AG Dedicated pad for substrate guard ring that protects the ADC reference system. Must be directly connected to the analog system ground plane. GND1_ADC 156 G Digital GND for ADC clocking circuit. GND1_ADC pin on system board (as close as possible to the pin). GND2_ADC 154 G Digital GND for ADC clocking circuit. Must be directly connected to the digital system ground plane. GND2_ADC pin on system board (as close as possible to the pin).

Table 2. DVI Input Port AVDD_IMB 173 AP Analog VDD (3.3V) for internal biasing circuits. Must be bypassed with decoupling capacitors (as close as possible to the pin). REXT 174 AI External reference resistor. An external 1Kohm (1%) resistor should be connected from this pin to AVDD_IMB pin. AGND_IMB 175 AG Analog GND for internal biasing circuits. Must be connected directly to the ground plane. GND_RX2 pin (as close as possible to the pin). GND_RX2 177 G GND for DVI input pair 2 logic circuits. Must be connected directly to the ground plane. AGND_RX2 178 AG Analog GND for DVI input pair 2 input buffer. Must be connected directly to the analog ground plane. capacitor to AGND_RX2 pin (as close as possible to the pin). GND_RX1 pin (as close as possible to the pin). GND_RX1 183 G GND for DVI input pair 1 input buffer. Must be connected directly to the analog ground plane. AGND_RX1 184 AG Analog GND for DVI input pair 1 input buffer. Must be connected directly to the analog ground plane. capacitor to AGND_RX1 pin (as close as possible to the pin). GND_RX0 pin (as close as possible to the pin). GND_RX0 189 G GND for DVI input pair 0 logic circuits. Must be connected directly to the ground plane. AGND_RX0 190 AG Analog GND for DVI input pair 0 input buffer. Must be connected directly to the analog ground plane. capacitor to AGND_RX0 pin (as close as possible to the pin). capacitor to AGND_RXC pin (as close as possible to the pin). AGND_RXC 197 AG Analog GND for DVI input clock pair input buffer. Must be connected directly to the analog ground plane. GND_RXPLL 198 G Digital GND for the DVI receiver internal PLL. Must be connected directly to the system ground plane. capacitor to AGND_RXPLL pin (as close as possible to the pin). CLKOUT 201 AO For test purposes only. Do not connect. Table 3. RCLK PLL Pins 0.1uF capacitor to pin AVSS_RPLL (as close to the pin as possible). AVSS_RPLL 149 AG Analog ground for the Reference DDS PLL. Must be directly connected to the analog system ground plane. CMOS/TTL clock oscillator (refer to Figure 7). This is a 5V-tolerant input. XTAL 151 AO Crystal oscillator output. VDD_RPLL 148 P Digital power for RCLK PLL. Connect to 3.3V supply. VSS_RPLL 147 G Digital ground for RCLK PLL.

Table 4. Analog HSYNC/VSYNC Inputs HSYNC 137 I ADC input horizontal sync input. VSYNC 136 I ADC input vertical sync input. Table 5. System Interface and GPIO Signals RESETn 5 I Active-low hardware reset signal. The reset signal must be held low for at least 1µS. GPIO0/PWM0 40 IO General-purpose input/output signal or PWM0. Open drain option via register setting. GPIO1/PWM1 41 IO General-purpose input/output signal or PWM1. Open drain option via register setting. GPIO2/PWM2 42 IO General-purpose input/output signal or PWM2. Open drain option via register setting. connected to Timer 1 clock input of the OCM. connected to the OCM UART data input signal by programming an OCM register. connected to the OCM UART data output signal by programming an OCM register. GPIO6 46 IO General-purpose input/output signal. GPIO7 47 IO General-purpose input/output signal. directly wired to OCM int_0n. GPIO9 48 IO General-purpose input/output signal. Open drain option via register setting. GPIO10 49 IO General-purpose input/output signal. Open drain option via register setting. GPIO14/DDC_SCL 6 I DDC Interface for DVI-HDCP communication. This is 5V-tolerant SCL pin. GPIO15/DDC_SDA 7 IO DDC Interface for DVI-HDCP communication. This is 5V-tolerant SDA pin. General-purpose input/output signal. GPIO22/HCLK 204 IO General-purpose input/output signal when host interface is disabled, or host clock signal. General-purpose output signals.

Table 6. Display Output Port DCLK 118 O Panel output clock. DVS 117 O Panel Vertical Sync. DHS 116 O Panel Horizontal Sync. DEN 115 O Panel Display Enable, which frames the output background.

Table 7. Parallel ROM Interface Port ROM address output. These pins also serve as 5V-tolerant bootstrap inputs on power up. 5V-tolerant external PROM data input, or general-purpose input in standalone operation. Table 8. Reserved Pins

other VDD pins should be connected to 3.3V power supplies. Table 9. Power Pins for ADC Sampling Clock DDS AVDD_DDDS 146 AP Analog power for the Destination DDS. Connect to 3.3V supply. (as close to the pin as possible). AVSS_DDDS 145 AG Analog ground for the Destination DDS. Must be directly connected to the analog system ground. VDD_DDDS 144 P Digital power for the Destination DDS. Connect to 3.3V supply. VSS_DDDS 143 G Digital ground for the Destination DDS. Table 10. Power Pins for Display Clock DDS AVDD_SDDS 141 AP Analog power for Source DDS. Connect to 3.3V supply. (as close to the pin as possible). AVSS_SDDS 140 AG Analog ground for Source DDS. Must be directly connected to the analog system ground plane. VDD_SDDS 139 P Digital power for the Source DDS. Connect to 3.3V supply. VSS_SDDS 138 G Digital ground for the Source DDS. Table 11. I/O Power and Ground Pins Must be bypassed with a 0.1uF capacitor to RVSS (as close to the pin as possible). Table 12. Core Power and Ground Pins Must be bypassed with a 0.1uF capacitor to CVSS (as close to the pin as possible).

4.1.1 Using the Internal Oscillator with External Crystal

circuit also minimizes the overdrive of the crystal, which reduces the aging of the crystal. sampled. If the pin is left unconnected (internal pull-down) then internal oscillator is enabled. Figure 4. Using the Internal Oscillator with External Crystal

then distributed to the gm5110/20 circuits.

3.3 Volts

Figure 5. Internal Oscillator Output capacitances. Approximate values are provided in Figure 6.

Figure 6. Sources of Parasitic Capacitance equivalent series resistance must be less then 90 Ohms.

4.1.2 Using an External Clock Oscillator

Figure 7. Using an External Single-ended Clock Oscillator Table 13. TCLK Specification

4.1.3 Clock Synthesis

The gm5110/20 synthesizes all additiona l clocks internally as illu strated in Figure 8 below.

1. Main Timing Clock (TCLK) is the output of the chip internal crystal oscillator. TCLK is

derived from the TCLK/XTAL pad input.

1. Reference Clock (RCLK) synthesized by RCLK PLL (RPLL) us ing TCLK as the
2. DVI Input Clock (DVI_CLK) synthesized by DVI receiver PLL using RC+/RC- pair as
3. Input Source Clock (S CLK) synthesi zed by S ource DDS (SDDS) PLL using input

HSYNC as the reference. The SDDS internal digital logic is driven by RCLK.

1. Display Clock (DCLK) synthesized by Des tination DDS (DDDS) P LL using IP_CLK as

the reference. The DDDS internal digital logic is driven by RCLK.

1. Half Re ference Clock (RCLK/2) is th e RCLK (see 2, above) divided by 2. Used as
2. Quarter Reference Clock (RCLK/4) is th e RCLK (see 2, above) divided by 4. Used as

alternative clock (faster than TCLK) to drive IFM.

1. ADC Output Clock (SENSE_ACLK) is a de lay-adjusted ADC sa mpling clock, ACLK.

Figure 8. Internally Synthesized Clocks

1. Input Domain Clock (IP_CLK). Max = 165MHz
2. Host Interface and On-Chip Microcontroller Clock (OCM_CLK). Max = 100MHz
3. Filter and Display Pixel Clock (DP_CLK). Max = 135MHz
4. Source Timing Measurement Domain Clock (IFM_CLK). Max = 50MHz
5. ADC Domain Clock (ACLK). Max = 165MHz.

CLOCK_CONFIG registers (index 0x03 and 0x04).

Figure 9. On-chip Clock Domains

1. Reset all registers of all types to the ir default state (this is 00h unless otherwise specified

in the gm5110/20 Register Listing).

1. Force each clock domain into reset. Reset will remain asserted for 64 lo cal clock domain

cycles following the de-assertion of RESETn.

1. Operate the OCM_CLK domain at the TCLK frequency.
2. Preset the RCLK PLL to output ~200MHz clock (assumes 14.3MHz TCLK crystal
3. Wait for RCLK PLL to Lock. Then, switch the OCM_CLK dom ain to operate f rom the
4. If a pull-up resistor is installed on ROM_ADDR9 pin (s ee Table 18 ), then th e OCM

until OCM_CONTROL register (0x22) bit 1 is enabled.

4.3.1 ADC Pin Connection

Table 14. Pin Connection for RGB Input with HSYNC/VSYNC Figure 10. Example ADC Signal Terminations

4.3.2 ADC Characteristics

Table 15. ADC Characteristics Full Scale Adjust Sensitivity +/- 1 LSB Measured at ADC Output. Independent of full scale RGB input. Zero Scale Adjust Sensitivity +/- 1 LSB Measured at ADC Output. No Missing Codes Guaranteed by test. clamp pulse position and width are programmable.

4.3.3 Clock Recovery Circuit

Figure 11. gm5110/20 Clock Recovery

4.3.4 Sampling Phase Adjustment

SDDS. The accuracy of the sam pling phase is ch ecked and the resu lt read from a register. This feature enables accurate auto-adjustment of the ADC sampling phase.

4.3.5 ADC Capture Window

vertical direction it is defined in lines. All the p arameters beginni ng with “Source” are programmed gm 5110/20 registers values. Figure 12. ADC Capture Window derived from external HSYNC and VSYNC inputs.

frequency ranging from 20 MHz to 165 MHz.

4.4.1 DVI Receiver Characteristics

described in "gm5115 Layout Guidelines" document number C5115-SLG-01A. Table 16. DVI Receiver Characteristics

• Active: The receiver block is fully on and running.
• Standby: Only the RC (clock) channel remains active. Data and other control signals are not decoded.
• Off: The receiver block is powered down.

4.4.2 DVI Capture Window

embedded HSYNC / VSYNC jitter. with ADC inputs (see Section 4.3.5.). by performing Input Format Measurement (IFM) need be programmed.

4.4.3 HDCP (High-Bandwidth Digital Content Protection)

support of the HDCP 1.0 protocol for DVI inputs. made available to HDCP licensed customers. Digital Content Protection System specification (see www.digital-cp.com). but not the standard versions gm5110 and gm5120. The gm5110/20 contains hundreds of test patterns, som e of which are shown in Figure 13. used to produce other patterns. Figure 13. Some of gm5110/20 built-in test patterns

format. It is also capable of detecting the field type of interlaced formats. The IFM fe atures a programm able reset, sepa rate from the regular gm5110/20 soft reset. while gm5110/20 is running in power down mode. RCLK/4), while vertical measurements are measured in terms of HSYNC pulses. For an overview of the internally synthesized clocks, see section 4.1.

4.6.1 HSYNC / VSYNC Delay

can capture data that spans across the sync pulse. HSYNC and VSYNC boundaries creates a horizontal and/or vertical wrap effect. HSYNC is delayed by a programmed number of selected input clocks. Figure 14. HSYNC Delay

incremented by the “first” HSYNC. Figure 15. Active Data Crosses HSYNC Boundary

4.6.2 Horizontal and Vertical Measurement

rising VSYNC. Measurements are made on every field / frame until disabled.

4.6.3 Format Change Detection

exceeding this threshold, a status bit is set. An interrupt can also be programmed to occur.

4.6.4 Watchdog

a second register bit is set. An interrupt can also be programmed to occur.

4.6.5 Internal Odd/Even Field Detection (For Interlaced Inputs to ADC Only)

selected from a predefined set of values. Figure 16. ODD/EVEN Field Detection

4.6.6 Input Pixel Measurement

setting, centering the image, or adjusting the contrast and brightness.

4.6.7 Image Phase Measurement

This functio n m easures the sam pling phase quality over a selected active window region. setting. Please refer to the gm5110/20 Programming Guide for the optimized algorithm.

4.6.8 Image Boundary Detection

is used when programming the Active Window and centering the image.

4.6.9 Image Auto Balance

signed offset stage as shown in Figure 17. Figure 17. RealColorTM Digital Color Controls saturation (multiplicative factor applied to both Y and V). final result is then dithered to eight or six bits (as required by the LCD panel).

4.7.1 RealColor™ Flesh tone Adjustment

* Genesis Microchip Confidential * gm5110/20 Preliminary Data Sheet June 2002 C5110-DAT-01C 26 tables, but rather a manipula tion of YUV-channel parameters. Flesh tone adjustment is available for all inputs.

4.7.2 Color Standardization and sRGB Support

Internet shoppers may be ve ry picky about what color th ey experience on the display. gm5110/20 RealColorTM digital color controls can be used to make the colo r response of an LCD monitor compliant with standard color defi nitions, such as sRGB. sRGB is a standard for color exchange proposed by Microsoft and HP (see www.srgb.com). gm5110/20 RealColor controls can be used to make LCD monitors sRGB compliant, even if the native response of the LCD panel itself is not. For more information on sRGB compliance using gm5110/20 family devices please refer to the sRGB application brief C5115-APB-02A. 44..88 HHiigghh--QQuuaalliittyy SSccaalliinngg The gm5110/20 zoom scaler uses an adaptive scaling technique prop rietary to Genesis Microchip Inc., and provides high quality scaling of real time video and graphics images. An input field/frame is scalable in both the vertical and horizontal dimensions. Interlaced fields may be spatially de-interl aced by vertically scaling and repositioning the input fields to align with the output display’s pixel map.

4.8.1 Variable Zoom Scaling

The gm5110/20 scaling filter can combine its adva nced scaling with a pixel-replication type scaling function. This is useful for improving the sharpness and definition of graphics when scaling at high zoom factors (such as VGA to XGA).

4.8.2 Horizontal and Vertical Shrink

A shrink function may be performed on the input da ta. This is an arbitrary horizontal active resolution reduction to between (50% + 1 pixel) to 100% of the input. For example, this allows SXGA 1280 pixels to be displayed as 1024 (XGA). The gm5110/20 provides an arbitrar y vertical shrink down to (50% + 1 line) of the original image size. Together with the arbitrary hor izontal shrink, this a llows the gm5110/20 to capture and display images one VESA standard format larger than the native display resolution. For example, SXGA may be captured and displayed on an XGA panel.

* Genesis Microchip Confidential * gm5110/20 Preliminary Data Sheet June 2002 C5110-DAT-01C 27

4.8.3 Moiré Cancellation

The gamma curve and other non-linearities can a ffect the energy distribution of pixels when scaled to different areas of the screen. Th is is an example of the Moiré effect. The gm5110/20 has hardware features to negate the Moiré effect, improving the scaling quality. 44..99 BByyppaassss OOppttiioonnss The gm5110/20 has the capab ility to completely bypass intern al processing. In this case, captured input signals and data are passed, with a small register latency, straight through to the display output. The gm5110/20 is also able to bypass the zoom filter. 44..1100 GGaammmmaa LLUUTT The gm5110/20 provides an 8 to 10-bit look-up table (LUT) for each input color channel intended for Gamma correction and to compen sate for a non-linear response of the LCD panel. A 10-bit output results in an improved color depth contro l. The 10-bit output is then dithered down to 8 bits (or 6 bits) per channel at the display (see section 4.11.3 below). The LUT is user programmable to provide an ar bitrary transfer function. Gamma correction occurs after the zoom / shrink scaling block. The LUT has bypass enable. If bypassed, the LUT does not require programming. 44..1111 DDiissppllaayy OOuuttppuutt IInntteerrffaaccee The Display Output Port prov ides data and control signal s that permit the gm5110/20 to connect to a variety of flat panel or CRT devices. The output interface is configurable for 18 or 24-bit RGB pixels, either single or double pi xel wide. All display data and timing signals are synchronous with the DCLK output clock.

4.11.1 Display Synchronization

Refer to section 4.1 for information regarding internal clock synthesis. The gm5110/20 supports the following display synchronization modes:

• Frame Sync Mode: The display frame rate is sync hronized to the input frame or field rate. This mode is used for standard operation.
• Free Run Mode: No synchronization. This mode is used when there is no valid input timing (i.e. to display OSD messages or a splash screen) or for testing purposes. In

the display window and timing registers.

4.11.2 Programming the Display Timing

signals. The figure below provides the registers that define the output display timing. leading edge of the vertical sync signal. Figure 18. Display Windows and Timing The double-wide output only supports an even number of horizontal pixels.

Figure 19. Single Pixel Width Display Data Figure 20. Double Pixel Wide Display Data

4.11.3 Panel Power Sequencing (PPWR, PBIAS)

Figure 21. Panel Power Sequencing

* Genesis Microchip Confidential * gm5110/20 Preliminary Data Sheet June 2002 C5110-DAT-01C 30

4.11.4 Output Dithering

The Gamma LUT outputs a 10-bit value for each co lor channel. This value is dithered down to either 8-bits for 24-bit per pixel panels, or 6-bits for 18-bit per pixel panels. The benefit of dithering is that the eye te nds to average neighboring pixels and a smooth image free of contours is perceived. Dithering works by spreading the quantization error over neighboring pixels both spatially and tempora lly. Two dithering algorithms are available: random or ordered dithering. Ordered dithering is recommended when driving a 6-bit panel. All gray scales are available on the panel output whether using 8-bit panel (dithering from 10 to 8 bits per pixel) or using 6-bit panel (dithering from 10 down to 6 bits per pixel). 44..1122 EEnneerrggyy SSppeeccttrruumm MMaannaaggeemmeenntt ((EESSMM)) High spikes in the EMI power spectrum may cause LCD m onitor products to violate emissions standards. The gm5110/20 has many features that can be used to reduce electromagnetic interference (EMI). These include drive strength control and clock spectrum modulation. These features help to elimin ate the costs associat ed with EMI reducing components and shielding. 44..1133 OOSSDD The gm5110/20 has a fully programmable, high- quality OSD controller. The graphics are divided into “cells” 12 by 18 pixels in size. The cells are stored in an on-chip static RAM (4096 words by 24 bits) and can be stored as 1-bit per pixel data, 2-bit per pixel data or 4-bit per pixel data. This permits a good compression ra tio while allowing more than 16 colors in the image. Some general features of the gm5110/20 OSD controller include: OSD Position – The OSD menu can be positioned a nywhere on the display region. The reference point is Horizontal and Vertical Display Bac kground Start (DH_BKGND_START and DV_BKGND_START in Figure 18). OSD Stretch – The OSD image can be stretched horizontally and/or vertically by a factor of two, three, or four. Pixel and line replication is used to stretch the image. OSD Blending – Sixteen levels of blending are supported for the character-mapped and bitmapped images. One host register controls the blend levels for pixels with LUT values of 128 and greater, while another hos t register controls the blend levels for pixels with LUT values of 127 and lower. OSD color LUT value 0 is reserved for transparency and is unaffected by the blend attribute.

4.13.1 On-Chip OSD SRAM

The on-chip static RAM (4096 words by 24 bits) stores the cell map and the cell definitions. the foreground and background colors, blinking, etc. Figure 22. OSD Cell Map and 4-bit per pixel cell definitions require 9, 18 and 36 words of the OSD RAM respectively. the following inequality must be satisfied. (Note, the ROUND operation rounds 3.5 to 4).

pixel cells. Of course, different numbers of each type can also be used.

4.13.2 Color Look-up Table (LUT)

configuration, as illustrated in Figure 23.

• Auto mode detection
• Auto-configuration
• Standard high-quality OSD menus
• Factory test / calibration functions Analog RGB Input DVI Input ROM NVRAM OCM gm5110/20 OCM gm5110/20 PROM Analog RGB Input DVI Input NVRAM Output to LCD Panel Output to LCD Panel Configuration settings in NVRAM:
• OSD Colors, Logo and other configuration
• Panel Parameters
• Additional input modes
• Code patches User settings in NVRAM:
• Brightness/contrast settings, etc
• On mode-by-mode basis External ROM:
• Contains firmware code and data for all firmware functions

Figure 23. OCM Full-Custom and Standalone Configurations Figure 23A - Standalone Configuration

4.14.1 Standalone Configuration

device. This is illustrated in Figure 24 below. Figure 24. Programming OCM in Standalone Configuration

4.14.2 Full-Custom Configuration

ROM or programmable Flash ROM devices. Normally 64KB or 128KB of ROM is required.

14.3 MHz crystal is being used to produce TCLK, and the OCM_CLK is derived from

TCLK, then a 45ns ROM can be used. tool for defining OSD menus and functionality. Figure 25. Programming the OCM in Full-Custom Configuration

commercially available ROM programmers. PROMJET ROM emulator can be used (http://www.emutec.com/pjetmain.html).

4.14.3 General Purpose Inputs and Outputs (GPIO’s)

PWM0, PWM1 and PWM2 back light intensity controls, as described in section 4.17.2 below. GPIO3/TIMER1 43 Timer1 input of the OCM. OCM UART data in/out signals respectively. GPIO8/IRQINn 39 OCM external interrupt source (IRQINn). GPIO11/ROM_WEn 50 Write enable for external ROM if programmable FLASH device is used. standalone configuration (section Figure 23). input, for passing HDCP keys. GPIO16/HFSn 205 Serial data line for 2-wire host interface. GPIO21/IRQn 4 OCM interrupt output pin. GPIO22/HCLK 204 Serial input clock for 2-wire host interface. Table 17. gm5110/20 GPIOs and Alternate Functions

ROM_ADDR[15:0] have a 60KΩ internal pull-down resistor. HOST_ADDR(6:0) ROM_ADDR(6:0) If using 2-wire host protocol, these are the serial bus device address. HOST_PROTOCOL ROM_ADDR7 Program this bit to 0 for 2-wire host interface operation. HOST_PORT_EN ROM_ADDR8 Program this bit to 0 for 2-wire host interface operation. 0 = OCM remains in reset until enabled by register bit. 1 = OCM becomes active after OCM_CLK is stable. gm5110/20. Used to allow the OCM or external MCU access configuration settings. 0 = XTAL and TCLK pins are connected to a crystal oscillator. 1 = TCLK input is driven with a single-ended TTL/CMOS clock oscillator. 0 = All 48K of ROM is internal. 32K~48K ROM is external using ROM_ADDR13:0 address outputs. Table 18. Bootstrap Signals requires bootstrap settings as described in Table 18. calibration of the LCD panel. Figure 26. Factory Calibration and Test Environment interface port are always serviced (time division multiplexing).

4.16.1 Host Interface Command Format

one or more data bytes. This is described in Table 19. chosen. By utilizing these modes effectively, registers can be quickly configured. Table 19. Instruction Byte Map the address pointer to increment to the next address location. address pointer to increment to the next address location. is being performed. The gm5110/20 operates as a slave on the interface. The 2-wire protocol requires each device be addressable by a 7-bit identification number. multiple devices that can have the same address.

Note that on the last byte read, no acknowledgement is issued to terminate the transfer. Figure 29. 2-Wire Read Operation (0x9x and 0xAx)

4.17.1 Low Power State

4.17.2 Pulse Width Modulation (PWM) Back Light Control

microcontroller, the gm5110/20 generates these signals directly. light inverter. Panel HSYNC is used as the clock for a counter generating this output signal.

1. ELECTRICAL SPECIFICATIONS

The following targeted specifications have been derived by simulation. Table 20. Absolute Maximum Ratings NOTE (2): Absolute maximum voltage ranges are for transient voltage excursions. is calculated as TC = TJ - P x θJC. This equals 104 degrees Celsius for gm5110 and 106 degrees Celsius for gm5120.

Table 21. DC Characteristics

• 2.5V digital supply (2)
• 2.5V analog supply (3)
• 3.3V digital supply (4)
• 3.3V analog supply (5) I5110 I5110_2.5_VDD I5110_2.5_AVDD I5110_3.3_VDD I5110_3.3_AVDD 400 360(6) 40(6) 50(6) 150(6) mA Supply Current @ CLK =135MHz (gm5120)
• 2.5V digital supply (2)
• 2.5V analog supply (3)
• 3.3V digital supply (4)
• 3.3V analog supply (5) I5120 I5120_2.5_VDD I5120_2.5_AVDD I5120_3.3_VDD I5120_3.3_AVDD 500 500(6) 50(6) 60(6) 150(6) mA Supply Current @ Low Power Mode* ILP 50 mA INPUTS High Voltage VIH 2.0 VDD V Low Voltage VIL GND 0.8 V Clock High Voltage VIHC 2.4 VDD V Clock Low Voltage VILC GND 0.4 V High Current (VIN = 5.0 V) IIH -25 25 µA Low Current (VIN = 0.8 V) IIL -25 25 µA Capacitance (VIN = 2.4 V) CIN 8 pF OUTPUTS High Voltage (IOH = 7 mA) VOH 2.4 VDD V Low Voltage (IOL = -7 mA) VOL GND 0.4 V Tri-State Leakage Current IOZ -25 25 µA NOTE (1): Low power figures result from setting the ADC, DVI, and clock power down bits so that only the micro-controller is running. NOTE (3): Includes only VDD_RXPLL_2.5. NOTE (4): Includes pins VDD_DPLL, VDD_SDDS, VDD_DDDS and RVDD. NOTE (5): Includes pins AVDD_RED, AVDD_GREEN, AVDD_BLUE, AVDD_IMB, AVDD_RX0, AVDD_RX1, AVDD_RX2, AVDD_RXC, AVDD_RPLL, AVDD_SDDS and AVDD_DDDS. NOTE (6): Maximum current figures are provided for the purposes of selecting an appropriate power supply circuit. 55..22 PPrreelliimmiinnaarryy AACC CChhaarraacctteerriissttiiccss The following targeted specifications have been derived by simulation. All timing is measured to a 1.5V logic-swit ching threshold. The minimum and maximum operating conditions used were: TDIE = 0 to 125 ° C, Vdd = 2.35 to 2.65V, Process = best to worst, C L = 16pF for all outputs.

Table 22. Maximum Speed of Operation Table 23. Display Timing and DCLK Adjustments delay between DCLK and its related signals. Table 24. 2-Wire Host Interface Port Timing

* Genesis Microchip Confidential * gm5110/20 Preliminary Data Sheet June 2002 C5110-DAT-01C 43 6. ORDERING INFORMATION Order Code Application Package Temperature Range gm5110 XGA 208-pin PQFP 0-70°C gm5110-H (1) XGA 208-pin PQFP 0-70°C gm5120 SXGA 208-pin PQFP 0-70°C gm5120-H (1) SXGA 208-pin PQFP 0-70°C Note (1): gm5110-H and gm5120-H versions will only be sold to HDCP licensed customers.

1. MECHANICAL SPECIFICATIONS

Figure 30. gm5110/gm5120 208-pin PQFP Mechanical Drawing

0.50 BSC

1.60 REF