GF001H ONSEMI | Alldatasheet
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© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com GF001H • Rev. 1.1 GF001H — Green-Mode Fairchild Power Switch (FPS™) GF001H Green-Mode Fairchild Power Switch (FPS™)
Features
Advanced Burst Mode Operation at No-Load Condition 700 V High-Voltage JFET Startup Circuit Internal Avalanche-Rugged 700 V SenseFET Built-in 5 ms Soft-Start Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Leading-Edge Blanking (LEB) Synchronized Slope Compensation Frequency Modulation to Attenuating EMI Internal Overload / Open-Loop Protection (OLP) VDD Under-Voltage Lockout (UVLO) VDD Over-Voltage Protection (OVP) Internal Auto-Restart Circuit (OLP, VDD OVP) Adjustable Peak Current Limit
Description
The GF001H is a next -generation, Green-Mode Fairchild Power Switch (FPS™). It integrates an advanced current -mode Pulse W idth Modulator (PWM) and an avalanche -rugged 700 V SenseFET in a single package, allowing auxiliary power designs with higher standby energy efficiency, reduced size, improved reliability, and lower sys tem cost than previous solutions. A new frequency modulation reduces EMI emission and built-in synchronized slope compensation allows stable peak-current-mode control over a wide range of input voltage. Requiring a minimum number of external components, the GF001H provides a solid platform for cost -effective flyback converter design with low standby power consumption.
Ordering Information
Part Number SenseFET Operating Temperature Range Package Packing Method GF001HN 2 A 700 V -40°C to +105°C 8-Pin, Dual Inline Package (DIP) Tube
Figure 1. Typical Flyback Application
230 VAC ±15% (2) 85-265 VAC
- The maximum output power can be limited by junction temperature.
- 230 VAC or 100/115 VAC with voltage doublers.
- Typical continuous power in a non-ventilated enclosed adapter, with sufficient drain pattern of printed circuit
board (PCB) as a heat sink, at 50°C ambient.
- Maximum practical continuous power in an open-frame, design with sufficient drain pattern of printed circuit
board (PCB) as a heat sink, at 50°C ambient. Figure 2. Internal Block Diagram
Figure 3. Top Mark Figure 4. Pin Assignment
2 VDD
cycle is determined by comparing the signal on this pin and the internal current-sense signal.
4 IPK
resistor, which determines the current-limit level of pulse-by-pulse current limit. startup. This pin is also used to sense the line voltage for brownout protection.
© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com GF001H • Rev. 1.1 4 GF001H — Green-Mode Fairchild Power Switch (FPS™) Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDRAIN Drain Pin Voltage(5,6) 700 V IDM Drain Current Pulsed(7) 8.0 A EAS Single Pulsed Avalanche Energy(8) 140 mJ VDD DC Supply Voltage 25 V VFB FB Pin Input Voltage -0.3 6.0 V VIPK IPK Pin Input Voltage -0.3 6.0 V VHV HV Pin Input Voltage 700 V PD Power Dissipation (TA＜50°C) 1.5 W TJ Operating Junction Temperature -40 Internally Limited(9) C TSTG Storage Temperature Range -55 +150 C TL Lead Soldering Temperature (Wave Soldering or IR, 10 Seconds) +260 C Notes: 5. All voltage values, except differential voltages, are given with respect to the network ground terminal. 6. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 7. Non-repetitive rating: pulse width is limited by the maximum junction temperature. 8. L = 51 mH, starting TJ = 25°C. 9. Internally limited by Over-Temperature Protection(OTP). Refer to TOTP. Thermal Resistance Table Symbol Parameter Value Unit θJA Junction-to-Air Thermal Resistance 86 C/W ψJT Junction-to-Package Thermal Resistance(10) 20 C/W Note: 10. Measured on the package top surface. ESD Capability Symbol Parameter Value Unit ESD Human Body Model, JESD22-A114(11) All pins excluding HV pin 7 kV All pins including HV pin 3 Charged Device Model, JESD22-C101(11) All pins excluding HV pin 2 All pins including HV pin 2 Note: 11. Meets JEDEC standards JESD 22-A114 and JESD 22-C101.
© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com GF001H • Rev. 1.1 5 GF001H — Green-Mode Fairchild Power Switch (FPS™)
Electrical Characteristics
VDD=15 V, and TA=25°C unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit SenseFET Section(12) BVDSS Drain-Source Breakdown Voltage VDS = 700 V, VGS = 0 V 700 V IDSS Zero-Gate-Voltage Drain Current VDS = 700 V, VGS = 0 V 50 μA VDS = 560 V, VGS = 0 V, TC = 125°C 200 RDS(ON) Drain-Source On-State Resistance(12) VGS = 10 V, ID = 0.5 A 6.0 7.2 Ω CISS Input Capacitance VGS = 0V , VDS = 25 V, f = 1 MHz 550 715 pF COSS Output Capacitance VGS = 0 V, VDS = 25 V, f = 1 MHz 38 50 pF CRSS Reverse Transfer Capacitance VGS = 0 V, VDS = 25 V, f = 1 MHz 17 26 pF td(on) Turn-On Delay VDS = 350 V, ID = 1.0 A 20 50 ns tr Rise Time VDS = 350 V, ID = 1.0 A 15 40 ns td(off) Turn-Off Delay VDS = 350 V, ID = 1.0 A 55 120 ns tf Fall Time VDS = 350 V, ID = 1.0 A 25 60 ns Control Section VDD Section VDD-ON UVLO Start Threshold Voltage 11 12 13 V VDD-OFF1 UVLO Stop Threshold Voltage 5 6 7 V VDD-OFF2 IDD-OLP Enable Threshold Voltage 8 9 10 V VDD-OLP VDD Voltage Threshold for HV Startup Turn-On at Protection Mode 5 6 7 V IDD-ST Startup Supply Current VDD-ON – 0.16 V 30 µA IDD-OP1 Operating Supply Current with Normal Switching Operation VDD=15 V, VFB=3 V 3.8 mA IDD-OP2 Operating Supply Current without Switching Operation VDD=15 V, VFB=1 V 1.8 mA IDD-OLP Internal Sinking Current VDD-OLP + 0.1 V 30 60 90 µA VDD-OVP VDD Over-Voltage Protection 23 24 25 V tD-VDDOVP VDD Over-Voltage Protection Debounce Time 40 105 170 µs HV Section IHV Supply Current Drawn from HV Pin HV=120 VDC, VDD=0 V with 10 µF 1.5 5.0 mA VHV Minimum HV Voltage for VDD being charged to VDD-ON RHV=0 Ω, TA=-40 °C to 105 °C 30 V IHV-LC Leakage Current after Startup HV=700 V, VDD=VDD-OFF1+1 V 10 µA VDC-ON Brown-in Threshold Level (VDC) DC Voltage Applied to HV Pin Through 200 kΩ Resistor 104 114 124 V VDC-OFF Brownout Threshold Level (VDC) 89 99 109 V tUVP Brownout Protection Time 0.8 1.2 1.6 s Continued on the following page…
© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com GF001H • Rev. 1.1 6 GF001H — Green-Mode Fairchild Power Switch (FPS™) Electrical Characteristics (Continued) VDD=15 V, TA=25°C unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit Oscillator Section fOSC Frequency in Nominal Mode Center Frequency 94 100 106 kHz fM Frequency Modulation ±6 kHz fOSC-G Green-Mode Frequency 20 23 26 kHz fDV Frequency Variation vs. VDD Deviation VDD=11 V to 22 V 5 % fDT Frequency Variation vs. Temperature Deviation(12) TA=-40 °C to 105 °C 5 % Feedback Input Section AV Internal Voltage Dividing Factor of FB Pin(12) 1/4.5 1/4.0 1/3.5 V/V ZFB Pull-Up Impedance of FB Pin 15 21 27 kΩ VFB-OPEN FB Pin Pull-Up Voltage FB Pin Open 5.2 5.4 5.6 V VFB-OLP FB Voltage Threshold to Trigger Open-Loop Protection 4.3 4.6 4.9 V tD-OLP Delay of FB Pin Open-Loop Protection 46 56 66 ms VFB-N FB Voltage Threshold to Exit Green Mode VFB is Rising 2.4 2.6 2.8 V VFB-G FB Voltage Threshold to Enter Green Mode VFB is Falling VFB-N -0.2 V VFB-ZDC FB Voltage Threshold to Enter Zero-Duty State VFB is Falling 1.1 1.2 1.3 V VFB-ZDCR FB Voltage Threshold to Exit Zero-Duty State VFB is Rising VFB-ZDC +0.1 V IPK Pin Section VIPK-OPEN IPK Pin Open Voltage 3.0 3.5 4.0 V VIPK-H Internal Upper Clamping Voltage of IPK Pin(12) 3 V VIPK-L Internal Lower Clamping Voltage of IPK Pin(12) 1.5 V IPK Internal Current Source of IPK Pin TA=-40 °C to 105 °C, VIPK=2.25 V 45 50 55 µA ILMT-H Flat Threshold Level of Current Limit for the Highest IPK Level VIPK=3 V 0.90 1.00 1.10 A ILMT-L Flat Threshold Level of Current Limit for the Lowest IPK Level VIPK=1.5 V 0.45 0.50 0.55 A Current-Sense Section(13) tPD Current Limit Turn-Off Delay(14) 100 200 ns tLEB Leading-Edge Blanking Time(14) 160 210 260 ns tSS Soft-Start Time(12) 5 ms GATE Section(13) DCYMAX Maximum Duty Cycle 70 % Over Temperature Protection Section (OTP) TOTP Junction Temperature to Trigger OTP(12) 140 °C Notes: 12. Guaranteed by design; not 100% tested in production. 13. Pulse test: pulse width ≤ 300 µs, duty ≤ 2%. 14. These parameters, although guaranteed, are tested in wafer-sort process.
reaches 12 V, the IC resumes switching operation. Figure 26. Two-Level UVLO
NOTES: A) THIS PACKAGE CONFORMS TOJEDEC MS-001 VARIATION BA WHICH DEFINES B) CONTROLING DIMS ARE IN INCHESC) DIMENSIONSARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5M-2009 E) DRAWING FILENAME AND REVSION: MKT-N08MREV2. 0.4000.355 [10.1609.017] MIN 0.015 [0.381] MAX 0.210 [5.334] 0.1500.115 [3.8112.922]C FULL LEAD STYLE 4XHALF LEAD STYLE 4X 0.10C SEATING PLANE PIN 1 INDICATOR 0.031 [0.786] MIN0.010 [0.252] MIN 8X FOR FULL LEAD STYLE2 VERSIONS OF THE PACKAGE TERMINAL STYLE WHICH ARE SHOWN HERE.
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