GAL22V10-15

GAL22V10-15 NSC | Alldatasheet

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National PRELIMINARY | — Semiconductor = Generic Array Logic General Description Features The NSC E2CMOS™ GAL® devices combine a high per- _™@ High performance E2CMOS technology formance CMOS process with electrically erasable floating — 15 ns maximum propagation delay gate technology. This programmable memory technology —fmax = 50 MHz with feedback applied to array logic provides designers with reconfigurable —8 ns maximum from clock input to data output logic and bipolar performance at significantly reduced pow- — TTL compatible 16 mA outputs er levels. — UltraMOS® III advanced CMOS technology The 24-pin GAL22V10 features 22 inputs, and 10 program- — Internal pull-up resistor on all pins mable Output Logic Macro Cells (OLMCs) allowing each ® Electrically erasable cell technology TRI-STATE® output to be configured by the user. The archi- — Reconfigurable logic tecture of each output is user-programmable for registered — Reprogrammable cells . ‘or combinatorial operation, active high or low polarity, and — 100% tested/guaranteed 100% yields as an input, output or bidirectional I/O. This architecture — High speed electrical erasure (<S0 ms) features variable product term distribution, from 8 to 16 logi- — 20 year data retention cal product terms to each output, as shown in the logic dia- ™ Ten output logic macrocells gram. CMOS circuitry allows the GAL22V10 to consume just — Maximum Flexibility 90 mA typical Ioc which represents a 50% saving in power — Programmable output polarity when compared to its bipolar counterparts. Synchronous — Maximum flexibility for complex logic designs preset and asynchronous reset product terms have been — Full function/fuse map/parametric compatibility with added which are common to all output registers to enhance: PAL22V10 devices system operation. The GAL22V10 is directly compatible ™ Variable product term distribution with the bipolar PAL22V10 in terms of functionality, fuse — From 8 to 16 product terms per output data function map, pinout, and electrical characteristics. @ Synchronous preset and asynchronous reset to all Programming is accomplished using industry standard avail- registers able hardware and software tools. NSC guarantees a mini- ™ Preload and power-up reset of all registers mum 100 erase/write cycles. — 100% functional testability Unique test circuitry and reprogrammable cells allow com- _™ Fully supported by National PLANT™ and other industry plete AC, DC, cell and functionality testing during manutac- standard development software ture. Therefore, NSC guarantees 100% field programmabili- = Security cell prevents copying logic ty of all GAL devices. In addition, electronic signature is available to provide positive device ID. A security circuit is built-in, providing proprietary designs with copy protection. Generic Array Logic Family Number of Array inputs. rao 2 | Output Type: a 2 V = Variable Architecture AS a= Ol an) nero a] Bo 18: tpp = 15ns (Comm) =n Saas 20: tep = 20ns (ind /Mil) | | Et | 25: tpp = 25ns (Comm) oi ga —0) 30: tpep = 30ns —(Ind/Mil) | | | L = Low Power a = Package Type: | | Cea | N = 24-Pin Plastic DIP Cy bet Ferta) J = 24-Pin Ceramic DIP | | era | V = 28-Lead Plastic Chip Carrier (F] eee eg OT Temperature Range: [| Ee] C= Commercial (0°C to +75°C) Cy pre-e) | = Industrial (— 40°C to +85°C) | | | M = Miltary (—55°C to + 125°C) Ce} Eee) GAL 22 V 10 - 15 LNC =a Se. iy am al ae a Lf TUL/10408~2 2-193

& | Absolute Maximum Ratings (note 1) ba | if Military/Aerospace specified devices are required, Ambient Temperature

4 Please contact the National Semiconductor Sales with Power Applied —65°C to + 125°C

© | OfficesDistributors for availability and specifications. Junction Temperature 65°C to + 150°C Supply Voltage (Vcc) (Note 2) —0.5V to +7.0V Lead Temperature Input Voltage (Note 2) —2.5V to Voc + 1.0V (Soldering, 10 seconds) 260°C Off-State Output Voltage (Note 2) —2.5V to Voc + 1.0V ESD Tolerance TBD Output Current +100 mA Czar = toon - zap = 154 Storage Temperature 65°C to + 150°C Test Method: Human B Model Test Specification: NSC SOP-5-028 Recommended Operating Conditions SUPPLY VOLTAGE AND TEMPERATURE symbol [| commercin [tncuntr [mary | ang Pe ee te ee voc | suppyvotage [ars | s [sas [as [ s [es [ as | 5s | se | v Ta___| opwaingrreenrtompoane | 0 [as [75 | <a [a [ os | ss | = | | AC TIMING REQUIREMENTS Symbol le eee eee Unie teu | Set Up Time 12 ns (Input or Feedback before Clock) | Hostinetnonatercoey | o | To [fe | fo [ [on tw [tcerrusewameraniom [so [|e [fs Tf [| oe taw Asynchronous Reset Input Pulse Width ns teycte | Clock Cycle Period (with Feedback) ts (Note 3) feux | GroorFreaveney | winFeodback | | asa [ [aa | | aes || ae | 1 [inpurFrewvoneynoes | ase [| soo [woo [| oa | Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. Proper operation is not guaranteed outside the specified recommended operating conditions. Note 2: Some device pins may be raised above these limits during programming and preload operations according to the applicable specification. Note 3: teycir = tsu + touk Note 4: fox (with feedback) = (teycie)~ ? fcuk (without feedback) = (2 ty) 1 Note 5: f| = (tpp)- 1 2-194

fr) ical Ch isti . . = Electrical Characteristics over Recommended Operating Conditions iS ND Symbol Units. s o Vin | Higntevetinpuvonage | TTT cots |v Yu | towtevetinpurvennge | esos | oe Vou | HahLeveturputvotage | Voc = Min como [2a | | Tv | tow=-20ma | ome [ae |v Vo. | towtevetoupurvotage | voo-Min | i= tema | cowmo | | [os |v [iw=vema | ome Tos JozH High Level Off State Voc = Max, Vo = Voc (Max) A Output Current Las loz Low Level Off State Veco = Max, Vo = GND A Output Current f Maximuminpuicurent | Voc=Mexvi=VectMod [| | aso | | toa tw High Lovelinuturent | Voc=Maxvi= Veco [| | | Tt los" | Output Shor Grout Curent_| Vag = 5.0V. Yo = GND a ee ee tcc | Supply Curent 1 = ISM oo = Max [com TT | sa0 | ima Gi Input Capacitance [ voc=soumez | TT De *One output at a time for a maximum duration of one second. Switching Characteristics over Recommended Operating Conditions | cavzavio-15t | GAL22V10-20L | GAL22V10-25L | GAL22V10-30L_ Symbol Conditions | com | mom | com | inom [units tep Input or Feedback to 'S1 Closed, C, = 50 pF 18 | Combinatorial Output ns to”k Clock to Registered Output /S1 Closed, C, = 50 pF ns jor Feedback tpzxi __|Input to Combinatorial Output} Active High; S1 Open, CL = 50 pF B [Enabled via Product Term __|Active Low; S1 Closed, C, = 50 pF ‘s ‘tpxzi__ [Input to Combinatorial Output| From Voy; $1 Open, C, = 5 pF 18 ns Disabled via Product Term — | From Voi; S1 Closed, C, = 5 pF tap Asynchronous Reset ‘Input to Register ns Output treseT |Power-Up to Registered 'S1 Closed, C, = 50 pF 45 s [Output High a 2-195,

o S &| AC Test Load Ff sw Lo wit " Ri = 390 R2 = 750 oun COM'L/IND: ao 3m A= 200 T 2 = 990 = * TUL/10406-3 Test Waveforms Setup and Hold Pulse Width Ww HIGH@LEVEL id Vy w PULSE INPUT Mr Vr tser-up| Hou DATA ia LOW-LEVEL iNPUT w PULSE INPUT wr TUL/0406—4 TUL/10408-5 Propagation Delay Enable and Disable — OY wv ENABLE wet DVSABLED XN ov INPUT gy =/Not 4 ‘PHL IN-PHASE You OUTPUT Me | vr y wom comet a to (S1 CLOSED) fon “(1 OPEN) Z It teat f= tpn tw OUT OF Phase You NORMALLY LOW - Vy y ‘OUTPUT KC (S1 CLOSED) fo. (st close) Yo ——=F Ov TUL 10406-6 TL/L/10406-7 Notes: © includes probe and jig capacitance. Vr = 1.5V. Test inputs have rise and fall times of 5 ns between 0.3V and 2.7V. In the examples above, the phase relationships between inputs and outputs: have been chosen arbitrarity. 2-196

peur a LIL = ty 4 ° Te a ‘CLOCK / \\ / ‘err — on AsmaHonous meet ‘ww —+| = a a ‘OUTPUT ftax— - e | | OUTPUT TUL 0806-8 Power-Up Reset Waveforms . 0x ce ” tee chock ‘e OOXXXXXKXXXXXXXIO " ‘eeset weSUS DXAXKKKKKEKREKRARKRARAARALY NERA RGSS TUL 0408-8 Input/Output Schematics Phased Output Turn-On Circuit outa ts map ‘TRISTATE : ' peeeeeses | ' 1'2 H H teceeeeet TL/L/10406-11 2-197

o &| Functional Description SJ} The GAL22V10 logic array consists of a programmable paths are redirected with the register selection. The regis- < AND array with fixed OR-gate connections, similar to the tered configurations include an internal feedback path taken So traditional bipolar PAL architecture. The logic array is orga- directly from the register output. The combinatorial configu- nized as 22 complementary input lines crossing 132 “prod- rations include feedback from the 1/O pin, thus allowing for uct term” lines with a programmable E2PROM cell at each bidirectional I/O or additional input channels. intersection (5808 cells). Each programmable cell may es- All registers in a GAL22V10 device are reset to the low state tablish a connection between an input line (true or comple- upon power-up. Outputs, in turn, assume either low or high ment phase of an array input signal) and a product term. A logic levels (if enabled) depending on the selected output product term is satisfied (logically true) while all of the input polarity. Power-up reset may simplify sequential circuit de- lines “connected” to it are in the high logic state. sign and test. To ensure successful power-up reset, Voc Of the 132 product terms, 130 are distributed among ten must rise monotonically until the specified operating voltage “output logic macrocells” (OLMCs) with a varying number of is attained. During power-up, the clock input should assume terms allocated to each OLMC (as shown in Figure 7). The a valid, stable logic state as early as possible (within the ten OLMCs control the flow of input and output signals be- ‘specified time, tp) to avoid interfering with the reset opera- tween the logic array and the device's I/O pins. For a given tion. The clock input should also remain stable until after the OLMC, 8, 10, 12, 14 or 16 product terms feed into an OR- power-up reset operation is completed to allow the registers gate to produce each output value. This varied distribution to capture the proper next state on the first high-going clock of product terms among outputs allows more optimum use transition. of device resources. One additional product term in each of It should be noted that the switching of any input not logical- the ten OLMCs is used to control the associated TRI- ly connected to a product term or logic function has no ef- STATE device output. One global product term is used to fect on the associated output logic state. To minimize power control an asynchronous preset, and another global product consumption, however, unused inputs should be connected term is used for a synchronous reset, and both are connect- to a stable logic level such as ground or Vec (CMOS GAL ed to alll ten of the output registers. inputs may be tied directly to the supply voltage without The fundamental transfer function of each GAL22V10 out- causing excessive loading conditions). put is the familiar Boolean sum-of-products. Design devel- ‘opment software is available which accepts Boolean equa- Programmable Preset and Reset tions and converts them automatically into GAL22V10 pro- The ten macrocel! flip-flops share common programmable gramming patterns. preset and reset control for easy system initialization. The Q Under control of an OLMC, each output may be designated outputs of the register will go to the logic high state follow- either registered or combinatorial (non-registered). In the ing a low-to-high transition of the clock input when the syn- registered output configuration, the logic function output chronous preset (SP) product term is asserted. The register passes through a D-type flip-flop triggered by the rising will be forced to the logic low state independent of the clock ‘edge of the clock input. Additionally, the logic function's out- when the asynchronous reset (AR) product term is asserted. put polarity may be designated active-low or active-high (ad- Product term control allows preset and reset to be functions justed after the register, if present). OLMC options such as of any combination of device inputs and output feedback. these are selected using a set of programmable architec- The outputs will be high or low depending upon the polarity ture control cells. These architecture cells are normally con- option chosen. figured automatically by the development software or pro- Note that preset and reset control the flip-flop, not the out- gramming hardware. put. Thus, if active low polarity is selected, a synchronous The four possible |/O configurations of each GAL22V10 Preset would produce low-level outputs, and an asynchro- OLMC are: registered-active low, registered-active high, Nous reset would produce high-level outputs (if enabled). combinatorial-active low, and combinatorial-active high. These combinations are shown in Figure 3. The feedback 2-198

GAL22V 10 Block Diagram—DIP Connections fa Vv, o in = 1 [3] oo (27) fo Pf} ea | eh B sa] ow vo V8 =o 2) v0 Cia || Ba 1 i7) [el foes rig] 1231 1/0 Pf ae 1 (9) =n Anny eee [21] Vo 1 110) ae ef (20) 1/0 a ran ~~ ef is] 191 Yo “Ta | Ta 2_| L PLCC PiN NUMBERS id PCC Pin Numbers FIGURE 1 2-199

=| 28-Lead PLCC Connection Diagram nN z 11 Cl Vec 1/0 1/0 6 24-PIN DIP —> Nc jesew or — [3] [2] G] ve Ba) 23) [sH2H * HesH2zH2s AE fl vo ‘BE eq fq vo iol El ve 28= LEAD PLCC ne [8] (TOP VIEW) [22] xc ‘oe El ve ') ba eq [2] v0 ‘Bw [3] Es] v0 2H SH 4H SH sh 7} {18} HE 3

1 Yo ¥o

' 1 wo v Vv ‘TL/L/10406-13 FIGURE 2 file can be down-loaded into industry standard programming Clock/Input Frequency equipment. Many software packages and programming Specifications units support a multitude of programmable logic products as The clock frequency (foLK) parameter listed in the Recom- well. The PLAN software package from National Semicon- mended Operating Conditions table specifies the maximum ductor supports all programmable logic products available speed at which the GAL22V10 registers are guaranteed to from National and is fully JEDEC-compatible. PLAN soft- operate. Clock frequency is defined differently for the two ware also provides automatic device selection based on the cases in which register feedback is used versus when it is designer's Boolean logic equations. not. In a data-path type application, when the logic functions National strongly recommends using only approved pro- fed into the registers are not dependent on register feed- gramming hardware and software for developing GAL de- back from the previous cycle (ie. based only on external signs. Programming using unapproved equipment generally inputs), the minimum required cycle period (foLk~1 without voids all guarantees. Approved programmers incorporate feedback) is defined as the greater of the minimum clock specialized programming algorithms that program the array Period (ty high + ty low) and the minimum “data window” and automatically configure the architecture cells. To en- period (tsy + ty). This assumes optimal alignment between sure data retention and reliability, the programming algo- data inputs and the clock input. in sequential logic applica- rithm also tracks the number of programming cycles to tions such as state machines, the minimum required cycle which each GAL device has been subjected since shipment, period (tcvoLe = fcLk~' with feedback) is defined as tok and stores this information automatically in the device. + tgy. This provides sufficient time for outputs from the The GAL22V10 can accept fuse-maps prepared for other ragisters to feed back through the logic array and set up on PAL22V10 devices. PAL22V10 fuse-maps can be created the inputs to the registers before the end of each cycle. by any JEDEC-compatible PAL development software or by The input frequency {f)) parameter specifies the maximum loading the fuse pattem from an existing programmed rate at which each GAL22V10 input can be toggled and still PAL22V10 device into the programming unit (provided the produce valid logic transitions on each combinatorial output. PAL device has not been secured). The f| specification is derived as the inverse of the combina- Detailed logic diagrams showing all JEDEC cell-map ad- torial propagation delay (tpp). dresses in the GAL22V10 logic array and OLMC are provid- : ed for direct map editing and diagnostic purposes. Figure 6 Design Development Support and Table II show details of the OLMC and the programma- A variety of software tools and programming equipment are ble architecture cell combinations. Figure 7 shows the available to support the development of designs using JEDEC logic diagram and details of all programmable cell GAL22V10 products. Typical software packages, including focations. For a list of current software and programming National's PLAN software, accept Boolean logic equations support tools available for these devices, please contact to define desired functions. Most are available to run on your local National sales representative or distributor. If de- personal computers and generate a JEDEC-compatible tailed specifications of the GAL22V10 programming algo- “cell-map” (analogous to a PAL “fuse-map”). The industry- rithm are needed, please contact the National Semiconduc- standard JEDEC format ensures that the resulting cell-map tor Programmable Device Support department. 2-200

=| Security Cell high-temperature bake. All DC and AC parameters are test- Fs] ; " ; ed at hot and cold temperatures using a variety of worst- =1| A security cell is provided on all GAL22V10 devices as a case logic and signal patterns. Functional tests include re- ‘Z| __ deterrent to unauthorized copying of the array configuration programming each OLMC to all valid architectural configura- © | patterns. Once programmed, the circuitry enabling array ac- tions. cess is disabled, praventing further programming or verifica- tion of the array. The security cell can be erased only in conjunction with the array during a bulk erase cycle, so the Register Preload original configuration can never be examined once this cell The register preload feature allows OLMC registers to be Is programmed. directly loaded with any desired data pattern. It also allows the present state of OLMC registers to be examined regard- less of TRI-STATE control conditions. This simplifies testing Electronic Signature . of devices after programming. A device may be put into any Each GAL device contains an electronic signature word desired register state at any point during the functional test consisting of 64 bits of reprogrammable memory. The elec- sequence. The test sequence may then be resumed to veri- tronic signature word can be programmed to contain any fy proper next-state transitions. This allows complete verifi- identification information desired by the user. Some uses cation of sequential logic circuits, including states that are include pattern identification labels, revision numbers, normally impossible or difficult to reach. It may also shorten dates, inventory control information, etc. The data stored in the overall test time significantly. ‘the electronic signature word has no effect on the function- , a ality of the device. The information is read out of the device See cal noncluone tor tha device boino texted To vont thea the normal Program verification Procedure provided by these transitions requires the ability to set the state registers Prog 1g equipment. y Be ac into an arbitrary “present state” value, and to set the device cessed at any time independent of the state of the security inputs to any arbitrary “present input” value, Once this is cell. National's PLAN development software allows elec- ce bs . - tronic signature data to be entered by the user and down- done, the state machine is then clocked into a new state, or loaded to the programming equipment. ‘next state.” The next state is then checked to validate the transition from the present state. In this way any state tran- sition can be checked. Bulk Erase , i " - Register preload is not an operational mode and is not in- The programming equipment automatically performs a bulk tended for board-level testing because elevated voltage lev- erase operation prior to each programming operation. No els must be applied to the device. The programming equip- special erase operation need be performed by the user. ment normally provides the register preload capability as Bulk erase clears the logic array, architecture cells, security part of its functional test facility. Note that the testing of GAL ceil, and electronic signature information. The GAL device is devices after programming by the user may be considered thereby reverted back to its virgin state. unnecessary because all E2CMOS GAL products are com- . pletely tested by the manufacturer, guaranteeing 100% Latch-Up Protection post-programming functional yield. GAL devices are designed with an on-chip charge pump to The register preload algorithm is described for those users negatively bias the substrate. The negative bias is of suffi- who wish to test programmed GAL devices using test equip- cient magnitude to prevent input undershoots from causing ment other than approved GAL programming equipment. As the circuitry to latch. Additionally, outputs are designed with shown in the register preload waveform in Figure 5, the pre- n-channel pullups instead of the traditional p-channel pull- load sequence must not begin until the normal power-up ups to eliminate any possibility of SCR induced latching. reset operation has completed (after time taeset). The de- vice is placed into preload mode by raising the “PRLD” in- Manufacturer Testing put (pin 13*) to voltage Vies, a8 specified in the register Because of E2CMOS technology, GAL devices can be re- preload specifications (Table |). programmed in milliseconds. This allows each device to be To preload the OLMC registers, a series of data bits are completely tested by the manufacturer using numerous log- shifted into the device on the “Spi” input (pin 11*), one bit ic array and architecture patterns prior to shipping. Every for each OLMC in which registered output has been select- programmable cell and every logic path through every de- ed. (Non-registered OLMCs are bypassed.) The shift se- vice is fully tested for programmability, functionality and per- quence is clocked by the rising edge of the “Dc.” input formance to all AC and DC parameters. The customer can (pin 1*). The data stream is shifted in through the registered therefore expect 100% programming and functional yield OLMC with the lowest corresponding pin number, and then and 100% compliance of all GAL products to datasheet “upward” through all remaining registered OLMCs in pin- specifications. number ascending order. Therefore, the first data bit in the The testing procedure performed on all GAL devices by the series is ultimately loaded into the registered OLMC with the manufacturer tests all aspects of device operation. Exten- highest corresponding pin number, as shown in Figure 4. sive testing of all programmable cells in the device include “Applies to 24-pin DIP packages for GAL22V10; refer to the 28-lead PCC margin testing, internal verify, and program retention during Connection Diagram for conversion. 2-202

o & | OLMC Logic Diagram S| = q Gt ouwc oy ' ' be ' ' ' Lm dE ct tane | Pm, Oi a ty Def tine ch aR ARRAY oa 00 P n= 8, 10, 12, 14, of 16, mr CE PG ° ee FUL/10406-20 FIGURE 6 TABLE Il [si] so | output conriguration t) Registered/Active Low

1 Registered/Active High

Ly} Combinatorial/Active Low

1 Combinatorial/Active High

g GAL22V 10 Logic Diagram c OP Pm mowers OP Pw WOMEERS, Nn i PROUT Fea, MBS = <

1 Yee o

afs |sfz ope 3 i. nt nani ar {af _ ee Soir | | wi | 2 ch oo ey SSS SSS SSS SHS SSE ie) SHS SSS SS SSS SSS: Pp 21 oe Sd eT Tr a a SSS SSS SSS SSS SSe Pp 20 ee SSS SS SS SSS SSS ‘ em | nse i | = SS SS SS SS SS SSS: Ve SSS SSS SSS SSIS Se nr on a ee SSS SSS SS SI SSs) SSS SS SS SS SS SSE mr 18 ‘ SS ES SS SS es | se TST er A ws i a so Se 0 TT at

8 SS rt 2

_ es ri A | won 3 TT US ShilSsiiS . 1 | I | mu ae " = 3 12 a thd a om ro: son wm ton = JEDEC Logic Array Cell Numbers = Product Line First Cell Number + Input Line Numbers FIGURE 7 2-205