Logic IC

GAL20V8A-10

National Semiconductor ...

Generic Array Logic

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GAL20V8A-10, -12, -15, -20 3 3 7 9 cd " . ; Generic Array Logic 8 General Description Features Ft The NSC E2CMOS™ GAL® device combines a high per- _™ High performance E2CMOS technology bf formance CMOS process with electrically erasable floating — 10 ns maximum propagation delay 8 gate technology. This programmable memory technology —feik = 62.5 MHz applied to array logic provides designers with reconfigurable. © — 8 ns maximum from clock input to data output logic and bipolar performance at significantly reduced pow- — TTL compatible 24 mA outputs er levels. — UltraMOS8 Il advanced CMOS technology The 24-pin GAL20V8A features 8 programmable Output ™ 36% reduction in power Logic Macrocelis (OLMCs) allowing each TRI-STATE® out- —115 mA max Iog Put to be configured by the user. Additionally, the @ Electrically erasable cell technology GAL20V8A is capable of emulating, in a functional/fuse — Reconfigurable logic map/parametric compatible device, the most popular 24-pin — Reprogrammable cells PAL® device architectures. — 100% tested/guaranteed 100% yields Programming is accomplished using readily available hard- — High speed electrical erasure (<50 ms) ware and software tools. NSC guarantees a minimum 100 _ — 20 year data retention erase/write cycles. @ Eight output logic macrocells Unique test circuitry and reprogrammable cells allow com- Maximum oaoitty {or complex logic designs Plete AC, DC, cell and functionality testing during manutac- frowrammable output polanty | mnction/ ture, Therefore, NSC quarantees 100% field programmabil., fk Baus Bé-pin PAL devices with full function ty of the GAL devices. In addition, electronic signature is luse map/parametric compatibility available to provide positive device ID. A security circuit is Preload and power-up reset of all registers built-in, providing proprietary designs with copy protection. — 100% functional testability ™ Fully supported by National PLAN™ development software ™ Security cell prevents copying logic '§ Electronic signature for identification @ Same JEDEC map as GAL20V8 I map OS GAVE PAL Replacement by Device Type Block Diagram—GAL20V8A “Small “Registered “Medium PAL” Mode PAL” Mode __|PAL” Mode| +h 124] 14L8] 16L6] 18L4)20L2| 20R8 | 20R6 | 20R4 20L8 re] | 123] 14H8]16H6| 18H4|20H2/20RP8|20RP6I20RP4| 20H8 |_| Rea 14P8] 16P6] 18P4| 20P2| 20P8 an fo -—3 | ere PAL Replacement by Speed/Power + aise 2 | nigewe Speed | Clee Poot Ee Version | an pe satay D 10ns 180 mA 40L (115 mA) a Oa a 118] D(MIL) 15ns 180mA | 151 (140 mA) a rt | b2 15ns 105mA | 15L.(115mA) [2] Hes 1:7] B 15 ns 180 mA 15L (115 mA) =e ninse= D2 (MIL) | 20ns | 105mA | 20L(140mA) B | B (MIL) 20ns | 180mA | 20L.(140mA) a Ls, i a LEOLE TW/L/10000-1 2-177

ig| Absolute Maximum Ratings (ote 1) Ly If Military/Aerospace specified devices are required, Ambient Temperature a please contact the National Semiconductor Sales with Power Applied —65°C to + 125°C = | Office/Distributors for availability and specifications. Junction Temperature 65°C to + 150°C s ‘Supply Voltage (Vcc) —0.5V to +7.0V Lead Temperature | _ Input Voltage (Note 2) ~2.8V to Voc +1.0V (Soldering, 10 seconds) 260°C © | _Oft-State Output Vottage (Note 2) —2.5VtoVoc +1.0V ESD Tolerance 500V © | Output Current +100 mA Bzar = er = ZAP = a Storage Temperature 65°C to + 150°C TaN ethed: Haman Body Model o) Test Specification: NSC SOP-5-028 Rev. C Recommended Operating Conditions ‘SUPPLY VOLTAGE AND TEMPERATURE symbol Pre |e ete eta [min [tye [wax [wn [tye [max [aan | tye | mex | voc | suppyvotage | avs | 5 [sas | as | s [ss | os | 5 | ss |v ta | Operingreeartoneanre | 0 | 2 | 75 | -«o | a | os | -ss | os | | AC TIMING REQUIREMENTS [cnzovenctou [| catzoveasar | carzoveais. | catzoverzot | com tsu Set-Up Time 42 ns (Input or Feedback before Clock) tu _[Hoatinetnpuranorcecy | o | | o [| oo | fo [| ww _[ooaPucewancimon fe | | e | | w | [2 | [os tercie | Clock Cycle Period (with Feedback) hs (Note 3) 1s taux | iockFrequoncy [win Feedback | [ses | | wo | [| ae | | saa | woe) [winourrooax| | ezs [| eas | | ooo [| ae | we i [rowrrownoywoes | | tooo | | waa | | os || x0 | wa _[Ooavaidaterronerus | [so [| wo [| wo | | i | *Preliminary Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. Proper operation is not guaranteed ‘outside the ‘specified recommended operating conditions. Note 2: Some device pins may be raised above these limits during programming and preload operations according to the applicable specification. Note 3: tcycte = teu + teix Note 4: fcix (with feedback) = (tcycie)” ! fcuk (without feedback) = (2 ty)~ 1 Note 5: f) = (tpp)~ 1 2-178

4 Meximuminewcurent | Voo=MaxvizVeomey | [TT tena

&.| AC Test Load v x Z. wit a w a Ri = 390 id a R2 = 750 = pur COML/IND Rt = 200 $ Tt er) => + + 8 = rss10000-10 a 6| Test Waveforms Setup and Hold Pulse Width TIMING 3V HIGH@LEVEL INPUT, ial ov PULSE INPUT ‘t Vr tser-vr| tou DATA Y \\ av INPUT LOW-LEVEL u Y ‘Ov PULSE INPUT Amy TL/L/10000~11 TLL/10000-12 Propagation Delay Enable and Disable yo wv wour ous Bsa ov ov i te noes a VN You NORMALLY HIGH Voy F: rt ogy v, ‘OUTPUT ¥ . (S1 CLOSED) ran oa fou (s1 OPEN) Z t ‘OUT OF PHASE y, fez teuz. (s+ ose} uae Ve ‘omtouror vena osv ‘OL (s1 cLosep) You + 08 TLL/10000-13 TL/L/10000-14 Notes: C, includes probe and jig capacitance. Vr = 1.5V. Test inputs have rise and fall times of 5 ns between 0.3V and 2.7V. in the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily. 2-180

wweuts (11/0) XXX) RXXXXKX vaio WPUEXKXKXKXKVALW MPUTXXKXKRARKAXXRRANK 4 tu 4 Ww tw a feyoLe: ny 5 4 [ok va s RI v i i ED 8 ANY INPU' Prostate For ee Co er ‘TRI“STATE CONTROL % ‘pai em omen UTPUTS MAXXSKAXKAXXKK CCS TL/L/10000~15 Power-Up Reset Waveforms ¥ 90% cc ” tor Vv Lock." XRXRXXXKKXXXXKX) IL tesset MpuTPUTS SX MKRKKRRKKXXAXKXAAAERAKAY WEA REBT TU/L/10000-16 Input/Output Schematics Input Translator/Bufter cy | O34 INPUT ental Q%p 3 y 2 TL/L/10000-17 2-181

N is| Input/Output Schematics (continues * Phased Output Turn-On Circult g A Ss = DATA s a; J N a o aL) ‘ ' | ‘ ' ‘ H ' ' ar H H t ‘ TRISTATE ‘ : VV ‘ ‘ ‘ : poor le ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ H H ‘ ' ' ' 4 4 ' ‘ ‘ ‘ frerneces TL/L/10000-18

Ordering Information

Generic Array Logic Family Number of Array Inputs Output Type: V=Variable Architecture Number of Outputs Second Generation GAL Technology Speed: 10:tpp=10ns* 12:tpp = 12ns 15: tpp = 15ns 20: tpp = 20ns** L = Low Power (115 mA for GAL20V8A devices) Package Type: N=24=Pin Plastic DIP J=24=Pin Ceramic DIP V=28-Lead Plastic Chip Carrier Temperature Range: C=Commercial (0°C to +75°C) 1 = Industrial (-40°C to +85°C) M=Military (-55°C to +125°C) GAL 20 V 8A- 15 LNC TL/L/10000-2 *-10 and -20 devices are Preliminary. **-20 devices are Military only. 2-182

Q Functional Description Fa The GAL logic array consists of a programmable AND array “OUTPUT” represents the always-active combinatorial out- | & with fixed OR-gate connections, similar to the bipolar PAL put configuration available in the “‘Small-PAL” mode. "REG- | & architecture. The logic array is organized as 20 complemen- ISTER” is the registered output with register feedback avail- | > tary input lines crossing 64 “product term” lines with a pro- able in the “Registered-PAL” mode. I/O” is the combina- | grammable E2PROM cell at each intersection (2560 cells). torial bidirectional 1/O available in “Registered-PAL” and | 2 Each programmable cell may establish a connection be- “Medium-PAL” modes. “TRI-STATE” is the TAFSTATE | ta tween an input line (true or complement phase of an array combinatorial output function appearing on pins* 15 and 22. | input signal) and a product term. A product term is satisfied in the “Medium-PAL” mode. “INPUT” in Table Idenotesan | a (logically true) while all of the input lines “connected” to it OLMC used as a dedicated input only. s are in the high logic state. In the “Small-PAL” and “Medium-PAL” modes (Table |), © The 64 product terms are organized into eight output groups pins* 1 and 13 are always dedicated inputs. In the “Regis- | © with eight terms each. Seven or eight of the product terms in tered-PAL” mode, however, pin* 1 becomes the clock input each output group feed into an OR-gate to produce each controlling all OLMC registers, and pin* 13 becomes the ‘output logic function; one of the product terms may instead output enable (G) input controlling the TRISTATE outputs be used to control the associated TRI-STATE device output. of all registered OLMCs. Within the “‘Small-PAL” and “Reg- The fundamental transfer function of each GAL output is the istered-PAL” modes in Table |, the functions of pins* 15 familiar Boolean sum-of-products. Design development soft- through 22 can be selected individually from either of the ware is available which accepts Boolean equations and two functions listed. For example, in “Registered-PAL” converts them automatically into GAL programming pat- mode, pins* 15 through 22 can each be designated as ei- tems. ther a registered output or a combinatorial I/O. The “Medi- As shown in the GAL20V8A Block Diagram (Figure 1), a um-PAL” mode represents a single fixed configuration used tota! of eight output logic functions are available. Each of to emulate combinatorial medium PAL devices (20L8, 20H8, the AND/OR logic functions feeds into an “output logic 20P8). macrocell” (OLMC). The eight OLMCs control the flow of Table II lists the bipolar PAL products which the GAL20V6A input and output signals between the logic array and the can emulate, and the specific input/output configurations device's 1/0 pins. used. This is just a subset, however, of all the configurations Under control of an OLMC, each output may be designated Provided in Table |. either registered or combinatorial (non-registered). In the All registers in a GAL device are reset to the low state ‘upon registered output configuration, the logic function output power-up. The active-low outputs, in turn, assume high logic passes through a D-type flip-flop triggered by the rising levels (if enabled) regardless of the selected output polarity. ‘edge of the clock input. Additionally, the logic function’s out- This may simplify sequential circuit design and test. To en- put polarity may be designated active-low or active-high (ad- sure successful power-up reset, Voc must rise monotonical- justed before the register, if present). OLMC options such ly until the specified operating voitage is attained. During as these are selected using a set of programmable architec- power-up, the clock input should assume a valid, stable log- ture control cells. These architecture cells are normally con- ic state as early as possible (within the specified time, tpa) figured automatically by the development software or pro- to avoid interfering with the reset operation. The clock input gramming hardware. should also remain stable until after the power-up reset op- All of the possible /O configurations of the GAL20V8A are eration is completed to allow the registers to capture the classified into three basic modes: “Small-PAL” mode, proper next state on the first high-going clock transition. “Registered-PAL” mode and “Medium-PAL” mode. These It should be noted that the switching of any input not logical- Modes correspond to the architectures of the PAL families ly connected to a product term or logic function has no ef- which the GAL20V8A can emulate. The modes determine fect on the associated output logic state. To minimize power the mixture of OLMC configurations which can be selected consumption, however, unused inputs should be connected for the device. The OLMC Selection table (Table |) lists to a stable logic level such as ground or Voc (CMOS GAL which functions can be selected on device pins* 1, 13 and inputs may be tied directly to the supply voltage without 15 through 22 for each of the three modes. The logic dia- causing excessive loading conditions). grams in Figure 3 illustrate these OLMC functions. * Applies to 24-pin DIP packages for GAL2OVBA; refer to the 28-lead POC Connection Diagram for conversion. 2-183

2 GAL20V8A Block Diagram—DIP Connections

oS et (2) [1] (28) Vee 3 | ee 5 1 (3) eT] Abe (2 wana 1 5] a fone ep P21] (28) 1/o Trot | 1 (6) aw El Ets (24) YO hot 1 71 fe] Phew ib fi9| (231 1/0 ‘i =a P| ae er | 1 (9) Penn ps jig} (211 1/0 || tee 1 [10] 1 meeS eco [20] 1/0 rt | 1 oof ao Phe ris] (19) 1/0 ht | 1 112) = eae 118) 1/0 1 3) [ttf L_ qt p14] 17) LE GND 14) 116) GI — [Puce PIN NUMBERS ] id naune1 raeoo-t8 2-184

. > 28-Lead PLCC Connection Diagram S -.3 #_¢g s 24= PIN —> Nc = zen — [3] 2] ea s NUMBERS [sH2H * Hest2729 FS

1 Yo U

4 é ‘Oo Fa BY vo 3 ‘Bl 3) [3] vo 28=LEAD PLCC NC ne [8] (TOP VIEW) B OB Fl [a] ve 'B) bo E29] [7] vo 'B) by Es] [is] vo D2HSHbisHisHi7}{} He « BE ~~ 2 7 & TL/L/10000-20 FIGURE 2 ming equipment. Many software packages and program- Clock/input Frequency ming units support a large variety of programmable logic Specifications products as well. The PLANT™ software package from Na- The clock frequency (fcLk) parameter listed in the Recom- tional Semiconductor supports all programmable logic prod- mended Operating Conditions table specifies the maximum ucts available from National and is fully JEDEC-compatible. speed at which the GAL registers are guaranteed to oper- PLAN software also provides automatic device selection ate. Clock frequency is defined differently for the two cases based on the designer's Boolean logic equations. in which register feedback is used versus when itis not. Ina National strongly recommends using only approved pro- data-path type application, when the logic functions fed into gramming hardware and software for developing GAL de- the registers are not dependent on register feedback from signs. Programming using unapproved equipment generally the previous cycle (i.e. based only on external inputs), the voids all guarantees. Approved programmers incorporate minimum required cycle period (foLx~1 without feedback) is specialized programming algorithms that program the array defined as the greater of the minimum clock period (ty high and automatically configure the architecture cells. To en- + ty low) and the minimum “data window” period (tsy + sure data retention and reliability, the programming algo- ty). This assumes optimal alignment between data inputs rithm also tracks the number of programming cycles to and the clock input. In sequential logic applications such as which each GAL device has been subjected since shipment, ‘state machines, the minimum required cycle period (teyoLe and stores this information automatically in the device. = fcux~! with feedback) is defined as tok + tgy. This The special GAL programming algorithm can also program Provides sufficient time for outputs from the registers to @ GAL device using a standard fuse-map developed for any 2 | feed back through the logic array and set up on the inputs to of the emulated PAL products. PAL fuse-maps can be creat- the registers before the end of each cycle. ed by any JEDEC-compatible PAL development software or The input frequency (f)) parameter specifies the maximum by loading the fuse pattern from an existing programmed rate at which each GAL input can be toggled and still pro- PAL device into the programming unit (provided the PAL duce valid logic transitions on each combinatorial output. device has not been secured). However, to utilize the full The f; specification is derived as the inverse of the combina- flexibility of the GAL architecture, true GAL development torial propagation delay (tpp). software (such as PLAN software) is recommended. Detailed logic diagrams showing all JEDEC cell-map ad- Design Development Support dresses in the GAL logic array and OLMC are provided for A variety of software tools and programming equipment is direct map editing and diagnostic purposes (see “Program- available to support the development of designs using GAL ming Details”). For a list of current software and program- products. Typical software packages accept Boolean logic ming support tools available for these devices, please con- equations to define desired functions. Most are available to tact your local National sales representative or distributor. If run on personal computers and generate a JEDEC-compati- detailed specifications of the GAL programming algorithm ble “cell-map” (analogous to a PAL “fuse-map"). The in- are needed, please contact the National Semiconductor dustry-standard JEDEC format ensures that the resulting Programmable Device Support department. ceil-map file can be down-loaded into a variety of program- 2-185

N g| OLMC Selection Table a 7 TABLE! s “4 ” = “Small-PAL” Mode “Registered-PAL” Mode Medlum PAL s INPUT CLOCK INPUT 5 ; wy, cs 124) Yoo F: iy ai ei Z| —> INPUT or OUTPUT* REGISTER or 1/O TRI-STATE** cs —> INPUT or OUTPUT* REGISTER or I/O vo wes o—> INPUT or OUTPUT* REGISTER or I/O vo 1 i}—> OUTPUT* REGISTER or I/O vo ea 3—> OUTPUT* REGISTER or I/O vo iy f3——> INPUT or OUTPUT* REGISTER or 1/0 vo vo ]——> INPUT or OUTPUT* REGISTER or I/O vo | s]—> INPUT or OUTPUT® REGISTER or I/O TRI-STATE** iy ti4) | ono (124 }3— INPUT OUTPUT ENABLE G) INPUT * Active combinatorial output TLL/10000-21 ‘**TRI-STATE combinatorial output Note: Pin numbers above apply to 24-pin DIP packages; refer to the 28-lead PCC Connection Diagram for conversion. PAL Replacement Configurations TABLE Il a ce, INPUT iNPUT INPUT WNPUT CLOCK ‘CLOCK CLOCK INPUT qd - fb. ig bs: mes —> OUTPUT*| INPUT INPUT INPUT | REGISTER vo vo TRESTATE** iq J——» | OUTPUT*|OUTPUT*| INPUT INPUT | REGISTER | REGISTER vo vO ig P51——> | OUTPUT*| OUTPUT*} OUTPUT*| INPUT | REGISTER | REGISTER | REGISTER vo gq i——> OUTPUT® | OUTPUT® | OUTPUT? | OUTPUT® | REGISTER | REGISTER | REGISTER vo iq f)——> | OUTPUT* | OUTPUT* | OUTPUT? | OUTPUT® | REGISTER | REGISTER | REGISTER vo q w—> OUTPUT* | OUTPUT* | OUTPUT*| INPUT | REGISTER | REGISTER | REGISTER vo iq w—> OUTPUT*| OUTPUT*| INPUT INPUT | REGISTER | REGISTER “vo vo op i o— OUTPUT*| INPUT INPUT INPUT | REGISTER vo vo TRI-STATE** ood —_ INPUT | INPUT | INPUT | INPUT ij G ic] (NPUT TL/t/10000-22| 14L8 1616 18L4 2012 20R8 20R6 20R4 2018 Emulated: 14H8 16H6 18H4 20H2 20RP8 ‘20RP6 ‘20RP4 20H8 PAL Products 14P8 16P6 18P4 20P2 ‘20P8 * Active combinatorial output. **TRI-STATE combinatorial output. Note: Pin numbers above apply to 24-pin DIP packages; refer to the 28-pin PCC Connection Diagram for conversion. 2-186

OUTPUT (Active Combinatorial Output) Ss

5 Polarity co

TL/L/10000~28 & REGISTER (Registered Output)

3 Polarity

ano LU 5° po—LPn] Array 0 > c 3 0 TLIL/10000-24 1/0 (Combinatorial Input/Output) Pp Py ~ y 0 mr < TL/s10000-25 TRI-STATE (TRI-STATE Combinatorial Output) ; Polarity AND } > 26 anay > 0 -po—] De 2 | TL/L/10000-26 FIGURE 3 2-187

Programmable cell and every logic path through every de- Py Security Cell - ; vice is fully tested for programmability, functionality and per- 7 A security cell is provided on all GAL20V8A devices as a formance to all AC and DC parameters. The customer can v deterrent to unauthorized copying of the array Configuration therefore expect 100% programming and functional yield "| Patterns. Once programmed, the circuitry enabling array ac- and 100% compliance of all GAL products to datasheet cs cess is disabled, preventing further programming or verifica- specifications. = tion of the array. The security cell can be erased only in The testing procedure performed on all GAL devices by the S _|__ conjunction with the array during a bulk erase cycle, 80 the manufacturer tests alt aspects of device operation. Exten- g original configuration can never be examined once this cell sive testing of alt programmable celis in the device include § is programmed. margin testing, internal verify, and program retention during high-temperature bake. All DC and AC parameters are test- $ Electronic Signature ed at hot and cold temperatures using a variety of worst- Each GAL device contains an electronic signature word case logic and signal patterns. Functional tests include re- consisting of 64 bits of reprogrammable memory. The elec- programming each OLMC to all valid architectural configura- tronic signature word can be programmed to contain any tions. identification information desired by the user. Some uses include pattern identification labels, revision numbers, Register Preload dates, inventory control information, etc. The data stored in a . the electronic signature word has no effect on the function- Groot ie wrth ary dearad eta pattern flee sone ality of the device. The information is read out of the device the present state of OLMC registers to be ined using the normal program verification procedure provided by less of TRI-STATE contro! fegiste 8. This simplifies testing the programming equipment. The information may be ac- of devices after ming. A device mey De put into any cessed at any time independent of the state of the security desired register oat any pol int during the functional test cell. National's PLAN development software allows elec- ence. The test then be resumed to veri- tronic signature data to be entered by the user and down- fy eroper next state tenattions This allows comuste youth. loaded to the programming equipment. cation of sequential logic circuits, including states that are normalty impossible or difficult to reach. It may also shorten Bulk Erase the overall test time significantly. The programming equipment automatically performs a bulk Register preload is not an operational mode and is not in- erase operation prior to each programming operation. No tended for board-level testing because elevated voltage lev- special erase operation need be performed by the user. els must be applied to the device. The programming equip- Bulk erase clears the logic array, architecture calls, security ment normally provides the register preload capability as Cell, and electronic signature information. The GAL device is part of its functional test facility. Note that the testing of GAL thereby reverted back to its virgin state. devices after programming by the user may be considered unnecessary because all E2CMOS GAL products are com- Latch-Up Protection Pletely tested by the manufacturer, guaranteeing 100% GAL devices are designed with an on-chip charge pump to Post-programming functional yield. negatively bias the substrate. The negative bias is of suffi- The register preload algorithm is described for those users cient magnitude to prevent input undershoots from causing who wish to test programmed GAL devices using test equip- the circuitry to latch. Additionally, outputs are designed with ment other than approved GAL programming equipment. As n-channel pullups instead of the traditional p-channel puil- shown in the Register Preload Waveform in Figure 5, the ups to eliminate any possibility of SCR induced latching. preload sequence must not begin until the normal power-up To insure that no undesired bias conditions occur with P+ reset operation has completed (after time taeset). The de- diffusions, a Latch-Lock™ power-up circuitry has been de- vice is placed into preload mode by raising the “PRLD” in- veloped. The drain of all P channel devices normally con- put (pin* 13) to voltage Vics, as specified in the Register nected to the device supply are now connected to an alter- Preload Specifications (Table Itl). nate supply that powers up after the device N-wells have To preload the OLMC registers, a series of data bits are been biased and the substrate has reached its negative shifted into the device on the “Spyy” input (pin* 11), one bit clamp value. This prevents any hazardous bias conditions for each OLMC in which registered output has been select- from developing in the power-up sequence. After power-up ed. (Non-registered OLMCs are bypassed.) The shift se- is complete, the Latch-Lock circuitry becomes dormant until quence is clocked by the rising edge of the “Dcik” input @ full power-down has occurred; this eliminates the chance (pin* 1). The data stream is shifted in through the registered of an unwanted P channel power-down during device opera- OLMC with the lowest corresponding pin number, and then tion. “upward” through alt remaining registered OLMCs in pin- number ascending order. Therefore, the first data bit in the Manufacturer Testing series is ultimately loaded into the registered OLMC with the Because of E2CMOS technology, GAL devices can be re- highest corresponding pin number, as shown in Figure 4. Programmed in milliseconds. This allows each device to be “Applies to 24-pin DIP packages for GAL20VBA; refer to the 28-lead PCC completely tested by the manufacturer using numerous log- ‘Connection Diagram for conversion. ic array and architecture patterns prior to shipping. Every 2-188

*.| OLMC Logic Diagram w From Adjacent ia ‘. OLMC/PIN av LMC s s = | > a rs 3 | iis, FDTD saad) bey Pal Ve =D} ——} a [ Fens >) xOR, e [ Fienvs | P F ACO if pin* 16-21 [| | setericg Necks LH ACT, o<] 6 To Adjacent owe TUL/10000-29 “Applies to 24-pin DIP packages for GAL20V8A; refer to the 28-lead PCC Connection Diagram for conversion. FIGURE 6 OLMC Architecture Programming TABLE IV “Small-PAL” Mode “Registered-PAL” Mode “Medium-PAL” Mode JEDEC JEDEC JEDEC Input Input Input Line #8 Line #s Line #8 (Note 1) (Note 1) (Note 1) Pin 1 INPUT INPUT 2,3 CLOCK CLOCK INPUT 2,3 Pin 23 INPUT INPUT 6,7 INPUT INPUT 2,3 INPUT 6,7 ***Pin 22 OUTPUT* INPUT 10,14 REGISTER vo 6,7 TRI-STATE *Pin 21 OUTPUT* INPUT 14,15 REGISTER vo 10,11 Ze) 10, 11 ***Pin 20 OUTPUT* INPUT 18,19 REGISTER ie} 14,15 fe} 14,15 ***Pin 19 OUTPUT* NC REGISTER Vo 18,19 vO 18,19 ***Pin 18 OUTPUT* NC REGISTER vo 22,23 ie} 22,23 ***Pin 17 OUTPUT* INPUT 22,23 REGISTER vo 26, 27 fe) 26,27 ***Pin 16 OUTPUT* INPUT 26,27 REGISTER vO 30,91 vo 30, 31 *9*Pin 15 OUTPUT* INPUT 30, 31 REGISTER vO 34,35 TRI-STATE Pin 14 INPUT INPUT 34,35 INPUT INPUT 38, 39 INPUT 34,35 Pin 13 INPUT INPUT 38,39 G G INPUT 38, 39 Aig= Ol AGig=t || Av=9 | Aig= a] | Ade SYN = 0, AGO = 1 SYN = 1,A00 = 1 All outputs are combinatorial At least one output is All I/O pins are and always active. registered. combinatorial. Note: Pin numbers above apply to 24-pin DIP packages; refer to the 28-lead PCC Connection Diagram for conversion. Note 1: All even and odd numbered JEDEC input line numbers correspond to true and complement array inputs, respectively. “Active combinatorial output. TRI-STATE combinatorial output. ***AC1, applies to these I/O pins only. 2-190

— > GAL20V8A Logic Diagram & ™. PIN NUMBERS: INPUT LINE ‘DIP PIN PRODUCT LINE FIRST CELL NUMBERS NUMBERS Veo, 1 Ss i} tu > 0 2 4 6_8 10 1214 1618 2022 2426 2830 3234 3638 C a TPS SET [9 pis pisps pt719 rari 9431 [33435 |37]59 Ss woe} HEMT | e 80-38 BRR eee ee ee ee eee eet Pd x0R=2560 4 120 eee eee eee

17004 EE EEE EEE Eee Hee eee td AC =2632 they 22 =”

ORE HEP EHEE PEE PEE Pee 8 3 ad 2647, 3 EO (OOO Eee eee ee ed AC1=2635 FFL Or 21 560-355 FERRE EEE EEE EEE EEE EEE —Ed piney bel ttt et | a —_f 44 oo Heer e eran atiatitee =2655, 60-p Ce

770 EEE Eee ee —Hy xor=2502 |

800 AOE EEE Eee Eee eee eee Eee Ed ACI=2634 FFL >O-7-20

920 FUERTE Ra PRRs stiat ieee Pr=ese "=

54 ooo Tee ee ta titatetasitattiee x oor EEE ae

100 PEE REE EEE eee Eee EE —H on= 2563 | |

1240 ACRUSGORIEHMGLIBy COO At 2671 4

‘5—__ooe Ae

1280 PEE | age

WAL EHSISTsiSHiEESHiSstTeeisesetestieeisetiis =—s XOR=2564 Trt 8 Tay eee tt et FAC = 2636 Or 1: Fee esi iiinsisssiiasssesiissssesssssssSssss =e ere ee ~ HEHE | a_i =2679 Lf To ooo COnnmeamatmnitoman ter ECC | 1640 eee ee eee 1880: ROE REE EEE ee eee eee eee ee ee ig XOR=2565, Ir

100 TRO Eee eee eee eee ed ACI=2637 FOr 17

18407 Rp EEE PERE EEE EEE Eee —F4 ipa 76ao fel

HEH | Ta _o =2687

8 Ao (A

206 HAE TTT pmm2es +

9 Ao {etttatiteee <

20 SEE

pepiy Mb SSEESSISIISSSISSHSISHSS ISS s Ss Re IF 300 ea0 EEE EEE Ee Eee ee eee ee ee AC1=2639 | >0-7- 15

24807820 Moret tet eet Pr=2606 -

10-De TT | pt 2705 J Ic 2 OTT TTT TTT Lgl A 1" eae AHARAAPALIRALAALA BALA RAAB a < — 13 1 0121 4161 81901 121141 16h 88 20122) 24126) 28130) 32134 361381 ee 773 te 7 at 4B 45 17 19 2125 2527 29 31 3535 87 39 SYN USER ELECTRONIC SIGNATURE WORD: 2568 2576 2584 2592 2600 2608 2616 2624 2631 MSB LSB MSB LSB ‘SYN=2704 ACO=2705 TL/t/10000-30 JEDEC Logic Array Cell Number = Product Line First Gell Number + input Line Number FIGURE 7 2-191

us| Programming Details 7 Understanding the information in this section is not essen- The SYN bit controls whether a device will have any regis- ef | _ tial when using approved programming equipment and soft- tered outputs (SYN = 0) or will be purely combinatorial 7 ware for developing GAL designs. This is a more thorough (SYN = 1). The SYN bit determines whether device pins* 1 o disclosure of the GAL architecture provided for direct and 13 are used as the clock and global TRI-STATE control = JEDEC cell-map editing and diagnostic purposes. This sec- inputs (SYN = 0) or whether they are ordinary inputs (SYN < tion alone, however, does not contain sufficient information = 1). The ACO bit selects between the “‘Small-PAL” mode | to implement the GAL programming algorithm. 1 detailed and the “Medium/Registered-PAL” modes. The function of & | _ specifications of the GAL programming algorithm are need- the AC? bits depend on the state of the ACO bit. In “Small- SY | eq, please contact the National Semiconductor Programma- PAL” mode (ACO = 0), the AC1 bit in each OLMC deter- <z ble Device Support department. mines whether the associated device pin is an output (AC1 S| As mentioned in the Functional Description, the OLMC is = 0) or an input (AC1 = 1). In “Registered-PAL” mode responsible for selecting input and/or output paths, regis- (ACO = 1), the ACI bit determines whether each OLMC is tered vs. combinatorial outputs, active-high or low polarity, registered (AC1 = 0) or combinatorial (AC1 = 1). In “Medi- and common vs. locally-controlled TRI-STATE control. Ad- um-PAL” mode (ACO = 1), the AC1 bits in all OLMCs must ditionally, the OLMCs select between alternate logic array be set to 1 (combinatorial). All of the valid architecture bit input paths to maintain JEDEC cell-map compatibility with Configurations are shown in the OLMC Architecture table either “‘small-PAL" or “medium-PAL" logic arrays. (Table |V), which has the same familiar format used in the The various configurations of the OLMCs are controlled by a OLMC Selection table (Table |). set of programmable “architecture” cells, separate from the Independent of SYN, ACO and the AC1 bits, the XOR bit in logic-defining array cells. Each GAL device contains two each OLMC selects between active-low (KOR = 0) or ac- “global” architecture cells, “SYN” and “ACO”, which affect tive-high (XOR = 1) output polarity. all OLMCs. Each of the devices’s eight OLMCs also con- “Applies to 24-pin DIP packages for GAL20V8A; refer to the 28-lead PCC tains two “local” cells, “AC1" and "XOR”. The OLMC Logic Connection Diagram for conversion. Diagram in Figure 6 shows how the architecture cells select the different paths through the OLMC. 2-192

Product Information

GAL20V8A-10 specifications and overview.

Summary

Generic Array Logic

Description

Generic Array Logic

Source title GAL20V8A-10 Datasheet(PDF) - National Semiconductor (TI)

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