GAL16V8

GAL16V8AS STMICROELECTRONICS | Alldatasheet

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fe MICROELECTRONICS GAL16V8AS EPROM CMOS PROGRAMMABLE LOGIC DEVICE = HIGH PERFORMANCE SGS-THOMSON SINGLE-POLY EPROM CMOS TECHNOLOGY \\ — 10ns maximum propagation delay ~ a (GAL16VBAS-1 0xxx) <a — Fmax = 62.5MHz 1 — 7ns max. from clock input to data output 20 | lt — TTL compatible 24mA outputs 1 — SGS-THOMSON proprietary Single-Poly F3-G™ technology B c = GLITCH FREE DEVICE PDIP20 PLec20 — Enhanced design minimises ground bounce = VERY LOW POWER — 90mA typ. (115mA max.) loo Halt power selection, 45mA typ. (58 mA max.) loc Quarter Pl! Connections power selection, 27mA typ. (30 mA max.) loc Eighth power selection . oO ® ELECTRICAL ERASABLE CELL TECHNOLOGY o/CLK Gt 20D Veo ~ Reconfigurable logic/reprogrammable cells 1 G2 ‘oe ~ 100% tested: guaranteed 100% final 2 Ge 1D Fe programming yield 544 7 PFs — High speed electrical program & erase 1 TS carreyg 18D F » EIGHT OUTPUT MACROCELLS i qs CALIOVS |. ht = Maximum flexibility for complex logic design q? DF. — Programmable output polarity “de ihr ~ Also emulates 21 types of 20 pin PAL® do phe devices with full function/fuse ond dic n bie map/parametric compatibility a of = PRELOAD AND POWER-ON RESET OF ALL REGISTERS é = 100% functional testability or 33: = ELECTRONIC SIGNATURE FOR USER'S psaaas IDENTIFICATION sds S21 . ids calieve spr, DESCRIPTION sda che The GAL16V8AS, at 10ns maximum propagation tote delay time, combines a high performance CMOS. BBo2 process with Electrical Erasable Single-Poly “> F3-G™ technology — SGS-THOMSON proprie- tary — to provide one of the highest_speed-power Pin Names performance products available in PLD market, (se Tino CMOS circuit allows GAL16V8AS to consume just [ak | } 27mAtyp. cc (Eighth power selection, 15ns) which CuK Clock Input H represents a 75% saving in power when compared vo | to its bipolar counterparts. Its E7PROM CMOS [OE _| Output Enable | technology offers high speed (50ms) erase time Power providing the ability to reprogram or reconfigure the device quickly and efficiently. GAL’ is a registered trademark of Lattice Semiconductor Corp.; PAL" is a registered trademark of Monolithic Memories inc. March 1992 114

GALI6VBAS features 8 programmable Output _and reprogrammable cells allow complete AC, DC Logic Macro Calls (OLMCs) allowing each output and functional testing during manufacture. to be configured by the user. Additionally, the Therefore, SGS-THOMSON guarantees 100% field GALi6VeAS is capable of emulating, in a func- programmability and functionality of GAL” devices. tional/fuse map/parametric compatible mode, 21 SGS-THOMSON also guarantees 100 erase/write types of 20 pin PAL® devices. Unique test circuits cycles and data retention exceeding 20 years. GAL16V8AS Block Diagram L}> E | prea 2}? ; f= = i [=] . Lf | ‘ To] Brel asi FH: tha ' In "PROM CMOS: (lane o7] {| ig pal 12 64x32 PROGRAMMABLE =— 14 ky " eT | ° AND ARRAY * Co b—*] ava w GALI6V8AS_ (Hy, 18 Co | is {| ° al pth bh: aps | [* ble ie] a a|_pe oes apa lowe TE] By wll" Heo * xt a GAL16VBAS PAL® Architecture Emulation 16L8 16R8 16RP6 16L2 14L4 1216 10L8 16H8 16RP8 16R4 16H2 14H4 12H6 10H8 16P8 16R6 16RP4 16P2 14P4 12P6 10P8 ae 9 sag-smonesgny ry > x

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ORS pt eect) VtaeAio Lead Temperature (Soldering) 260 (for 10s max.) Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied. ESD Immunity Test Method: Human Body Model (HBM) ESD Tolerance 2 2000V (See MIL-STD 883c). Test Method: Charge Device Model (CDM) ESD Tolerance > 500V Test Instrument: KeyTek ZapMaster CDM is an additional test only for GAL®s not yet adopted as a company standard test. Switching Test Conditions Switching Test Circuit Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns 10%-90% Input Timing Reference Output Timing Reference 3-state levels are measured 0.5V from steady-state UNDER TEST active level. Cn 3900 Test Conditions ‘Active High: o> Active Low: 200 Active High: 2 Aetive Low: 200 Capacitance (Ta=25'C, f=1.0MHz, Vec=5V) * Guarantied but not 100% tested. 44 scs-

‘Temperature Range Temperature Range [veo | Sieprvenags [as [sas [as fs fv [ta | mronvtenpeatie [0 | | 0 [se | [we | rstton vonge | vaste | oe | vesres | oe |v _| [8 agesaeremer [appa = Vesis the votage apoliedto the GND pin Electrical Characteristics Over Operating Conditions (Commercial Temperature Range) [_symiat [Params | __TontCodons | tin_| Mex. [ Unie [wn | rotesae cue | enoevcvoour | - [xe | oa | ee ee [_ atone |_| eau | Quarter Power (only 15ns) [est | Sapa Si Granwen | vecwsorveosy | eo | a0 | ma | [va uttowvonge [Od (ps | [vor [omeathenvonee fe P= Electrical Characteristics Over Operating Conditions (industrial Temperature Range) [-symbat | Params | TentCondtone | win | wax [ unis | [Thc | weatatnecone | enoeveone | = [ve | a eetire ce) | Quarer Power (only 1$ns) | tos* | Output Short Circuit Current 150 | 30 | ma_| oe a a * One output at a time for a maximum duration of one second. Gy SGS-THomson sie TT OS eee

Switching Characteristics Over Operating Conditions [mass | ea | mae | a ‘Symbol 10 5 [mex [wax [Max | Max _| Combinational 1 ted Propagation Delay cmnwowononey [one] "a [7 |e | we | [wo | Product Term Output i Output Register Registered tone Enable fo Output “Sutput 15 Product Term Output Disable to Output Output Register Registered [_w | Sassen Biss AC Operating Conditions 16V8AS 16VE 16V8AS 16V8AS Input or Feedback Setup megetenes | - |e [-[e [pel - |» [els | Input or Feedback Hold Time (Atter Clock Rise) [ten [Minimum coor wanrign [|e [= [es [= fo [Pe Poe | A Clock Frequency a7 Without Feedback 2 a ee ee ee * Commercial Temperature range only. * Refer to “Switching Test Conditions’ hae tte fae ant tw foes Tew tteo Switching Waveforms ea = Se SESS

FUNCTIONAL DESCRIPTION actual implementation is accomplished by develop- GAL16V8AS has a programmable AND array ‘Ment software/hardware and is completely trans- whose output terms feed a fixed (non programm- —_ Parent to the user. able) OR array, as bipolar PAL®. The 2x 8 input The outputs of the AND array are fed into an OLMC, lines enter the AND array as true or complemented where each output can be individually set to active form. 64 product terms are available allowing stand- high or active low, with either combinational (asyn- ard Sum of Products Logic impiementation. Each —_chronous) or registered (synchronous) configura- product term is obtained by appropriate connection- tions. A common output enable is connected to all s between the input lines and the product term line. registered outputs; product terms can be used to The connections can be made by programming the _ provide individual output enable control for combi- E*PROM memory cell at each intersection of the ational outputs. All outputs have always pro- AND matrix (2048 memory cells). The 64 product grammable polarity. terms are divided into eight groups of 8 terms each . _ One product term for each group can be used to The output logic macrocell provides the designer provide Output Enable contro! for combinational with maximum output flexibility in matching signal output, the others are connected with an OR gate ‘requirements, thus providing more functions than into the corresponding OLMC (Output Logic Mac- _—_ existing 20 pin PAL® devices. rocell). The output buffer is in 3-state when the Three different configuration modes of the OLMCs corresponding output enable signal is low. are possible: registered, complex and simple. The output of an OLMC in registered mode can be either OUTPUT LOGIC MACROCELL (OLMC) registered or combinational. Different modes can- The following discussion pertains to configuring the ‘Not be mixed: i.e. all OLMCs of a device have to be output logic macrocells. It should be noted that Configured in simple, complex or registered mode. GAL16V8AS Output Logic Macrocell Pin 12 and 19 GAL16V8AS Output Logic Macrocell Pin 13 to 18 |e t loo ae | | —— . . FS + ao | eS in [ass . 74

REGISTERED MODE All registered macrocells share common clock and In registered mode macrocelis are configured as output enable control. Registered outputs have 8 registered outputs or combinational inputs/outputs. —_data product terms per output, while combinational Any macrocell can be configured as registered out- _inputs/outputs have only 7 data product terms per put or combinational inpuvoutput. Up to 8 registered output: in the latter case the eighth product term outputs or up to 8 inputs/outputs are possible in this serves as individual output enable control for each mode. macrocell. Registered Output with Programmable Polarity SYN 0 | Aco 1 Actin) 0 \\ | ) ———— a ° | rm | - 2 ———_ oa . ORI) | Combinational Input/Output with Programmable OE and Polarity SYN 0 {1a the macrocelis are configured in this modo ACO 1 the CLK and OE pins don't have any function ACt(n) 1 & \\ —~ i— , | 3 ns | 4} Bd 1 BT SONS

COMPLEX MODE - Allmacrocells have 7 data product terms per output; In complex mode macrocells are configured. as.com- the eighth product term is used as individual output binational inputs/outputs or outputs only. The two enable control for each macrocell. The clock and ‘outermost macrocelts (12 and 19) do not have input —_output enable pins (pins 1 and 11 respectively) are capability: so only 6 inputs/outputs are possible in always available as inputs. this mode. Applications requiring 8 inputs/outputs must be implemented in registered mode. Combinational Input/Output with Programmable OE and Polarity SYN 1 The two outermost macrocells can't perform this function in Complex Mode ACO 1 ACt(n) 1 \\ En — | p? J xo Combinational Output with Programmable OE and Polarity SYN 1 In Complex Mode the two outermost macrocelis are permanently ACO 1 configured in this mode \\ Om) prover eee en eie : : _. Frown vnt | = 914

SIMPLE MODE ; _ terms per output. The clock and output enable pins In simple mode macrocelis are configured as dedi- (pins 1 and 11 respectively) are always available as cated inputs or as dedicated, always active, combi- inputs. national outputs. All macrocells have 8 data product Dedicated Input Mode aco o act 1 Dedicated Combinational Output with Feedback and Programmable Polarity syn 1 acim © . i {> >—y > a Se readies Dedicated Combinational Output with Programmable Polarity Aco 0 By not Catag te facnaox tt AN aera Acta © ; 7 N ov —— >} Ss & poe 10/14 . seve ge tyomgy

ROW ADDRESS MAP DESCRIPTION ELECTRONIC SIGNATURE WORD DESCRIPTION There are a total of 36 unique row addresses avail- An electronic signature word is provided with every able to the user when programming the GAL16V8AS_—_ GAL16V8AS device. It resides at row address 32 device. Row addresses 0-31 each contain 64 bits of and contains 64 bits of reprogrammable memory input term data. This is the AND array where the that can contain user-defined data. Some uses in- custom logic pattern is programmed. Row 32 is the —_ clude user ID codes, revision numbers, or inventory Electronic Signature Word. It has 64 bits available control. This signature data is always available to the for any user defined purpose. Row 33-59 are user independent of the state of the security cel reserved by the manufacturer and are not available wacuiteCTURE CONTROL WORD : ., All the various output configurations of the Row 60 contains the architecture and output polarity GaLi6VgAS devices are controlled by programm- information. The 82 bits within this word are pro- ing cells within the 82 bit Architecture Control Word grammed to configure the device for a specific ap- that resides at row 60. The location of specific bits lication. Row 61 contains a one bit security cell that within the Architecture Control Word is shown in the when programmed prevents further pattern verifica” control word diagram in figure below. The function tion of the array. Row 63 is the row thatis addressed of the SYN, ACO and AC1(n) bits have been ex- to perform a bulk erase of the device, resetting it plained in the OUTPUT LOGIC MACROCELL de- back to a virgin state. Each of these functions is scription. The eight polarity bits determine each described in the following sections. output's polarity individually. The numbers below the XOR(n) and AC1(n) bits in the architecture control word diagram shows the output device pin number GAL16V8AS Row Addresses Map Block ter the sous bit contol m Diagram SECURITY CELL ies yp Pro Row address 61 contains the Security Cell (one bit). ° = : The Security Cell is provided on all GAL16V8AS { | devices as a deterrent to unauthorized copying of R | | the array configuration patterns. Once programmed, 3° | AND | AND the circuitry enabling array access is disabled, pre- wi ARRAY | | ARRAY venting further verification of the array (rows 0-31). \\ ANIMA The cell can be erased only in conjunction with the n 5 array during a bulk erase cycle, so the original Ay zai lafcmars configuration can never be examined once this cell df 32 [RCRONC SOWURE} || ILECTRONC SGAATURE is programmed. Signature data is always available d ( 3 — to the user. e | 98 J By addressing row 63 during a programming cycle, S 60 L ARCHITECTURE CONTROL WORD a clear function performs a bulk erase of the array Ss} ~ OO and the Architecture Control Word. In addition, the & | 6 Li) securny ce Electronic Signature Word and the Security Cell are 62] Reserved erased. This mode resets a previously configured i. device back to its virgin state. \\ 63 (7 sutx erase OUTPUT REGISTER PRELOAD When testing state machine designs, all possible GAL16V8AS Architecture Control Word Diagram

4 Bits} 1 Bit]4 Bits 64 Product Term 4 Bits | 1 al Bits

XOR | SYN |AC1{n) Disables ACt(n)} ACO | XOR 12:13: 14:15 12:13:14 15 PIES. vee PTO 16 17 18.19 16:17 18:19 -THOMSON 11/94

states and state transitions must be verified in the Output Register Preload Pinout design, not just those required in the normal ma- chine operations. This is because in system oper- V, ation, certain events occur that may throw the logic ce into an illegal state (power-up, line voltage glitches, Dean > VY 20 b brown-outs, etc.). To test a design for proper man- ak agement of these conditions, a method must be q2, 9p provided to break the feedback paths, and force any q3 13 desired (e.g. illegal) state into a register. Then the ds wh machine can be sequenced and the outputs tested for the correct next state condition. The qs 1D GAL16VBAS device includes circuitry that allows ds ish each registered output to be synchronously set either high or low. Thus, any present state condition q? 40 can be forced for test sequencing. If necessary, de 13D approved GAL programmers capable of executing >. ds ahs test vectors can perform output register preload ~DIN SDOUT automatically. {| 10 1) PRLD The figure on the right shows the pin functions necessary to preload the register. This test mode is entered by raising PRLD to Vies (register preload specified time (treset=10u1s). As a result, the state on input voltage, typically 15V), which enables the the registered output pins (if they are enabled serial data in (Spn) buffer and the serial data out through OE) will always be high on power-up, re- (Spout) buffer. Data is then serially shifted into the _gardless of the programmed polarity of the output registers on each rising edge of the clock, Dc.k. pins. This features can greatly simplity state ma- Only the macrocells with registered output configu: chine design by providing a known state on power- rations are loaded. If only 3 outputs have registers, up. then only 3 bits need be shifted in. The registers are The timing diagram for power-up is shown below. loaded from the bottom up as shown in the figure Because ‘ot the asynctionous nature of system on the right. power-up, the Voc rise must be monotonic to guar- LATCH-UP PROTECTION antee a valid power-up reset of the GAL16V8AS. GAL® devices are designed with an on board The registers will reset within a maximum of treset charge pump to negatively bias the substrate. The __ time: before this time any clock transition from low negative bias is of sufficient magnitude to prevent __o high is forbidden to avoid undesired commuta- input undershoots from causing the circuitry to _ tions. Asin normal system operation, avoid clocking latch. Additionally, outputs are designed with n- the device until all input and feedback path setup channel pullups instead of the traditional p-channel __ times have been met (i.e. avoid clocking before the pullups to eliminate any possibility of SCR induced _tpr=treset+tsu time interval). latching. DEVICES PROGRAMMING POWER-UP RESET SGS-THOMSON strongly recommends the use of Circuitry within the GAL16V8AS provides a reset qualified programming hardware. Programming on signal to all registers during power-up. All internal Unapproved equipment will invalidate all guaran- registers will have their Q outputs set low aftera _'@@S- Power-Up Reset Timing Diagram Nee OO er Power o soe ye Tree “Yyyyy Coa Teratere “Ee, Gutputs , KXXXKXXXKKY 12/14 S77 THOMSON

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Ordering Informations* SGS-THOMSON GAL®s are available in a variety of package and temperature ranges. General ordering code is reported below. GAL16V8AS- sw p t | L Temperature 1 0°C to +70°C 3. -40°C to +85°C (only for 15 and 20ns Speed selection) Package BB 20 Pins PDIP C 20 Pins PLCC \\_—— Power H_ Half Power Q Quarter Power (only for 15 and 20ns Speed selection) E Eighth Power (only for 15ns Speed selection) Speed 10 10ns 12 12ns 15 15ns 20 20ns Example: ordering code for a GAL16V8AS, 12ns speed and Half Power in PDIP is GAL16V8AS-12HB1 * Please contact local Product Marketing for latest update on package / temperature range availability. wee 7 seg-moqson