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Dec 2014 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/ Pg1 of 8 Normally – OFF Silicon Carbide Junction Transistor Features Package 225°C maximum operating temperature Gate Oxide Free SiC Switch Exceptional Safe Operating Area Excellent Gain Linearity Temperature Independent Switching Performance Low Output Capacitance Positive Temperature Coefficient of RDS,ON Suitable for Connecting an Anti-parallel Diode TO-258 Advantages Applications Compatible with Si MOSFET/IGBT Gate Drive ICs > 20 µs Short-Circuit Withstand Capability Lowest-in-class Conduction Losses High Circuit Efficiency Minimal Input Signal Distortion High Amplifier Bandwidth Down Hole Oil Drilling Geothermal Instrumentation Solenoid Actuators General Purpose High-Temperature Switching Amplifiers Solar Inverters Switched-Mode Power Supply (SMPS) Power Factor Correction (PFC) Table of Contents Section I: Absolute Maximum Ratings Parameter Symbol Conditions Value Unit Notes Drain – Source Voltage VDS VGS = 0 V 600 V Continuous Drain Current ID TJ = 225°C, TC = 25°C 100 A Fig. 21 Continuous Gate Current IGM 3.5 A Turn-Off Safe Operating Area RBSOA TJ = 225°C, IG = 3.5 A, Clamped Inductive Load ID,max = 50 @ VDS ≤ VDSmax A Fig. 19 Short Circuit Safe Operating Area SCSOA TJ = 225°C, IG = 3.5 A, VDS = 400 V, Non Repetitive >20 µs Reverse Gate – Source Voltage VSG 30 V Reverse Drain – Source Voltage VSD 25 V Power Dissipation Ptot TJ = 225°C, TC = 25°C 769 W Fig. 16 Operating and Storage Temperature Tstg -55 to 225 °C D S G D D S G VDS = 600 V RDS(ON) = 25 mΩ ID (Tc = 25°C) = 100 A hFE (Tc = 25°C) = 105
Dec 2014 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/ Pg2 of 8 Section II: Static Electrical Characteristics A: On State B: Off State C: Thermal Section III: Dynamic Electrical Characteristics A: Capacitance and Gate Charge B: Switching1 Parameter Symbol Conditions Value Unit Notes Min. Typical Max. Drain – Source On Resistance RDS(ON) ID = 50 A, Tj = 25 °C ID = 50 A, Tj = 125 °C ID = 50 A, Tj = 175 °C ID = 50 A, Tj = 225 °C mΩ Fig. 5 Gate – Source Saturation Voltage VGS,SAT ID = 50 A, ID/IG = 40, Tj = 25 °C ID = 50 A, ID/IG = 30, Tj = 175 °C 3.42 3.23 V Fig. 7 DC Current Gain hFE VDS = 5 V, ID = 50 A, Tj = 25 °C VDS = 5 V, ID = 50 A, Tj = 125 °C VDS = 5 V, ID = 50 A, Tj = 175 °C VDS = 5 V, ID = 50 A, Tj = 225 °C 105 – Fig. 5 Drain Leakage Current IDSS VR = 600 V, VGS = 0 V, Tj = 25 °C VR = 600 V, VGS = 0 V, Tj = 125 °C VR = 600 V, VGS = 0 V, Tj = 225 °C 100 μA Fig. 8 Gate Leakage Current ISG VSG = 20 V, Tj = 25 °C 20 nA Thermal resistance, junction - case RthJC 0.26 °C/W Fig. 20 Parameter Symbol Conditions Value Unit Notes Min. Typical Max. Input Capacitance Ciss VGS = 0 V, VD = 100 V, f = 1 MHz 6450 pF Fig. Error! Reference source not found. Reverse Transfer/Output Capacitance Crss/Coss VD = 100 V, f = 1 MHz 420 pF Fig. Error! Reference source not found. Output Capacitance Stored Energy EOSS VGS = 0 V, VD = 400 V, f = 1 MHz 17.4 µJ Fig. Error! Reference source not found. Effective Output Capacitance, time related Coss,tr ID = constant, VGS = 0 V, VDS = 0…400 V 390 pF Effective Output Capacitance, energy related Coss,er VGS = 0 V, VDS = 0…400 V 284 pF Gate-Source Charge QGS VGS = -5…3 V 55 nC Gate-Drain Charge QGD VGS = 0 V, VDS = 0…400 V 156 nC Gate Charge - Total QG 211 nC Internal Gate Resistance – zero bias RG(INT-ZERO) f = 1 MHz, VAC = 50 mV, VDS = 0 V, VGS = 0 V, Tj = 225 ºC 0.9 Ω Internal Gate Resistance – ON RG(INT-ON) VGS > 2.5 V, VDS = 0 V, Tj = 225 ºC 0.09 Ω Turn On Delay Time td(on) Tj = 25 ºC, VDS = 400 V, ID = 50 A, Resistive Load Refer to Section V for additional driving information. 25 ns Fall Time, VDS tf ns Fig. Error! Reference source not found., Error! Reference source not found. Turn Off Delay Time td(off) 40 ns
Dec 2014 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/ Pg3 of 8 1 – All times are relative to the Drain-Source Voltage VDS Rise Time, VDS tr ns Fig. Error! Reference source not found., Error! Reference source not found. Turn On Delay Time td(on) Tj = 225 ºC, VDS = 400 V, ID = 50 A, Resistive Load 19 ns Fall Time, VDS tf ns Fig. Error! Reference source not found. Turn Off Delay Time td(off) 89 ns Rise Time, VDS tr ns Fig. Error! Reference source not found. Turn-On Energy Per Pulse Eon Tj = 25 ºC, VDS = 400 V, ID = 50 A, Inductive Load Refer to Section V. 690 µJ Fig. Error! Reference source not found., Error! Reference source not found. Turn-Off Energy Per Pulse Eoff 359 µJ Fig. Error! Reference source not found., Error! Reference source not found. Total Switching Energy Etot 1049 µJ Turn-On Energy Per Pulse Eon Tj = 225 ºC, VDS = 400 V, ID = 50 A, Inductive Load 758 µJ Fig. Error! Reference source not found. Turn-Off Energy Per Pulse Eoff 337 µJ Fig. Error! Reference source not found. Total Switching Energy Etot 1095 µJ
Dec 2014 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/ Pg11 of 8 Section VI: Package Dimensions TO-258 PACKAGE OUTLINE NOTE 1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER. 2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS
Revision History
Date Revision Comments Supersedes 2014/12/12 5 Updated Electrical Characteristics 2014/08/23 4 Updated Electrical Characteristics 2014/04/10 3 Updated Electrical Characteristics 2014/02/05 2 Updated Electrical Characteristics 2013/12/19 1 Updated Gate Drive Section 2013/12/05 0 Initial release Published by GeneSiC Semiconductor, Inc.
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Dulles, VA 20166 GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage.
Dec 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg1 of 1 Section VII: SPICE Model Parameters This is a secure document. Please copy this code from the SPICE model PDF file on our website (http://www.genesicsemi.com/images/hit_sic/sjt/GA50JT06-258_SPICE.pdf) into LTSPICE (version 4) software for simulation of the GA50JT06-258. * MODEL OF GeneSiC Semiconductor Inc. * $Revision: 1.3 $ * $Date: 12-DEC-2014 $ * GeneSiC Semiconductor Inc. * 43670 Trade Center Place Ste. 155 * Dulles, VA 20166 * COPYRIGHT (C) 2014 GeneSiC Semiconductor Inc. * ALL RIGHTS RESERVED * These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY * OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED * TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE." * Models accurate up to 2 times rated drain current. .model GA50JT06 NPN + IS 5.00E-47 + ISE 1.26E-26 + EG 3.23 + BF 106 + BR 0.55 + IKF 9000 + NF 1 + NE 2 + RB 0.9 + IRB 0.002 + RBM 0.09 + RE 0.01 + RC 0.013 + CJC 2.3989E-9 + VJC 2.8346223 + MJC 0.4846 + CJE 6.026E-09 + VJE 3.17915435 + MJE 0.52951635 + XTI 3 + XTB -1.2 + TRC1 7.00E-3 + VCEO 600 + ICRATING 100 + MFG GeneSiC_Semiconductor * End of GA50JT06 SPICE Model