GA15IDDJT22-FR4 GENESIC | Alldatasheet
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Isolated Gate Driver GA15IDDJT22-FR4 Sep 2014 Pg1 of 5 Gate Driver for SiC SJT with Output and Signal Isolation Features Package Requires single 12 V voltage supply Two-voltage level topology with low drive losses High-side drive capable with 2200 V min. supply isolation 6000 V Signal Isolation (up to 10 s) Capable of high Gate Currents with 3 W Maximum Power RoHS Compliant Suitable for driving GA50JT12-247 GA50JT12-247 GA50SICP12-227 GA100SICP12-227 Gate Drive Theory of Operation The SJT transistor is a current controlled transistor which requires a positive gate curr ent for turn-on as well as to remain i n on-state. An ideal gate current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 1. Figure 1: Idealized Gate Current Waveform Gate Currents, IG,pk/-IG,pk and Voltages during Turn-On and Turn-Off An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, Q G, for turn-on is supplied by a burst of high gate current, IG,on, until the gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged. As an example, an IG,pon ≥ 3 A is required to achieve a 25 ns V DS fall time for a 800 V switching transition, due to the gate-drain charge, Q GD of 77 nC for the GA20JT12-247. The I G,pon pulse should ideally terminate, when the drain volt age falls to its on-state value, in order to avoid unnecessary drive losses during the steady on-stat e. In practice, the rise time of the I G,on pulse is affected by the parasitic inductances, L par in the TO-247 package and drive circuit. A voltage developed ac ross the parasitic inductance in the source path, L s, can de-bias the gate-source junction, when high drain currents begin to flow through the device. The applied gate voltage should be maintained high enough, above the VGS,ON level to counter these effects. A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. While sati sfactory turn off can be achieved with V GS = 0 V, a negative gate voltage V GS may be used in order to speed up the turn-off transition. VISO,min = 2200 V PDrive, cont = 15 W PDrive,switch = > 3 W fMAX = TBD
Isolated Gate Driver GA15IDDJT22-FR4 Sep 2014 Pg2 of 5 After the device is turned on, I G may be advantageously lowered to I G,steady for reducing unnecessary gate drive losses. The I G,steady is determined by noting the DC current gain, hFE, of the device. The desired I G,steady is determined by the peak device junction temperature T J during operation, drain current I D, DC current gain h FE, and a 50 % safety margin to ensure operating the device in the saturation region with low on-state voltage drop by the equation: ሻ1 . 5 Implementation Using the IXYS IX2204 Gate Driver The IXYS IX2204 is a dual output gate drive integrated circuit which can be used to drive an SJ T transistor by supplying the re quired gate drive current I G in a low-power gate drive solution. This conf iguration features an external gate capacitor, C G, which creates the brief current peak I G,on during device turn-on and I G,off during turn-off for fast switching and an external gate resistor R G(EXT) to set the continuous gate current IG,steady required for the device to remain on. This configuration is shown in Figure 2 with further details provided below. Figure 2: Gate drive configuration using an IXYS IX2204 gate drive IC. Table 1: Recommended Component List for implementing the IX2204 based Gate Drive for the GA20JT12-247 Reference Component Description Suggested Part RG(EXT) Gate Resistance, External 2.2 Ω, 2 W CRM2512-JW-2R2ELF CG Gate Capacitance 10 nF C1812C103J1GACTU RCG Damping Resistor 1.0 Ω, 0.5 W ERJ-1TYJ1R0U DRG Silicon Schottky Diode 40 V, 2 A SS24T3G Rb BJT Base Resistor 1.0 Ω, 0.5 W ERJ-1TYJ1R0U QHA, QHB Current Boost NPN 40 V, 8 A, Silicon NPN BJT MJD44H11 QLA, QLB Current Boost PNP 40 V, 8 A, Silicon PNP BJT MJD45H11 U1 Signal Isolator Opto-Isolator –or– Transformer Isolator ACPL-4800 / ADUM3210 X1 DC/DC Converter, V GH Supply VOUT = +20 V, VIN = +12 V, 2 W, VISO = 5.2 kV MGJ2D122005SC X2 DC/DC Converter, V GL Supply VOUT = +5 V, VIN = +12 V, 3 W, VISO = 3.0 kV MEV3S1205SC X3 DC/DC Converter, V EE Supply VOUT = -5 V, VIN = +12 V, 2 W, VISO = 5.2 kV MGJ2D122005SC Voltage Supply Selection The IX2204 gate drive design requires three supply voltages V GH, V GL, and V EE (listed in Table 2) optionally supplied through DC/DC converters. During device turn-on, V GH charges the external capacitor C G thereby delivering the narrow width, high current pulse I G,on to the SJT gate and charges the SJT’s internal terminal capacitances C GD and CGS. For a given level of parasitic induct ance in the gate circuit and SJT package, the rise time of IG,on is controlled by the choice of VGH and CG. During the steady on-state, VGL in combination with the internal and external gate
Isolated Gate Driver GA15IDDJT22-FR4 Sep 2014 Pg3 of 5 resistances provides a continuous gate cu rrent for the SJT to remain on. The V EE supply sets the gate negative during turn-off and steady off- state for faster switching and to avoid spurious turn-on which may be caused by external circuit noise. The power rating of the voltage supplies should be adequate to meet the gate drive power requirements as determined by 2ீு 2ாா ܦ Table 2: IX2204 Gate Drive Example Component List Symbol Parameter Values Range Typical VGH Supply Voltage, Driver Output A 15 – 20 + 20.0 VGL Supply Voltage, Driver Output B 5.0 – 7.0 + 5.0 VEE Negative Supply Voltage -10 – GND - 5.0 Gate Capacitor CG Selection Figure 3: Primary gate drive circuit passive components with series gate resistance Schottky rectifier. An external gate capacitor C G connected directly to the device gate pin delivers the positive current peak I G,on during device turn-on and the negative current peak IG,off during turn-off. A low value resistor R CG is connected in series with C G to damp potential high-frequency oscillation. A high value resistor Rch in parallel with CG sets the SJT gate to a defined potential (-VEE) during steady off-state. At device turn-on, C G is pulled to V GH which produces a transient peak of gate voltage and current. This current peak rapidly charges the internal SJT CGS and CGD capacitances. A Schottky diode, D RG, in series with R G(EXT) blocks any CG induced current from draining out through RG(EXT) and ensures that all of the charge within C G flows only into the device gate, allowing for an ultra-fast device turn-on. During steady on- state, a potential of V GH - VGS = VGH – 3 V is across C G. When the device is turned off, C G is pulled to negative V EE and V GS is pulled to a transient peak of V GS,turn-off = VEE – (V GH – 3 V), this induces the negative current peak I G,off out of the gate which discharges the SJT internal capacitances. External Gate Resistor RG(EXT) Selection An external gate resistor RG(EXT) connected directly to the SJT gate pin acts to deliver a continuous current I G,steady during steady on-state. The gate current is determined by: ௌ ீሺூே்ሻ The on-state gate-source voltage V GS(FWD) can be approximated to 3 V and the Schottky on-state voltage V Sch can be approximated to 0.3 V which simplifies the equation to: ீሺூே்ሻ IG CG RG(EXT) D S DRG RG(INT) RCG VGL / VEE VGH / VEE Rch G
Isolated Gate Driver GA15IDDJT22-FR4 Sep 2014 Pg4 of 5 The desired IG,steady is determined by the peak device junction temperature TJ during operation, drain current ID, DC current gain β, and a 50 % safety margin to avoid operating the device in saturation. IG,steady may also be approximated from the temperature dependent on-state curves of the device, provided that a 50 % increase is given. Table 3: Passive Output Component List Symbol Parameter Values Range Typical Units CG Gate Capacitor, External 5 – 20 10 nF RCG Damping Resistor of Gate Capacitor 0.5 – 2.0 1.0 Ω Rch Charging Resistor 500 – 10k 1k Ω RG(EXT) Gate Resistor, External 0.5 – 10 2.0 Ω RG(INT-ON) Gate Resistance, Internal, On-State 0.05 – 0.2 0.13 Ω DRG Schottky Diode of Gate Resistor -- -- Optional Gate Current Boost Network An optional output totem-pole network may be attached to the IX2204 output pins as shown in Figure 2 using either silicon BJTs (shown) or MOSFETs. This configuration allows the IX2204 to directly driv e the BJT bases or MOSFET gates and not supply the full peak and steady state gate current entering the SJT gate. The primary gate curr ent delivery device is transferred to the discrete components which have higher power dissipation ratings than the IX2204. Voltage Supply Isolation The DC/DC supply voltage converters are suggested to prov ide isolation at a minimu m of twice the working V DS on the SJT transistor during off-state to provide adequate protection to circuitry external to the gate drive ci rcuit. Suggested DC/DC converters have an is olation of 3.0 kV or greater. Alternatively, DC/DC converter galvanic isolation may be bypassed and direct connection of variable voltage supplies may be done, this may be convenient during testing and prototyping but carries risk and is not suggested for extended usage. Figure 4: Typical DC/DC converter configuration Signal Isolation The gate supply signal is suggested to be isolated to twice the working V DS on the SJT during off-state to provide adequate protection to circuitry external to the gate drive circuit. This may be done using opto or galvanic isolation techniques. Additional Features The IX2204 has additional functionality available which is unused in the given configuration. Desaturation detection and fault status monitoring may be implemented by un-grounding the DESAT, BLANK, and TRISTA TE pins and configuring them as recommended in the IX2204 datasheet, available from IXYS. Active mill er clamping is also available on other gat e drive ICs which may also be desired in s ome SJT switching applications but is not required, refer to specific gate drive IC datasheets for more information.
Isolated Gate Driver GA15IDDJT22-FR4 Sep 2014 Pg5 of 5
Revision History
Date Revision Comments Supersedes 2014/09/15 0 Initial release Published by GeneSiC Semiconductor, Inc.
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