GA10SICP12-263

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Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 1 of 11 Normally – OFF Silicon Carbide Junction Transistor Features Package

• 175 °C Maximum Operating Temperature
• Gate Oxide Free SiC Switch
• Optional Gate Return Pin
• Exceptional Safe Operating Area
• Integrated SiC Schottky Rectifier
• Excellent Gain Linearity
• Temperature Independent Switching Performance
• Low Output Capacitance
• Positive Temperature Coefficient of RDS,ON
• Suitable for Connecting an Anti-parallel Diode 7L D2PAK (TO-263-7L) Advantages Applications
• Compatible with Si MOSFET/IGBT Gate Drive ICs
• > 20 µs Short-Circuit Withstand Capability
• Lowest-in-class Conduction Losses
• High Circuit Efficiency
• Minimal Input Signal Distortion
• High Amplifier Bandwidth
• Down Hole Oil Drilling, Geothermal Instrumentation
• Hybrid Electric Vehicles (HEV)
• Solar Inverters
• Switched-Mode Power Supply (SMPS)
• Power Factor Correction (PFC)
• Induction Heating
• Uninterruptible Power Supply (UPS)
• Motor Drives Table of Contents Section I: Absolute Maximum Ratings Parameter Symbol Conditions Value Unit Notes Drain – Source Voltage VDS VGS = 0 V 1200 V Continuous Drain Current ID TC = 25°C 25 A Fig. 17 Continuous Drain Current ID TC = 150°C 10 A Fig. 17 Continuous Gate Current IG 1.3 A Continuous Gate Return Current IGR 1.3 A Turn-Off Safe Operating Area RBSOA TVJ = 175 oC, Clamped Inductive Load ID,max = 10 @ VDS ≤ VDSmax A Fig. 19 Short Circuit Safe Operating Area SCSOA TVJ = 175 oC, IG = 1 A, VDS = 800 V, Non Repetitive >20 µs Reverse Gate – Source Voltage VSG 30 V Reverse Drain – Source Voltage VSD 25 V Power Dissipation Ptot TC = 25 °C / 150 °C, tp > 100 ms 170 / 22 W Fig. 16 Storage Temperature Tstg -55 to 175 °C G TAB Drain GR S S S S S Drain (TAB) Source Gate (Pin 1) Gate Return (Pin 2) VDS = 1200 V RDS(ON) = 100 mΩ ID (@ 25°C) = 25 A hFE (@ 25°C) = 80 Please note: The Source and Gate Return pins are not exchangeable. Their exchange might lead to malfunction.

Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 2 of 11 Parameter Symbol Conditions Value Unit Notes Free-Wheeling SiC Diode Repetitive peak reverse voltage VRRM 1200 V Continuous forward current IF TC ≤ 150 °C 10 A RMS forward current IF(RMS) TC ≤ 150 °C 17 A Surge non-repetitive forward current, Half Sine Wave IFSM TC = 25 °C, tP = 10 ms TC = 150 °C, tP = 10 ms 55 A Non-repetitive peak forward current IF,max TC = 25 °C, tP = 10 µs 280 A I t value ∫i 2 dt TC = 25 °C, tP = 10 ms TC = 115 °C, tP = 10 ms 15 A s Section II: Static Electrical Characteristics A: On State B: Off State C: Thermal Section III: Dynamic Electrical Characteristics A: Capacitance and Gate Charge Parameter Symbol Conditions Value Unit Notes Min. Typical Max. Drain – Source On Resistance RDS(ON) ID = 10 A, Tj = 25 °C ID = 10 A, Tj = 150 °C ID = 10 A, Tj = 175 °C 100 155 175 mΩ Fig. 4 Gate – Source Saturation Voltage VGS,SAT ID = 10 A, ID/IG = 40, Tj = 25 °C ID = 10 A, ID/IG = 30, Tj = 175 °C 3.50 3.27 V Fig. 7 DC Current Gain hFE VDS = 8 V, ID = 10 A, Tj = 25 °C VDS = 8 V, ID = 10 A, Tj = 125 °C VDS = 8 V, ID = 10 A, Tj = 175 °C FWD forward voltage VF IF = 10 A, Tj = 25 °C IF = 10 A, Tj = 175 °C 1.6 2.5 V Drain Leakage Current IDSS VDS = 1200 V, VGS = 0 V, Tj = 25 °C VDS = 1200 V, VGS = 0 V, Tj = 150 °C VDS = 1200 V, VGS = 0 V, Tj = 175 °C μA Fig. 8 Gate Leakage Current ISG VSG = 20 V, Tj = 25 °C 20 nA Thermal resistance, junction - case RthJC SiC Junction Transistor 0.88 °C/W Fig. 20 Thermal resistance, junction - case RthJC SiC Diode 0.8 °C/W Fig. 21 Parameter Symbol Conditions Value Unit Notes Min. Typical Max. Input Capacitance Ciss VGS = 0 V, VDS = 800 V, f = 1 MHz 1400 pF Fig. 9 Reverse Transfer/Output Capacitance Crss/Coss VDS = 1 V, f = 1 MHz VDS = 400 V, f = 1 MHz VDS = 800 V, f = 1 MHz 760 pF Total Output Capacitance Charge Qoss VDS = 400 V VDS = 800 V 56 80 nC Output Capacitance Stored Energy EOSS VGS = 0 V, VDS = 800 V, f = 1 MHz 25 µJ Fig. 10 Effective Output Capacitance, time related Coss,tr ID = constant, VGS = 0 V, VDS = 0…800 V 100 pF Effective Output Capacitance, energy related Coss,er VGS = 0 V, VDS = 0…800 V 75 pF Gate-Source Charge QGS VGS = -5…3 V 10 nC Gate-Drain Charge QGD VGS = 0 V, VDS = 0…800 V 55 nC Gate Charge - Total QG 65 nC

Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 3 of 11 B: Switching1 1 – All times are relative to the Drain-Source Voltage VDS Parameter Symbol Conditions Value Unit Notes Min. Typical Max. Internal Gate Resistance – ON RG(INT-ON) VGS > 2.5 V, VDS = 0 V, Tj = 175 ºC 0.19 Ω Turn On Delay Time td(on) Tj = 25 ºC, VDS = 800 V, ID = 10 A, Resistive Load Refer to Section V for additional driving information. 10 ns Fall Time, VDS tf 10 ns Fig. 11, 13 Turn Off Delay Time td(off) 22 ns Rise Time, VDS tr 10 ns Fig. 12, 14 Turn On Delay Time td(on) Tj = 175 ºC, VDS = 800 V, ID = 10 A, Resistive Load 10 ns Fall Time, VDS tf 10 ns Fig. 11 Turn Off Delay Time td(off) 35 ns Rise Time, VDS tr 10 ns Fig. 12 Turn-On Energy Per Pulse Eon Tj = 25 ºC, VDS = 800 V, ID = 10 A, Inductive Load Refer to Section V. 140 µJ Fig. 11, 13 Turn-Off Energy Per Pulse Eoff 10 µJ Fig. 12, 14 Total Switching Energy Etot 150 µJ Turn-On Energy Per Pulse Eon Tj = 175 ºC, VDS = 800 V, ID = 10 A, Inductive Load 140 µJ Fig. 11 Turn-Off Energy Per Pulse Eoff 100 µJ Fig. 12 Total Switching Energy Etot 150 µJ

Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 8 of 11 Section V: Driving the GA10SICP12-263 Drive Topology Gate Drive Power Consumption Switching Frequency Application Emphasis Availability TTL Logic High Low Wide Temperature Range Coming Soon Constant Current Medium Medium Wide Temperature Range Coming Soon High Speed – Boost Capacitor Medium High Fast Switching Production High Speed – Boost Inductor Low High Ultra Fast Switching Coming Soon Proportional Lowest High Wide Drain Current Range Coming Soon Pulsed Power Medium N/A Pulse Power Coming Soon A: Static TTL Logic Driving The GA10SICP12-263 may be driven with direct (5 V) TTL logic and current amplification. The amplified current level of the supply must meet or exceed the steady state gate current (I G,steady) required to operate the GA10SICP12-263. Minimum I G,steady is dependent on the anticipated drain current I D through the SJT and the DC current gain h FE, it may be calculated from the following equation. An accurate value of the h FE may be read from Figure 4. An optional resistor R G may be used in series with the gate pin to trim I G,steady, also an optional capacitor C G may be added in parallel with RG to facilitate faster SJT switching if desired, further details on these options are given in the following section. 𝐼𝐼𝐺𝐺,𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 ≈ 𝐼𝐼𝐷𝐷 ℎ𝐹𝐹𝐹𝐹(𝑇𝑇, 𝐼𝐼𝐷𝐷) ∗1.5 Figure 23: TTL Gate Drive Schematic B: High Speed Driving The SJT is a current controlled transistor which requires a positive gate current for turn- on and to remain in on-state. An idealized gate current waveform for ultra-fast switching of the SJT while maintaining low gate drive losses is shown in Figure 24, it features a positive current peak during turn-on, a negative current peak during turn-off, and continuous gate current during on-state. Figure 24: An idealized gate current waveform for fast switching of an SJT. An SJT is rapidly switched from its blocking state to on- state when the necessary gate char ge, QG, for turn -on is supplied by a burst of high gate current, IG,on, until the SJT gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged. 𝑄𝑄𝑜𝑜𝑜𝑜 = 𝐼𝐼𝐺𝐺,𝑜𝑜𝑜𝑜 ∗𝑠𝑠1 𝑄𝑄𝑜𝑜𝑜𝑜 ≥ 𝑄𝑄𝑔𝑔𝑠𝑠 + 𝑄𝑄𝑔𝑔𝑠𝑠 TTL Gate Signal 5 / 0 V TTL i/p

5 V D

S G GR CG RG IG,steady

Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 9 of 11 Ideally, IG,on should terminate when the drain voltage falls to its on- state value in order to avoid unnecessary drive losses during the steady on- state. In practice, the rise time of the I G,on pulse is affected by the parasitic inductances, L par in the device package and drive circuit. A voltage developed across the parasitic inductance in the source path, Ls, can de- bias the gate-source junction, when high drain currents begin to flow through the device. The voltage applied to the gate pin should be maintained high enough, above the VGS,sat (see Figure 7) level to counter these effects. A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn- off. Turn off can be achieved with V GS = 0 V, however a negative gate voltage V GS may be used in order to speed up the turn-off transition. Gate Return Pin The optional gate return (GR) pin allows for a reduction of source path i nductive and resistive coupling in the gate driver connection to the GA10SICP12-263. Drain currents through the source pin during transient and steady state operation induce an undesirable source voltage in all power transistors due to unavoidable source p in inductance and resistance. This voltage can negatively affect gate driving performance, however the gate return pin allows for decoupling from these source current path effects which results in faster switching and higher efficiency gate driving. B:1: High Speed, Low Loss Drive with Boost Capacitor, GA03IDDJT30-FR4 The GA10SICP12-263 may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology in which multiple voltage levels, a gate resistor, and a gate capacitor are used to provide fast sw itching current peaks at turn-on and turn-off and a continuous gate current while in on-state. A 3 kV isolated evaluation gate drive board ( GA03IDDJT30-FR4) utilizing this topology is commercially available for high and low- side driving, its datasheet provides additional details about this drive topology. Figure 25: Topology of the GA03IDDJT30-FR4 Two Voltage Source gate driver. The GA03IDDJT30-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre -installed for an effective gate resistance of R G = 3.75 Ω. It may be necessary for the user to reduce RG1 and RG2 under high drain current conditions for safe operation of the GA10SICP12-263. The steady state current supplied to the gate pin of the GA10SICP12-263 with on- board RG = 3.75 Ω, is shown in Figure 26. The maximum allowable safe value of RG for the user’s required drain current can be read from Figure 27. For the GA10SICP12-263, RG must be reduced for ID ≥ ~10 A for safe operation with the GA03IDDJT30-FR4. For operation at ID ≥ ~10 A, RG may be calculated from the following equation, which contains the DC current gain h FE (Figure 4) and the gate- source saturation voltage VGS,sat (Figure 7). 𝑅𝑅𝐺𝐺,𝑚𝑚𝑠𝑠𝑚𝑚 = 4.7𝑉𝑉 −𝑉𝑉𝐺𝐺𝐺𝐺,𝑠𝑠𝑠𝑠𝑠𝑠∗ℎ𝐹𝐹𝐹𝐹(𝑇𝑇, 𝐼𝐼𝐷𝐷) 𝐼𝐼𝐷𝐷 ∗1.5 −0.6Ω IG CG2 Gate Signal VGH R1 U1 VGL VEE VGL VEE VGL VGH VEE VEE VGL VEE CG1 RG1 RG2 C10 +12 V +12 V VCC High VCC High RTN VCC Low VCC Low RTN Signal Signal RTN Gate Source Voltage Isolation Barrier GA03IDDJT30-FR4 Gate Driver Board D S G GR

Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 12 of 11 Section VI: Package Dimensions TO-263-7L PACKAGE OUTLINE NOTE 1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER. 2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS

Revision History

Date Revision Comments Supersedes 2015/11/23 1 Updated Electrical Characteristics 2015/05/29 0 Initial release Published by GeneSiC Semiconductor, Inc.

43670 Trade Center Place Suite 155

Dulles, VA 20166 GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage. 0.171 (4.343) 0.181 (4.597) 0.045 (1.143) 0.055 (1.397) 0.000 (0.000) 0.012 (0.305) SEATING PLANE <D> 0.090 (2.286) 0.110 (2.794) 0.010 (0.254) GATE PLANE 0°- 8° 0.013 (0.330) 0.017 (0.432) 0.400 (10.160) 0.420 (10.668) 0.055 (1.397) REF. 0.075 (1.905) 0.045 (1.143) 0.055 (1.397) 0.351 (8.915) 0.361 (9.169) 0.575 (14.605) 0.625 (15.875) 18°- 22° REF. 0.400 (10.160) 0.300 (7.620) 0.256 (6.502) 0.065 (1.651) 0.125 (3.175) 0.304 (7.722) GA10SICP12-263 XXXXXX Lot code 0.050 (1.27) 0.024 (0.60)

Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 1 of 1 Section VII: SPICE Model Parameters This is a secure document. Please copy this code from the SPICE model PDF file on our website (http://www.genesicsemi.com/images/products_sic/igbt_copack/GA10SICP12-263_SPICE.pdf) into LTSPICE (version 4) software for simulation of the GA10SICP12-263. * MODEL OF GeneSiC Semiconductor Inc. * $Revision: 2.0 $ * $Date: 20-NOV-2015 $ * GeneSiC Semiconductor Inc. * 43670 Trade Center Place Ste. 155 * Dulles, VA 20166 * COPYRIGHT (C) 2015 GeneSiC Semiconductor Inc. * ALL RIGHTS RESERVED * These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY * OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED * TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE." * Models accurate up to 2 times rated drain current. * Start of GA10SICP12-263 SPICE Model .SUBCKT GA10SICP12 DRAIN GATE SOURCE Q1 DRAIN GATE SOURCE GA10SICP12_Q D1 SOURCE DRAIN GA10SICP12_D1 D2 SOURCE DRAIN GA10SICP12_D2 .model GA10SICP12_Q NPN + IS 9.833E-48 ISE 1.073E-26 EG 3.23 + BF 87 BR 0.55 IKF 5000 + NF 1 NE 2 RB 4.67 + IRB 0.001 RBM 0.16 RE 0.005 + RC 0.08 CJC 229.9E-12 VJC 3.22 + MJC 0.492 CJE 1244E-9 VJE 2.86 + MJE 0.465 XTI 3 XTB -1.35 + TRC1 7E-3 VCEO 1200 ICRATING 10 .MODEL GA10SICP12_D1 D + IS 4.55E-15 RS 0.0736 N 1 + IKF 1000 EG 1.2 XTI -2 + TRS1 0.0054347826 TRS2 2.71739E-05 CJO 6.40E-10 + VJ 0.469 M 1.508 FC 0.5 + TT 1.00E-10 BV 1200 IBV 1.00E-03 + VPK 1200 IAVE 10 .MODEL GA10SICP12_D2 D + IS 1.54E-22 RS 0.19 TRS1 -0.004 + N 3.941 EG 3.23 IKF 19 + XTI 0 FC 0.5 TT 0 + BV 1200 IBV 1.00E-03 VPK 1200 .ENDS * End of GA10SICP12-263 SPICE Model