GA10SICP12-247 GENESIC | Alldatasheet
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Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 1 of 8 Silicon Carbide Junction Transistor/Schottky Diode Co-pack Features Package 175°C Maximum Operating Temperature Gate Oxide free SiC switch Exceptional Safe Operating Area Integrated SiC Schottky Rectifier Excellent Gain Linearity Temperature Independent Switching Performance Low output capacitance Positive temperature co-efficient of R DS,ON Suitable for connecting an anti-parallel diode RoHS Compliant TO-247AB Advantages Applications Compatible with Si MOSFET/IGBT Gate Drive ICs > 20 µs Short-Circuit Withstand Capability Lowest-in-class Conduction Losses High Circuit Efficiency Minimal Input Signal distortion High Amplifier Bandwidth Reduced cooling requirements Reduced system size Down Hole Oil Drilling, Geothermal Instrumentation Hybrid Electric Vehicles (HEV) Solar Inverters Switched-Mode Power Supply (SMPS) Power Factor Correction (PFC) Induction Heating Uninterruptible Power Supply (UPS) Motor Drives Maximum Ratings at Tj = 175 °C, unless otherwise specified Parameter Symbol Conditions Values Unit SiC Junction Transistor Drain – Source Voltage V DS VGS = 0 V 1200 V Continuous Drain Current I D TC,MAX = 95 °C 10 A Gate Peak Current I GM 10 A Turn-Off Safe Operating Area RBSOA TVJ = 175 oC, IG = 1 A, Clamped Inductive Load ID,max = 10 @ VDS ≤ VDSmax A Short Circuit Safe Operating Area SCSOA TVJ = 175 oC, IG = 1 A, VDS = 800 V, Non Repetitive 20 µs Reverse Gate – Source Voltage V SG 30 V Reverse Drain – Source Voltage V SD 25 V Power Dissipation P tot TC = 95 °C 91 W Storage Temperature T stg -55 to 175 °C Free-wheeling Silicon Carbide diode DC-Forward Current I F TC ≤ 150 ºC 10 A Non Repetitive Peak Forward Current I FM TC = 25 ºC, tP = 10 μs 280 A Surge Non Repetitive Forward Current I F,SM tP = 10 ms, half sine, TC = 25 ºC 65 A Thermal Characteristics Thermal resistance, junction - case R thJC SiC Junction Transistor 0.88 °C/W Thermal resistance, junction - case R thJC SiC Diode 0.85 °C/W Mechanical Properties Mounting torque M 0.6 Nm G D S D VDS = 1200 V RDS(ON) = 120 mΩ ID (Tc = 25°C) = 25 A hFE (Tc = 25°C) 100
Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 2 of 8 Electrical Characteristics at Tj = 175 °C, unless otherwise specified Parameter Symbol Conditions Values Unit min. typ. max. SJT On-State Characteristics Drain – Source On Resistance R DS(ON) ID = 10 A, IG = 200 mA, Tj = 25 °C 120 mΩ ID = 10 A, IG = 400 mA, Tj = 125 °C 150 ID = 10 A, IG = 800 mA, Tj = 175 °C 220 Gate Forward Voltage V GS(FWD) IG = 500 mA, Tj = 25 °C 3.3 V IG = 500 mA, Tj = 175 °C 3.1 DC Current Gain h FE VDS = 5 V, ID = 10 A, Tj = 25 °C VDS = 5 V, ID = 10 A, Tj = 175 °C 100 TBD SJT Off-State Characteristics Drain Leakage Current I DSS VR = 1200 V, VGS = 0 V, Tj = 25 °C VR = 1200 V, VGS = 0 V, Tj = 125 °C 350 530 nA VR = 1200 V, VGS = 0 V, Tj = 175 °C 700 Gate Leakage Current I SG VSG = 20 V, Tj = 25 °C 20 nA SJT Capacitance Characteristics Input Capacitance C iss VGS = 0 V, VD = 1 V, f = 1 MHz tbd pF Reverse Transfer/Output Capacitance C rss/Coss VD = 1 V, f = 1 MHz tbd pF SJT Switching Characteristics Turn On Delay Time t d(on) VDD = 800 V, ID = 10 A, RG(on) = RG(off) = tbd Ω, FWD = GB10SLT12, Tj = 25 ºC Refer to Figure 15 for gate current waveform tbd ns Rise Time t r tbd ns Turn Off Delay Time t d(off) tbd ns Fall Time t f tbd ns Turn-On Energy Per Pulse E on tbd µJ Turn-Off Energy Per Pulse E off tbd µJ Total Switching Energy E ts tbd µJ Turn On Delay Time t d(on) VDD = 800 V, ID = 10 A, RG(on) = RG(off) = tbd Ω, FWD = GB10SLT12, Tj = 175 ºC Refer to Figure 15 for gate current waveform tbd Rise Time t r tbd ns Turn Off Delay Time t d(off) tbd ns Fall Time t f tbd ns Turn-On Energy Per Pulse E on tbd µJ Turn-Off Energy Per Pulse E off tbd µJ Total Switching Energy E ts tbd µJ Free-wheeling Silicon Carbide Schottky Diode Forward Voltage V F IF = 10 A, VGE = 0 V, Tj = 25 ºC (175 ºC ) 1.55 V Diode Knee Voltage V D(knee) Tj = 25 ºC, IF = 1 mA 0.8 V Peak Reverse Recovery Current I rrm IF = 10 A, VGE = 0 V, VR = 800 V, -dIF/dt = 625 A/µs, Tj = 175 ºC tbd A Reverse Recovery Time t rr tbd ns Rise Time t r VDD= 800 V, ID = 10 A, Rgon = Rgoff = tbd Ω, Tj= 25 ºC tbd ns Fall Time t f tbd ns Turn-On Energy Loss Per Pulse E on tbd μJ Turn-Off Energy Loss Per Pulse E off tbd μJ Reverse Recovery Charge Q rr tbd nC Rise Time t r VDD= 800 V, ID = 10 A, Rgon = Rgoff = tbd Ω, Tj= 175 ºC tbd ns Fall Time t f tbd ns Turn-On Energy Loss Per Pulse E on tbd μJ Turn-Off Energy Loss Per Pulse E off tbd μJ Reverse Recovery Charge Q rr tbd nC
Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 7 of 8 Gate Drive Theory of Operation for the GA10SICP12-263 The SJT transistor is a current controlled transistor which requires a positive gate curr ent for turn-on as well as to remain i n on-state. An ideal gate current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 22. Figure 22: Idealized Gate Current Waveform Gate Currents, IG,pk/-IG,pk and Voltages during Turn-On and Turn-Off An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, Q G, for turn-on is supplied by a burst of high gate current, IG,on, until the gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged. The IG,pon pulse should ideally terminate, when the drain voltage falls to its on-state value, in order to avoid unnecessary drive losses during the steady on-state. In practice, the rise time of the I G,on pulse is affected by the parasitic inductances, L par in the module and drive circuit. A voltage developed across the parasitic inductance in the source path, Ls, can de-bias the gate-source junction, when high drain currents begin to flow through the device. The applied gate voltage should be maintained high enough, above the VGS,ON level to counter these effects. A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. While sati sfactory turn off can be achieved with V GS = 0 V, a negative gate voltage V GS may be used in order to speed up the turn-off transition. Steady On-State After the device is turned on, I G may be advantageously lowered to I G,steady for reducing unnecessary gate drive losses. The I G,steady is determined by noting the DC current gain, hFE, of the device The desired I G,steady is determined by the peak device junction temperature T J during operation, drain current I D, DC current gain h FE, and a 50 % safety margin to ensure operating the device in the saturation region with low on-state voltage drop by the equation: ሻ1.5
Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 8 of 8 Package Dimensions: TO-247AB PACKAGE OUTLINE NOTE 1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER. 2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS
Revision History
Date Revision Comments Supersedes 2014/08/25 1 Gate Drive Theory Update 2013/09/12 0 Initial release Published by GeneSiC Semiconductor, Inc.
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Dulles, VA 20166 GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage.
June 2014 http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 1 of 1 SPICE Model Parameters This is a secure document. Please copy this code from the SPICE model PDF file on our website (http://www.genesicsemi.com/images/products_sic/igbt_copack/GA10SICP12-247_spice.pdf) into LTSPICE (version 4) software for simulation of the GA10SICP12-247. * MODEL OF GeneSiC Semiconductor Inc. * $Revision: 1.1 $ * $Date: 23-JUN-2014 $ * GeneSiC Semiconductor Inc. * 43670 Trade Center Place Ste. 155 * Dulles, VA 20166 * http://www.genesicsemi.com/index.php/sic-products/copack * COPYRIGHT (C) 2014 GeneSiC Semiconductor Inc. * ALL RIGHTS RESERVED * These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY * OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED * TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE." * Models accurate up to 2 times rated drain current. * Start of GA10SICP12-247 SPICE Model .SUBCKT GA10SIPC12 DRAIN GATE SOURCE Q1 DRAIN GATE SOURCE GA10SIPC12_Q D1 SOURCE DRAIN GA10SIPC12_D1 D2 SOURCE DRAIN GA10SIPC12_D2 .model GA10SIPC12_Q NPN + IS 5.00E-47 ISE 1.26E-28 EG 3.23 + BF 100 BR 0.55 IKF 350 + NF 1 NE 2 RB 6.97 + RE 0.01 RC 0.1 CJC 3.5E-10 + VJC 3 MJC 0.5 CJE 1.11E-09 + VJE 3 MJE 0.5 XTI 3 + XTB -1.2 TRC1 7.00E-03 MFG GeneSiC_Semi .MODEL GA10SIPC12_D1 D + IS 4.55E-15 RS 0.0736 N 1 + IKF 1000 EG 1.2 XTI -2 + TRS1 0.005434 TRS2 2.71739E-05 CJO 6.40E-10 + VJ 0.469 M 1.508 FC 0.5 + TT 1.00E-10 .MODEL GA10SIPC12_D2 D + IS 1.54E-22 RS 0.19 TRS1 -0.004 + N 3.941 EG 3.23 IKF 19 + XTI 0 FC 0.5 TT 0 .ENDS * End of GA10SICP12-247 SPICE Model