GA100SBJT12-FR4 GENESIC | Alldatasheet
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Technical content
Double Pulse Test Board GA100SBJT12-FR4 Sept 2014 http://www.genesicsemi.com/ Pg 2 of 6 Figure 3: Switching Test Board with Labeling MHV Voltage Connection High voltage for testing up to 1200 V is supplied to the Test Board through a MHV coaxial connection. Voltage may be generated through a high voltage power supply of choice. Capacitor Bank The capacitor bank is comprised of 20, 1 µF, 630 V capacitors t o store up to 3.6 J of energy to supply to the DUT. The bank in cludes 10 low effective series inductance (ESL) surface mount ceramic capacitors to allow DUT drain currents to rise and fall with minimal circuit interference. Thick 6 oz. copper traces on the Test Board also minimize this parasitic inductance and connect the capacitor bank to the test circuit. Voltage Balancing Network A voltage balancing network of two 1 MΩ, 2 W SMD resistors is used to ensure an equal potential is across the series connected capacitors on the Test Board along with two blocking rectifiers to protect against extreme overvoltage of the energy storage capacitors. External Load Inductor Connection A load inductor (not provided) is soldered directed to the HV a nd Drain nodes upon the connecti on pads provided. Care should b e taken to ensure the voltage rating of the inductor is not exceeded. Also, if the chosen inductor value is too large the capacitor bank may drain before the inductor is fully charged to the desired test current ID level. An inductance of Lload ≤ 1.0 mH is suggested. Device Under Test (DUT) and Free Wheeling Diode (FWD) The DUT and FWD are to be soldered into the connection terminals with minimal lead extending from the board, extra leads extending through the Test Board should be trimmed from the package to reduce ele ctrical noise which may distort measurement during ultra-fast, high-voltage switching which SJT devices are capable of. Devices may be conn ected to isolated hotplates while connected to the Test Board f or high- temperature testing as desired. It is also recommended to probe any device voltages (i.e. VGS, VDS) as close as possible to the device for accurate measurement and minimal testing induced voltage and current ringing. Gate Drive Conn. Drain Current Sensor Conn. DUT 5 µF Capacitor Bank MHV Voltage Conn. Voltage Balancing External Load Inductor Connection FWD
Double Pulse Test Board GA100SBJT12-FR4 Sept 2014 http://www.genesicsemi.com/ Pg 4 of 6 Figure 6: SJT 800V Switching Turn On Waveform Figure 7: SJT 800V Switching Turn Off Waveform
Double Pulse Test Board GA100SBJT12-FR4 Sept 2014 http://www.genesicsemi.com/ Pg 5 of 6 Top Side Copper Metallization Bottom Side Copper Metallization Figure 8: Test Board’s top and bottom copper pours.
Double Pulse Test Board GA100SBJT12-FR4 Sept 2014 http://www.genesicsemi.com/ Pg 6 of 6
Revision History
Date Revision Comments Supersedes 2014/09/15 0 Initial release Published by GeneSiC Semiconductor, Inc.
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Dulles, VA 20166 GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage.