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Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 1 of 11 Normally – OFF Silicon Carbide Junction Transistor Features Package

  • 175 °C Maximum Operating Temperature
  • Gate Oxide Free SiC Switch
  • Optional Gate Return Pin
  • Exceptional Safe Operating Area
  • Excellent Gain Linearity
  • Temperature Independent Switching Performance
  • Low Output Capacitance
  • Positive Temperature Coefficient of RDS,ON
  • Suitable for Connecting an Anti-parallel Diode Isolated Baseplate SOT-227 Advantages Applications
  • Compatible with Si MOSFET/IGBT Gate Drive ICs
  • > 20 µs Short-Circuit Withstand Capability
  • Lowest-in-class Conduction Losses
  • High Circuit Efficiency
  • Minimal Input Signal Distortion
  • High Amplifier Bandwidth
  • Reduced cooling requirements
  • Reduced system size
  • Down Hole Oil Drilling, Geothermal Instrumentation
  • Hybrid Electric Vehicles (HEV)
  • Solar Inverters
  • Switched-Mode Power Supply (SMPS)
  • Power Factor Correction (PFC)
  • Induction Heating
  • Uninterruptible Power Supply (UPS)
  • Motor Drives Table of Contents Section I: Absolute Maximum Ratings Parameter Symbol Conditions Value Unit Notes Drain – Source Voltage VDS VGS = 0 V 1700 V Continuous Drain Current ID TC = 25°C 160 A Fig. 17 Continuous Drain Current ID TC = 115°C 100 A Fig. 17 Continuous Gate Current IG 7 A Continuous Gate Return Current IGR 7 A Turn-Off Safe Operating Area RBSOA TVJ = 175 oC, Clamped Inductive Load ID,max = 100 @ VDS ≤ VDSmax A Fig. 19 Short Circuit Safe Operating Area SCSOA TVJ = 175 oC, IG = 1 A, VDS = 800 V, Non Repetitive >20 µs Reverse Gate – Source Voltage VSG 30 V Reverse Drain – Source Voltage VSD 25 V Power Dissipation Ptot TC = 25 °C / 115 °C, tp > 100 ms 535 / 214 W Fig. 16 Operating and storage temperature Tstg -55 to 175 °C G S GR D D S G GR VDS = 1700 V RDS(ON) = 10 mΩ ID (Tc = 25°C) = 160 A ID (Tc = 115°C) = 100 A hFE (Tc = 25°C) = 100 Please note: The Source and Gate Return pins are not exchangeable. Their exchange might lead to malfunction. Pin D - Drain Pin S - Source Pin GR - Gate Return Pin G - Gate

Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 2 of 11 Section II: Static Electrical Characteristics A: On State B: Off State C: Thermal Section III: Dynamic Electrical Characteristics A: Capacitance and Gate Charge B: SJT Switching Characteristics1 1 – All times are relative to the Drain-Source Voltage VDS Parameter Symbol Conditions Value Unit Notes Min. Typical Max. Drain – Source On Resistance RDS(ON) ID = 100 A, Tj = 25 °C ID = 100 A, Tj = 150 °C ID = 100 A, Tj = 175 °C mΩ Fig. 5 Gate – Source Saturation Voltage VGS,SAT ID = 100 A, ID/IG = 40, Tj = 25 °C ID = 100 A, ID/IG = 30, Tj = 175 °C 3.42 3.23 V Fig. 7 DC Current Gain hFE VDS = 8 V, ID = 100 A, Tj = 25 °C VDS = 8 V, ID = 100 A, Tj = 125 °C VDS = 8 V, ID = 100 A, Tj = 175 °C 100 105 – Fig. 4 Drain Leakage Current IDSS VDS = 1700 V, VGS = 0 V, Tj = 25 °C VDS = 1700 V, VGS = 0 V, Tj = 150 °C VDS = 1700 V, VGS = 0 V, Tj = 175 °C 100 100 μA Fig. 8 Gate Leakage Current ISG VSG = 20 V, Tj = 25 °C 40 nA Thermal resistance, junction - case RthJC 0.28 °C/W Fig. 20 Parameter Symbol Conditions Value Unit Notes Min. Typical Max. Input Capacitance Ciss VGS = 0 V, VDS = 1200 V, f = 1 MHz 14.3 nF Fig. 9 Reverse Transfer/Output Capacitance Crss/Coss VDS = 1200 V, f = 1 MHz 240 pF Fig. 9 Output Capacitance Stored Energy EOSS VGS = 0 V, VDS = 1200 V, f = 1 MHz 190 µJ Fig. 10 Effective Output Capacitance, time related Coss,tr ID = constant, VGS = 0 V, VDS = 0… 1200 V 370 pF Effective Output Capacitance, energy related Coss,er VGS = 0 V, VDS = 0… 1200 V 265 pF Gate-Source Charge QGS VGS = -5…3 V 120 nC Gate-Drain Charge QGD VGS = 0 V, VDS = 0… 1200 V 450 nC Gate Charge - Total QG 570 nC Internal Gate Resistance – ON RG(INT-ON) VGS > 2.5 V, VDS = 0 V, Tj = 175 ºC 0.1 Ω Turn On Delay Time td(on) Tj = 25 ºC, VDS = 1200 V, ID = 100 A, Resistive Load Refer to Section V for additional driving information. 13 ns Fall Time, VDS tf 50 ns Fig. 11, 13 Turn Off Delay Time td(off) 33 ns Rise Time, VDS tr 27 ns Fig. 12, 14 Turn On Delay Time td(on) Tj = 175 ºC, VDS = 1200 V, ID = 100 A, Resistive Load 15 ns Fall Time, VDS tf 50 ns Fig. 11 Turn Off Delay Time td(off) 40 ns Rise Time, VDS tr 30 ns Fig. 12 Turn-On Energy Per Pulse Eon Tj = 25 ºC, VDS = 1200 V, ID = 100 A, Inductive Load Refer to Section V. 3.5 mJ Fig. 11, 13 Turn-Off Energy Per Pulse Eoff 2.3 mJ Fig. 12, 14 Total Switching Energy Etot 5.8 mJ Turn-On Energy Per Pulse Eon Tj = 175 ºC, VDS = 1200 V, ID = 100 A, Inductive Load 3.55 mJ Fig. 11 Turn-Off Energy Per Pulse Eoff 2.4 mJ Fig. 12 Total Switching Energy Etot 5.95 mJ

Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 7 of 11 Section V: Driving the GA100JT17-227 Drive Topology Gate Drive Power Consumption Switching Frequency Application Emphasis Availability TTL Logic High Low Wide Temperature Range Coming Soon Constant Current Medium Medium Wide Temperature Range Coming Soon High Speed – Boost Capacitor Medium High Fast Switching Production High Speed – Boost Inductor Low High Ultra Fast Switching Coming Soon Proportional Lowest High Wide Drain Current Range Coming Soon Pulsed Power Medium N/A Pulse Power Coming Soon A: Static TTL Logic Driving The GA100JT17-227 may be driven with direct (5 V) TTL logic and current amplification. The amplified current level of the supply must meet or exceed the steady state gate current (I G,steady) required to operate the GA100JT17- 227. Minimum I G,steady is dependent on the antic ipated drain current I D through the SJT and the DC current gain h FE, it may be calculated from the following equation. An accurate value of the h FE may be read from Figure 5 . An optional resistor R G may be used in series with the gate pin to trim I G,steady, also an optional capacitor C G may be added in parallel with RG to facilitate faster SJT switching if desired, further details on these options are given in the following section. 𝐼𝐼𝐺𝐺,𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 ≈ 𝐼𝐼𝐷𝐷 ℎ𝐹𝐹𝐹𝐹(𝑇𝑇, 𝐼𝐼𝐷𝐷) ∗1.5 Figure 22: TTL Gate Drive Schematic B: High Speed Driving The SJT is a current controlled transistor which requires a positive gate current for turn- on and to remain in on-state. An idealized gate current waveform for ultra-fast switching of the SJT while maintaining low gate drive losses is shown in Figure 23, it features a positive current peak during turn-on, a negative current peak during turn-off, and continuous gate current during on-state. Figure 23: An idealized gate current waveform for fast switching of an SJT. An SJT is rapidly switched from its blocking state to on- state when the necessary gate charge, Q G, for turn -on is supplied by a burst of high gate current, IG,on, until the SJT gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged. 𝑄𝑄𝑜𝑜𝑜𝑜 = 𝐼𝐼𝐺𝐺,𝑜𝑜𝑜𝑜 ∗𝑠𝑠1 𝑄𝑄𝑜𝑜𝑜𝑜 ≥ 𝑄𝑄𝑔𝑔𝑠𝑠 + 𝑄𝑄𝑔𝑔𝑠𝑠 TTL Gate Signal 5 / 0 V TTL i/p

5 V D

S G GR CG RG IG,steady

Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 8 of 11 Ideally, IG,on should terminate when the drain voltage falls to its on- state value in order to avoid unnecessary drive losses during the steady on- state. In practice, the rise time of the IG,on pulse is affected by the parasitic inductances, L par in the device package and drive circuit. A voltage developed across the parasitic inductance in the source path, L s, can de-bias the gate-source junction, when high drain currents begin to flow through the device. The voltage applied to the gate pin should be maintained high enough, above the V GS,sat (see Figure 7) level to counter these effects. A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn- off. Turn off can be achieved with V GS = 0 V, however a negati ve gate voltage V GS may be used in order to speed up the turn-off transition. Gate Return Pin The optional gate return (GR) pin allows for a reduction of source path inductive and resistive coupling in the gate driver c onnection to the GA100JT17-227. Drain currents through the source pin during transient and steady state operation induce an undesirable source voltage i n all power transistors due to unavoidable source pin inductance and resistance. This voltage can negatively affect gate driving performance, however the gate return pin allows for decoupling from these source current path effects which results in faster switching and higher efficiency gate driving. B:1: High Speed, Low Loss Drive with Boost Capacitor, GA15IDDJT22-FR4 The GA100JT17-227 may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology in which multiple voltage levels, a gate resistor, and a gate capacitor are used to provide fast switching current peaks at turn -on and turn-off and a continuous gate current whil e in on-state. An evaluation gate drive board ( GA15IDDJT22-FR4) utilizing this topology is commercially available for high and low- side driving, its datasheet provides additional details. Figure 24: Topology of the GA15IDDJT22-FR4 Two Voltage Source gate driver. The GA15IDDJT22-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre -installed for an effective gate resistance of RG = 0.7 Ω. It may be necessary for the user to reduce RG1 and/or RG2 under high drain current conditions for safe operation of the GA100JT17-227. The steady state current supplied to the gate pin of the GA100JT17-227 with on-board RG = 0.7 Ω, is shown in Figure 25. The maximum allowable safe value of RG for the user’s required drain current can be read from Figure 26. For the GA100JT17-227, RG must be reduced for ID ≥ ~40 A for safe operation with the GA15IDDJT22-FR4. For operation at I D ≥ ~40 A, RG may be calculated from the following equation, which contains the DC current gain hFE and the gate -source saturation voltage VGS,sat (Figure 7). 𝑅𝑅𝐺𝐺,𝑚𝑚𝑠𝑠𝑚𝑚 = 4.7𝑉𝑉 −𝑉𝑉𝐺𝐺𝐺𝐺,𝑠𝑠𝑠𝑠𝑠𝑠∗ℎ𝐹𝐹𝐹𝐹(𝑇𝑇, 𝐼𝐼𝐷𝐷) 𝐼𝐼𝐷𝐷 ∗1.5 −0.1Ω IGGate Source D S G GR CG2 VGH R1 U4 VGL VEE VGL VGH VEE VEE VGL VEE CG1 RG1 RG2 C21 +12 V +12 V VCC High VCC High RTN VCC Low VCC Low RTN Signal Signal RTN VGL VEE C10 GA15IDDJT22-FR4 Gate Driver Board

Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 11 of 11 Section VI: Package Dimensions SOT-227 PACKAGE OUTLINE NOTE 1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER. 2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS

Revision History

Date Revision Comments Supersedes 2015/12/07 1 Updated Electrical Characteristics 2015/09/16 0 Initial release Published by GeneSiC Semiconductor, Inc.

43670 Trade Center Place Suite 155

Dulles, VA 20166 GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage. 1.240 (31.5) 1.255 (31.88) 0.310 (7.87) 0.322 (8.18) R 3.97 0.163 (4.14) 0.169 (4.29) Ø 0.163 (4.14) 0.169 (4.29) 0.186 (4.72) 0.191 (4.85) 0.165 (4.19) 0.169 (4.29) 0.588 (14.9) 0.594 (15.09) 1.186 (30.1) 1.192 (30.28) 1.494 (37.9) 1.504 (38.20) 0.108 (2.74) 0.124 (3.15) 0.372 (9.45) 0.378 (9.60) 0.472 (11.9) 0.480 (12.19) 0.030 (0.76) 0.033 (0.84) 0.495 (12.5) 0.506 (12.85) 0.990 (25.1) 1.000 (25.40) 1.049 (26.6) 1.059 (26.90) 0.080 (2.03) 0.084 (2.13) 0.164 (4.16) 0.174 (4.42) 0.172 (4.37) 0.234 (5.94)

Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 1 of 1 Section VII: SPICE Model Parameters This is a secure document. Please copy this code from the SPICE model PDF file on our website (http://www.genesicsemi.com/images/products_sic/sjt/GA100JT17-227_SPICE.pdf) into LTSPICE (version 4) software for simulation of the GA100JT17-227. * MODEL OF GeneSiC Semiconductor Inc. * $Revision: 2.0 $ * $Date: 07-DEC-2015 $ * GeneSiC Semiconductor Inc. * 43670 Trade Center Place Ste. 155 * Dulles, VA 20166 * COPYRIGHT (C) 2015 GeneSiC Semiconductor Inc. * ALL RIGHTS RESERVED * These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY * OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED * TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE." * Models accurate up to 2 times rated drain current. * Start of GA100JT17-227 SPICE Model .SUBCKT GA100JT17 DRAIN GATE SOURCE QA DRAIN GATE SOURCE GA100JT17_Q QB DRAIN GATE SOURCE GA100JT17_Q .model GA100JT17_Q NPN + IS 9.833E-48 ISE 1.073E-26 EG 3.23 + BF 110 BR 0.55 IKF 9000 + NF 1 NE 2 RB 0.95 + RE 0.005 RC 0.014 CJC 2.12E-9 + VJC 3.788 MJC 0.537 CJE 6.026E-09 + VJE 3.1791 MJE 0.5295 XTI 3 + XTB -1.5 TRC1 9.0E-03 MFG GeneSiC_Semi + IRB 0.005 RBM 0.073 .ENDS * End of GA100JT17-227 SPICE Model