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Nov 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ Pg1 of 11 S D G Normally – OFF Silicon Carbide Junction Transistor Features Package 175 °C Maximum Operating Temperature Gate Oxide Free SiC Switch Exceptional Safe Operating Area Excellent Gain Linearity Temperature Independent Switching Performance Low Output Capacitance Positive Temperature Coefficient of R DS,ON Suitable for Connecting an Anti-parallel Diode RoHS Compliant TO-247 Advantages Applications Compatible with Si MOSFET/IGBT Gate Drive ICs > 20 µs Short-Circuit Withstand Capability Lowest-in-class Conduction Losses High Circuit Efficiency Minimal Input Signal Distortion High Amplifier Bandwidth Down Hole Oil Drilling, Geothermal Instrumentation Hybrid Electric Vehicles (HEV) Solar Inverters Switched-Mode Power Supply (SMPS) Power Factor Correction (PFC) Induction Heating Uninterruptible Power Supply (UPS) Motor Drives Table of Contents Section I: Absolute Maximum Ratings Parameter Symbol Conditions Value Unit Notes Drain – Source Voltage V DS VGS = 0 V 1200 V Continuous Drain Current I D TC = 25°C 15 A Fig. 17 Continuous Drain Current I D TC = 160°C 5 A Fig. 17 Continuous Gate Current I G 0.2 A Turn-Off Safe Operating Area RBSOA TVJ = 175 oC, Clamped Inductive Load ID,max = 5 @ VDS ≤ VDSmax A Fig. 19 Short Circuit Safe Operating Area SCSOA TVJ = 175 oC, IG = 0.2 A, VDS = 800 V, Non Repetitive > 20 µs Reverse Gate – Source Voltage V SG 30 V Reverse Drain – Source Voltage V SD 25 V Power Dissipation P tot TC = 25 °C / 160 °C, tp > 100 ms 106 / 10 W Fig. 16 Storage Temperature T stg -55 to 175 °C S G D D VDS = 1200 V RDS(ON) = 210 mΩ ID (Tc = 25°C) = 15 A ID (Tc > 125°C) = 5 A hFE (Tc = 25°C) = 80
Nov 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ Pg2 of 11 Section II: Static Electrical Characteristics A: On State B: Off State C: Thermal Section III: Dynamic Electrical Characteristics A: Capacitance and Gate Charge B: Switching1 1 – All times are relative to the Drain-Source Voltage VDS Parameter Symbol Conditions Value Unit Notes Min. Typical Max. Drain – Source On Resistance R DS(ON) ID = 5 A, Tj = 25 °C ID = 5 A, Tj = 125 °C ID = 5 A, Tj = 175 °C 210 316 408 m Ω Fig. 5 Gate – Source Saturation Voltage V GS,ON ID = 5 A, ID/IG = 40, Tj = 25 °C ID = 5 A, ID/IG = 30, Tj = 175 °C 3.45 3.22 V Fig. 7 DC Current Gain h FE VDS = 5 V, ID = 5 A, Tj = 25 °C VDS = 5 V, ID = 5 A, Tj = 125 °C VDS = 5 V, ID = 5 A, Tj = 175 °C – Fig. 5 Drain Leakage Current I DSS VDS = 1200 V, VGS = 0 V, Tj = 25 °C VDS = 1200 V, VGS = 0 V, Tj = 125 °C VDS = 1200 V, VGS = 0 V, Tj = 175 °C 0.1 0.1 μA Fig. 8 Gate Leakage Current I SG VSG = 20 V, Tj = 25 °C 20 nA Thermal resistance, junction - case R thJC 1.41 °C/W Fig. 20 Parameter Symbol Conditions Value Unit Notes Min. Typical Max. Input Capacitance C iss VGS = 0 V, VDS = 800 V, f = 1 MHz 668 pF Fig. 9 Reverse Transfer/Output Capacitance C rss/Coss VDS = 800 V, f = 1 MHz 19 pF Fig. 9 Output Capacitance Stored Energy E OSS VGS = 0 V, VDS = 800 V, f = 1 MHz 6 µJ Fig. 10 Effective Output Capacitance, time related Coss,tr ID = constant, VGS = 0 V, VDS = 0…800 V 35 pF Effective Output Capacitance, energy related Coss,er VGS = 0 V, VDS = 0…800 V 25 pF Gate-Source Charge Q GS VGS = -5…3 V 5 nC Gate-Drain Charge Q GD VGS = 0 V, VDS = 0…800 V 28 nC Gate Charge - Total Q G 33 nC Internal Gate Resistance – zero bias R G(INT-ZERO) f = 1 MHz, VAC = 50 mV, VDS = 0 V, VGS = 0 V, Tj = 175 ºC 5.7 Ω Internal Gate Resistance – ON R G(INT-ON) VGS > 2.5 V, VDS = 0 V, Tj = 175 ºC 0.36 Ω Turn On Delay Time t d(on) Tj = 25 ºC, VDS = 800 V, ID = 5 A, Resistive Load Refer to Section V for additional driving information. 11 ns Fall Time, VDS t f 10 ns Fig. 11, 13 Turn Off Delay Time t d(off) 19 ns Rise Time, VDS t r 11 ns Fig. 12, 14 Turn On Delay Time t d(on) Tj = 175 ºC, VDS = 800 V, ID = 5 A, Resistive Load 9 ns Fall Time, VDS t f 10 ns Fig. 11 Turn Off Delay Time t d(off) 34 ns Rise Time, VDS t r 9 ns Fig. 12 Turn-On Energy Per Pulse E on Tj = 25 ºC, VDS = 800 V, ID = 5 A, Inductive Load Refer to Section V. 94 µJ Fig. 11, 13 Turn-Off Energy Per Pulse E off 8 µJ Fig. 12, 14 Total Switching Energy E tot 102 µJ Turn-On Energy Per Pulse E on Tj = 175 ºC, VDS = 800 V, ID = 5 A, Inductive Load 93 µJ Fig. 11 Turn-Off Energy Per Pulse E off 7 µJ Fig. 12 Total Switching Energy E tot 100 µJ
Nov 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ Pg8 of 11 Ideally, IG,pon should terminate when the drain voltage falls to its on-state value in order to avoid unnecessary drive losses during the stea dy on-state. In practice, the rise time of the I G,on pulse is affected by the parasitic inductances, L par in the device package and drive circuit. A voltage developed across the parasitic inductance in the source path, Ls, can de-bias the gate-source junction, when high drain currents begin to flow through the device. The voltage applied to t he gate pin should be maintained high enough, above the V GS,sat (see Figure 7) level to counter these effects. A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. While sati sfactory turn off can be achieved with V GS = 0 V, a negative gate voltage V GS may be used in order to speed up the turn-off transition. Two high-speed drive topologies for the SiC SJTs are presented below. B:1: High Speed, Low Loss Drive with Boost Capacitor, GA03IDDJT30-FR4 The GA05JT12-247 may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology in which multiple voltage level s, a gate resistor, and a gate capacitor are used to provide fast switchi ng current peaks at turn-on and turn-off and a continuous gate c urrent while in on-state. A 3 kV isolated evaluation gate drive board (GA03IDDJT30- FR4) utilizing this topology is commercially available for h igh and low- side driving, its datasheet provides additional details about this drive topology. Figure 24: Topology of the GA03IDDJT30-FR4 Two Voltage Source gate driver. The GA03IDDJT30-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective gate resistance of RG = 3.75 Ω. It may be necessary for the user to reduce RG1 and RG2 under high drain current conditions for safe operation of the GA05JT12-247. The steady state current supplied to the gate pin of the GA05JT12-247 with on-board RG = 3.75 Ω, is shown in Figure 25. The maximum allowable safe value of RG for the user’s required drain current can be read from Figure 26. For the GA05JT12-247, RG must be reduced for ID ≥ ~8 A for safe operation with the GA03IDDJT30-FR4. For operation at ID ≥ ~8 A, RG may be calculated from the following equati on, which contains the DC current gain hFE (Figure 6) and the gate- source saturation voltage VGS,sat (Figure 7). 1.5 െ0.6Ω
Nov 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ Pg11 of 11 Section VI: Package Dimensions TO-247 PACKAGE OUTLINE NOTE 1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER. 2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS
Revision History
Date Revision Comments Supersedes 2014/11/13 1 Updated Electric al Characteristics 2014/08/25 0 Initial release Published by GeneSiC Semiconductor, Inc.
43670 Trade Center Place Suite 155
Dulles, VA 20166 GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage. (15.748) (16.256) 0.620 0.640 Ø 0.140 (3.556) 0.143 (3.632) 0.065 (1.651) 0.083 (2.108) 0.040 (1.016) 0.016 (0.406) 0.031 (0.787) 0.059 (1.498) 0.098 (2.489) 0.171 (4.699) 0.208 (5.283) 0.075 (1.905) 0.115 (2.921) (4.318 REF.) 0.170 REF. (5.486) 0.216 0.819 0.844 (20.803) (21.438) 0.780 0.800 (19.812) (20.320) 0.177 MAX (4.496) 0.242 BSC. (6.147 BSC.) Ø 0.118 (3.00) 0.22 (5.59) Ø 0.283 (7.19) 0.652 (16.56) 0.55 (13.97) 0.236 (5.99) 0.054 (1.36) 0.012 (0.3) 0.045 (1.14) GA05JT12-247 XXXXXX Lot code
Aug 2014 http://www.genesicsemi.com/comme rcial-sic/sic-junction-transistors/ Pg 1 of 1 Section VII: SPICE Model Parameters This is a secure document. Please copy this code from the SPICE model PDF file on our website (http://www.genesicsemi.com/images/products_sic/sjt/GA05JT12-247_SPICE.pdf) into LTSPICE (version 4) software for simulation of the GA05JT12-247. * MODEL OF GeneSiC Semiconductor Inc. * $Revision: 2.0 $ * $Date: 25-AUG-2014 $ * GeneSiC Semiconductor Inc. * 43670 Trade Center Place Ste. 155 * Dulles, VA 20166 * COPYRIGHT (C) 2014 GeneSiC Semiconductor Inc. * ALL RIGHTS RESERVED * These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY * OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED * TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE." * Models accurate up to 2 times rated drain current. .model GA05JT12 NPN + IS 5.00E-47 + ISE 1.26E-28 + EG 3.23 + BF 88 + BR 0.55 + IKF 5000 + NF 1 + NE 2 + RB 10.49 + IRB 0.002 + RBM 0.32 + RE 0.005 + RC 0.2 + CJC 254E-12 + VJC 3.0423 + MJC 0.4619 + CJE 649.0E-1209 + VJE 2.8800 + MJE 0.4813 + XTI 3 + XTB -1.34 + TRC1 6.5E-3 + VCEO 1200 + ICRATING 5 + MFG GeneSiC_Semiconductor * End of GA05JT12 SPICE Model