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Dec 2014 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/ Pg 1 of 10 Normally – OFF Silicon Carbide Junction Transistor Features Package  225°C maximum operating temperature  Gate Oxide Free SiC Switch  Exceptional Safe Operating Area  Excellent Gain Linearity  Temperature Independent Switching Performance  Low Output Capacitance  Positive Temperature Coefficient of RDS,ON  Suitable for Connecting an Anti-parallel Diode  RoHS Compliant TO-46 Advantages Applications  Compatible with Si MOSFET/IGBT Gate Drive ICs  > 20 µs Short-Circuit Withstand Capability  Lowest-in-class Conduction Losses  High Circuit Efficiency  Minimal Input Signal Distortion  High Amplifier Bandwidth  Down Hole Oil Drilling  Geothermal Instrumentation  Solenoid Actuators  General Purpose High-Temperature Switching  Amplifiers  Solar Inverters  Switched-Mode Power Supply (SMPS)  Power Factor Correction (PFC) Table of Contents Section I: Absolute Maximum Ratings Parameter Symbol Conditions Value Unit Notes Drain – Source Voltage VDS VGS = 0 V 100 V Continuous Drain Current ID TJ = 225°C, TC = 25°C 5.8 A Fig. 21 Continuous Gate Current IGM 0.5 A Turn-Off Safe Operating Area RBSOA TVJ = 225°C, IG = 0.5 A, Clamped Inductive Load ID,max = 9 @ VDS ≤ VDSmax A Fig. 19 Short Circuit Safe Operating Area SCSOA TVJ = 225°C, IG = 0.5 A, VDS = 70 V, Non Repetitive >20 µs Reverse Gate – Source Voltage VSG 30 V Reverse Drain – Source Voltage VSD 25 V Power Dissipation Ptot TJ = 225°C, TC = 25°C 20 W Fig. 16 Operating and Storage Temperature Tstg -55 to 225 °C D S G D S G VDS = 100 V RDS(ON) = 240 mΩ ID (Tc = 25°C) = 9 A hFE (Tc = 25°C) = 110

Dec 2014 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/ Pg 2 of 10 Section II: Static Electrical Characteristics A: On State B: Off State C: Thermal Section III: Dynamic Electrical Characteristics A: Capacitance and Gate Charge B: Switching1 1 – All times are relative to the Drain-Source Voltage VDS Parameter Symbol Conditions Value Unit Notes Min. Typical Max. Drain – Source On Resistance RDS(ON) ID = 5 A, Tj = 25 °C ID = 5 A, Tj = 125 °C ID = 5 A, Tj = 175 °C ID = 5 A, Tj = 225 °C 240 368 455 620 mΩ Fig. 5 Gate – Source Saturation Voltage VGS,sat ID = 5 A, ID/IG = 40, Tj = 25 °C ID = 5 A, ID/IG = 30, Tj = 175 °C 3.45 3.22 V Fig. 7 DC Current Gain hFE VDS = 5 V, ID = 5 A, Tj = 25 °C VDS = 5 V, ID = 5 A, Tj = 125 °C VDS = 5 V, ID = 5 A, Tj = 175 °C VDS = 5 V, ID = 5 A, Tj = 225 °C 113 – Fig. 5 Drain Leakage Current IDSS VR = 100 V, VGS = 0 V, Tj = 25 °C VR = 100 V, VGS = 0 V, Tj = 125 °C VR = 100 V, VGS = 0 V, Tj = 225 °C 100 100 500 1000 μA Fig. 6 Gate Leakage Current ISG VSG = 20 V, Tj = 25 °C 20 nA Thermal resistance, junction - case RthJC Assumes thermal conduction through baseplate only actual value may be lower 9.86 °C/W Fig. 17 Parameter Symbol Conditions Value Unit Notes Min. Typical Max. Input Capacitance Ciss VGS = 0 V, VD = 100 V, f = 1 MHz 547 pF Fig. 7 Reverse Transfer/Output Capacitance Crss/Coss VD = 100 V, f = 1 MHz 45 pF Fig. 7 Output Capacitance Stored Energy EOSS VGS = 0 V, VD = 100 V, f = 1 MHz 0.2 µJ Fig. 8 Effective Output Capacitance, time related Coss,tr ID = constant, VGS = 0 V, VDS = 0…70 V 83 pF Effective Output Capacitance, energy related Coss,er VGS = 0 V, VDS = 0…70 V 67 pF Gate-Source Charge QGS VGS = -5…3 V 3.7 nC Gate-Drain Charge QGD VGS = 0 V, VDS = 0…70 V 5.8 nC Gate Charge - Total QG 9.5 nC Internal Gate Resistance – zero bias RG(INT-ZERO) f = 1 MHz, VAC = 50 mV, VDS = VGS = 0 V , Tj = 225 ºC 14.5 Ω Internal Gate Resistance – ON RG(INT-ON) VGS > 2.5 V, VDS = 0 V, Tj = 225 ºC 0.37 Ω Turn On Delay Time td(on) Tj = 25 ºC, VDS = 70 V, ID = 5 A, Resistive Load Refer to Section V: for additional driving information 8.0 ns Fall Time, VDS tf 7.4 ns Fig. 11, 13 Turn Off Delay Time td(off) 14.0 ns Rise Time, VDS tr 4.2 ns Fig. 12, 14 Turn On Delay Time td(on) Tj = 225 ºC, VDS = 70 V, ID = 5 A, Resistive Load Refer to Section V: for additional driving information 8.0 ns Fall Time, VDS tf 7.8 ns Fig. 11 Turn Off Delay Time td(off) 28.0 ns Rise Time, VDS tr 2.3 ns Fig. 12 Turn-On Energy Per Pulse Eon Tj = 25 ºC, VDS = 70 V, ID = 5 A, Inductive Load 3.6 µJ Fig. 11, 13 Turn-Off Energy Per Pulse Eoff 0.4 µJ Fig. 12, 14 Total Switching Energy Etot 4.0 µJ Turn-On Energy Per Pulse Eon Tj = 225 ºC, VDS = 70 V, ID = 5 A, Inductive Load 3.6 µJ Fig. 11 Turn-Off Energy Per Pulse Eoff 0.5 µJ Fig. 12 Total Switching Energy Etot 4.1 µJ

Dec 2014 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/ Pg 10 of 10 Section VI: Package Dimensions TO-46 PACKAGE OUTLINE NOTE 1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER. 2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS

Revision History

Date Revision Comments Supersedes 2014/12/12 1 Updated Electrical Characteristics 2014/08/25 0 Initial release Published by GeneSiC Semiconductor, Inc.

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Dulles, VA 20166 GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage.

Dec 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 1 of 1 Section VII: SPICE Model Parameters This is a secure document. Please copy this code from the SPICE model PDF file on our website (http://www.genesicsemi.com/images/hit_sic/sjt/GA05JT01-46_SPICE.pdf into LTSPICE (version 4) software for simulation of the GA05JT01- 46. * MODEL OF GeneSiC Semiconductor Inc. * $Revision: 1.0 $ * $Date: 12-DEC-2014 $ * GeneSiC Semiconductor Inc. * 43670 Trade Center Place Ste. 155 * Dulles, VA 20166 * COPYRIGHT (C) 2014 GeneSiC Semiconductor Inc. * ALL RIGHTS RESERVED * These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY * OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED * TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE." * Models accurate up to 2 times rated drain current. .model GA05JT01 NPN + IS 9.8338E-48 + ISE 1.0733E-26 + EG 3.23 + BF 135 + BR 0.55 + IKF 200 + NF 1 + NE 2. + RB 14.5 + IRB 0.002 + RBM 0.37 + RE 0.01 + RC 0.23 + CJC 2.16E-10 + VJC 3.656 + MJC 0.4717 + CJE 5.021E-10 + VJE 2.95 + MJE 0.4867 + XTI 3 + XTB - 1.0 + TRC1 1.050E-2 + VCEO 100 + ICRATING 9 + MFG GeneSiC_Semiconductor * End of GA05JT01 SPICE Model