HGTG30N60A4 INTERSIL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 8

Technical content

Features

  • >100kHz Operation at 390V, 30A
  • 200kHz Operation at 390V, 18A
  • 600V Switching SOA Capability J = 125oC
  • Low Conduction Loss
  • Temperature Compensating SABER Model www.intersil.com Packaging JEDEC STYLE TO-247

Ordering Information

HGTG30N60A4 TO-247 G30N60A4 NOTE: When ordering, use the entire part number. C E G COLLECTOR (FLANGE) C E G INTERSIL CORPORATION IGBT PRODUCT IS COVERED BY ONE OR MORE OF THE FOLLOWING U.S. PATENTS 4,364,073 4,417,385 4,430,792 4,443,931 4,466,176 4,516,143 4,532,534 4,587,713 4,598,461 4,605,948 4,620,211 4,631,564 4,639,754 4,639,762 4,641,162 4,644,637 4,682,195 4,684,413 4,694,313 4,717,679 4,743,952 4,783,690 4,794,432 4,801,986 4,803,533 4,809,045 4,809,047 4,810,665 4,823,176 4,837,606 4,860,080 4,883,767 4,888,627 4,890,143 4,901,127 4,904,609 4,933,740 4,963,951 4,969,027 Data Sheet January 2000

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified HGTG30N60A4 UNITS Collector Current Continuous Operating and Storage Junction Temperature Range . . . . TJ, TSTG -55 to 150 oC Maximum Lead Temperature for Soldering 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. Pulse width limited by maximum junction temperature. Electrical SpecificationsTJ = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Collector to Emitter Breakdown Voltage BVCES IC = 250µA, VGE = 0V 600 - - V Emitter to Collector Breakdown Voltage BVECS IC = 10mA, VGE = 0V 15 - - V Collector to Emitter Leakage Current I CES VCE = 600V T J = 25oC - - 250 µA TJ = 125oC - - 4.0 mA Collector to Emitter Saturation Voltage VCE(SAT) IC = 30A, VGE = 15V TJ = 25oC - 1.8 2.6 V TJ = 125oC - 1.6 2.0 V Gate to Emitter Threshold Voltage V GE(TH) IC = 250µA, VCE = 600V 4.5 5.2 7.0 V Gate to Emitter Leakage Current I GES VGE =±20V - - ±250 nA Switching SOA SSOA T J = 150oC, RG = 3Ω, VGE = 15V L = 100µH, VCE = 600V 150 - - A Gate to Emitter Plateau Voltage V GEP IC = 30A, VCE = 300V - 8.5 - V On-State Gate Charge Q g(ON) IC = 30A, VCE = 300V VGE = 15V - 225 270 nC VGE = 20V - 300 360 nC Current Turn-On Delay Time t d(ON)I IGBT and Diode at TJ = 25oC ICE = 30A VCE = 390V VGE =15V R G = 3Ω L = 200µH Test Circuit - (Figure 20) -2 5 - n s Current Rise Time t rI -1 2 - n s Current Turn-Off Delay Time t d(OFF)I - 150 - ns Current Fall Time t fI -3 8 - n s Turn-On Energy (Note 2) E ON1 - 280 - µJ Turn-On Energy (Note 2) E ON2 - 600 - µJ Turn-Off Energy (Note 3) E OFF - 240 350 µJ HGTG30N60A4

FIGURE 11. TURN-OFF DELAY TIME vs COLLECTOR TO FIGURE 12. FALL TIME vs COLLECTOR TO EMITTER FIGURE 13. TRANSFER CHARACTERISTIC FIGURE 14. GATE CHARGE WAVEFORMS FIGURE 15. TOTAL SWITCHING LOSS vs CASE FIGURE 16. TOTAL SWITCHING LOSS vs GATE RESISTANCE

20 TJ = 125oC, L = 200µH, VCE = 390V, VGE = 15V

Handling Precautions for IGBTs Insulated Gate Bipolar Transistors are susceptible to gate-insulation damage by the electrostatic discharge of energy through the devices. When handling these devices, care should be exercised to assure that the static charge built in the handler’s body capacitance is not discharged through the device. With proper handling and application procedures, however, IGBTs are currently being extensively used in production by numerous equipment manufacturers in military, industrial and consumer applications, with virtually no damage problems due to electrostatic discharge. IGBTs can be handled safely if the following basic precautions are taken: 1. Prior to assembly into a circuit, all leads should be kept shorted together either by the use of metal shorting springs or by the insertion into conductive material such as “ECCOSORBD™ LD26” or equivalent. 2. When devices are removed by hand from their carriers, the hand being used should be grounded by any suitable means - for example, with a metallic wristband. 3. Tips of soldering irons should be grounded. 4. Devices should never be inserted into or removed from circuits with power on. 5. Gate Voltage Rating- Never exceed the gate-voltage rating of V GEM . Exceeding the rated VGE can result in permanent damage to the oxide layer in the gate region. 6. Gate Termination- The gates of these devices are essentially capacitors. Circuits that leave the gate open- circuited or floating should be avoided. These conditions can result in turn-on of the device due to voltage buildup on the input capacitor due to leakage currents or pickup. 7. Gate Protection- These devices do not have an internal monolithic Zener diode from gate to emitter. If gate protection is required an external Zener is recommended. Operating Frequency Information Operating frequency information for a typical device (Figure 3) is presented as a guide for estimating device performance for a specific application. Other typical frequency vs collector current (I CE ) plots are possible using the information shown for a typical unit in Figures 5, 6, 7, 8, 9 and 11. The operating frequency plot (Figure 3) of a typical device shows f MAX1 or fMAX2 ; whichever is smaller at each point. The information is based on measurements of a typical device and is bounded by the maximum rated junction temperature. f MAX1 is defined by fMAX1 = 0.05/(td(OFF)I+ td(ON)I). Deadtime (the denominator) has been arbitrarily held to 10% of the on-state time for a 50% duty factor. Other definitions are possible. t d(OFF)I and td(ON)I are defined in Figure 21. Device turn-off delay can establish an additional frequency limiting condition for an application other than T JM . fMAX2 is defined by fMAX2 = (PD - PC )/(EOFF + EON2 ). The allowable dissipation (PD ) is defined by PD =( TJM -TC )/RθJC. The sum of device switching and conduction losses must not exceed P D . A 50% duty factor was used (Figure 3) and the conduction losses (PC ) are approximated by PC =( VCE x ICE )/2. EON2 and EOFF are defined in the switching waveforms shown in Figure 21. EON2 is the integral of the instantaneous power loss (ICE x VCE ) during turn-on and EOFF is the integral of the instantaneous power loss (ICE xV CE ) during turn-off. All tail losses are included in the calculation for EOFF ; i.e., the collector current equals zero (ICE = 0). HGTG30N60A4

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitewww.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 TO-247

3 LEAD JEDEC STYLE TO-247 PLASTIC PACKAGE

TERM. 4 - COLLECTOR A b c D E L ØR 1 2 3 1 ØS Q ØP BACK VIEW TERM. 4 e SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX A 0.180 0.190 4.58 4.82 - b 0.046 0.051 1.17 1.29 2, 3 b1 0.060 0.070 1.53 1.77 1, 2 b2 0.095 0.105 2.42 2.66 1, 2 c 0.020 0.026 0.51 0.66 1, 2, 3 D 0.800 0.820 20.32 20.82 - E 0.605 0.625 15.37 15.87 - e 0.219 TYP 5.56 TYP 4 e1 0.438 BSC 11.12 BSC 4 J1 0.090 0.105 2.29 2.66 5 L 0.620 0.640 15.75 16.25 - L1 0.145 0.155 3.69 3.93 1 ØP 0.138 0.144 3.51 3.65 - Q 0.210 0.220 5.34 5.58 - ØR 0.195 0.205 4.96 5.20 - ØS 0.260 0.270 6.61 6.85 - NOTES: 1. Lead dimension and finish uncontrolled in L1. 2. Lead dimension (without solder). 3. Add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 5. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 6. Controlling dimension: Inch. 7. Revision 1 dated 1-93. HGTG30N60A4