HGTG20N120C3D INTERSIL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 8

Technical content

Features

  • 45A, 1200V, TC = 25oC
  • 1200V Switching SOA Capability J = 150oC
  • Short Circuit Rating
  • Low Conduction Loss Symbol Packaging JEDEC STYLE TO-247

Ordering Information

HGTG20N120C3D TO-247 20N120C3D NOTE: When ordering, use the entire part number. INTERSIL CORPORATION IGBT PRODUCT IS COVERED BY ONE OR MORE OF THE FOLLOWING U.S. PATENTS 4,364,073 4,417,385 4,430,792 4,443,931 4,466,176 4,516,143 4,532,534 4,567,641 4,587,713 4,598,461 4,605,948 4,618,872 4,620,211 4,631,564 4,639,754 4,639,762 4,641,162 4,644,637 4,682,195 4,684,413 4,694,313 4,717,679 4,743,952 4,783,690 4,794,432 4,801,986 4,803,533 4,809,045 4,809,047 4,810,665 4,823,176 4,837,606 4,860,080 4,883,767 4,888,627 4,890,143 4,901,127 4,904,609 4,933,740 4,963,951 4,969,027 C E G G C E Data Sheet October 1998 File Number 4508.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified HGTG20N120C3D UNITS Collector Current Continuous CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Pulse width limited by maximum junction temperature. 2. VCE(PK) = 720V, TJ = 125oC, RGE = 3Ω. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Collector to Emitter Breakdown Voltage BVCES IC = 250µA, VGE = 0V 1200 - - V Collector to Emitter Leakage Current I CES VCE = BVCES TC = 25oC - - 150 µA TC = 150oC - - 2.0 mA Collector to Emitter Saturation Voltage VCE(SAT) IC = IC110 , VGE = 15V TC = 25oC - 2.4 3.0 V TC = 150oC - 2.2 2.9 V Gate to Emitter Threshold Voltage V GE(TH) IC = 250µA, VCE = VGE 5.0 7.0 7.5 V Gate to Emitter Leakage Current I GES VGE =±20V - - ±250 nA Switching SOA SSOA T J = 150oC, R G = 3Ω, VGE = 15V L = 100µH, VCE (PK)= 960V 60 - - A VCE (PK)= 1200V 20 - - A Gate to Emitter Plateau Voltage V GEP IC = IC110 , VCE = 0.5 BVCES - 9.4 - V On-State Gate Charge Q G(ON) IC = IC110 , VCE = 0.5 BVCES VGE = 15V - 93 130 nC VGE = 20V - 186 230 nC Current Turn-On Delay Time t d(ON)I IGBT and Diode at TJ = 25oC ICE = IC110 VCE = 0.8 BVCES VGE = 15V R G = 3Ω L = 1mH Test Circuit - (Figure 19) -3 9 - n s Current Rise Time t rI -2 2 - n s Current Turn-Off Delay Time t d(OFF)I - 110 - ns Current Fall Time t fI -9 5 - n s Turn-On Energy (Note 4) E ON1 - 950 - µJ Turn-On Energy (Note 4) E ON2 - 2250 - µJ Turn-Off Energy (Note 3) E OFF - 1200 2400 µJ HGTG20N120C3D

FIGURE 3. OPERATING FREQUENCY vs COLLECTOR TO FIGURE 4. SHORT CIRCUIT WITHSTAND TIME FIGURE 5. COLLECTOR TO EMITTER ON-STATE VOLTAGE FIGURE 6. COLLECTOR TO EMITTER ON-STATE VOLTAGE FIGURE 7. TURN-ON ENERGY LOSS vs COLLECTOR TO FIGURE 8. TURN-OFF ENERGY LOSS vs COLLECTOR TO

15.0 TJ = 25oC, TJ = 150oC, VGE = 12V

  1. Prior to assembly into a circuit, all leads should be kept

as “ECCOSORBD™ LD26” or equivalent.

  1. When devices are removed by hand from their carriers,

means - for example, with a metallic wristband.

  1. Tips of soldering irons should be grounded.
  2. Devices should never be inserted into or removed from
  3. Gate Voltage Rating- Never exceed the gate-voltage

permanent damage to the oxide layer in the gate region.

  1. Gate Termination- The gates of these devices are

on the input capacitor due to leakage currents or pickup.

  1. Gate Protection- These devices do not have an internal

protection is required an external Zener is recommended. MAX1 is defined by fMAX1 = 0.05/(td(OFF)I+ td(ON)I). d(OFF)I and td(ON)I are defined in Figure 20. allowable dissipation (PD ) is defined by PD =( TJM -TC )/RθJC. i.e., the collector current equals zero (ICE = 0). FIGURE 19. INDUCTIVE SWITCHING TEST CIRCUIT FIGURE 20. SWITCHING TEST WAVEFORMS ECCOSORBD‰ is a Trademark of Emerson and Cumming, Inc.

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitewww.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 HGTG20N120C3D TO-247

3 LEAD JEDEC STYLE TO-247 PLASTIC PACKAGE

A b c D E L ØR 1 2 3 1 ØS Q ØP BACK VIEW TERM. 4 e SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX A 0.180 0.190 4.58 4.82 - b 0.046 0.051 1.17 1.29 2, 3 b1 0.060 0.070 1.53 1.77 1, 2 b2 0.095 0.105 2.42 2.66 1, 2 c 0.020 0.026 0.51 0.66 1, 2, 3 D 0.800 0.820 20.32 20.82 - E 0.605 0.625 15.37 15.87 - e 0.219 TYP 5.56 TYP 4 e1 0.438 BSC 11.12 BSC 4 J1 0.090 0.105 2.29 2.66 5 L 0.620 0.640 15.75 16.25 - L1 0.145 0.155 3.69 3.93 1 ØP 0.138 0.144 3.51 3.65 - Q 0.210 0.220 5.34 5.58 - ØR 0.195 0.205 4.96 5.20 - ØS 0.260 0.270 6.61 6.85 - NOTES: 1. Lead dimension and finish uncontrolled in L1. 2. Lead dimension (without solder). 3. Add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 5. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 6. Controlling dimension: Inch. 7. Revision 1 dated 1-93.