G1421 GMT | Alldatasheet
Document overview
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Technical content
Features
Depop Circuitry Integrated Output Power at 1% THD+N, VDD=5V --1.8W/CH (typical) into a 4Ω Load --1.2W/CH (typical) into a 8Ω Load Eliminates Headphone Amplifier Output Cou- pling Capacitors Maximum Output Power Clamping Circuitry Integrated Bridge-Tied Load (BTL), Single-Ended (SE), and Stereo Headphone Amplifier (HP-IN) modes Supported Stereo Input MUX Mute and Shutdown Control Available Surface-Mount Power Package 24-Pin TSSOP-P
Applications
Stereo Power Amplifiers for Notebooks or Desktop Computers Multimedia Monitors Stereo Power Amplifiers for Portable Audio Systems General Description G1421 is a stereo audio power amplifier in 24pin TSSOP thermal pad package. It can drive 1.8W con- tinuous RMS power into 4 Ω load per channel in Bridge-Tied Load (BTL) mode at 5V supply voltage. Its THD is smaller than 1% under the above operation condition. To simplify the audio system design in the notebook application, G1421 supports the Bridge-Tied Load (BTL) mode for driving the speakers, Single-End (SE) mode for driving the headphone. In the HP-IN mode, it can support a DC value to the phone-jacket and drive the headphone without the audio amplifier outputs coupling capacitors. G1421 can mute the out- put when Mute-In is activated. For the low current consumption applications, the SHDN mode is sup- ported to disable G1421 when it is idle. The current consumption can be further reduced to below 5µA. G1421 also supports two input paths, that means two different gain loops can be set in the same PCB and choosing either one by setting HP/ LINE pin. It en- hances the hardware designing flexibility. G1421 also supports an extra function -- the maximum output power clamping function to protect the speakers or headphones from burned-out.
Ordering Information
(Pb free) TEMP. RANGE PACKAGE G1421 G1421f -40°C to +85°C TSSOP-24 (FD) Note: U: Tape & Reel ( F D ) : T h e r m a l P a d Pin Configuration ROUT+ RLINEIN RHPIN RBYPASS RVDD HP-IN HP/LINE ROUT- SE/BTL GND/HS LOUT+ LLINEIN LHPIN LBYPASS LVDD SHUTDOWN MUTE OUT LOUT- MUTE IN G1421 GND/HS TSSOP-24 (FD) TJ VOL Thermal Pad Top View Bottom View GND/HSGND/HS Note: Recommend connecting the Thermal Pad to the GND for excellent power dissipation. ROUT+ RLINEIN RHPIN RBYPASS RVDD HP-IN HP/LINE ROUT- SE/BTL GND/HS LOUT+ LLINEIN LHPIN LBYPASS LVDD SHUTDOWN MUTE OUT LOUT- MUTE IN G1421 GND/HS TSSOP-24 (FD) TJ VOL Thermal Pad Top View Bottom View GND/HSGND/HS Note: Recommend connecting the Thermal Pad to the GND for excellent power dissipation.
Ver: 1.6 Aug 04, 2005 TEL: 886-3-5788833 http://www.gmt.com.tw G1421Global Mixed-mode Technology Inc. Absolute Maximum Ratings Operating Ambient Temperature Range T Maximum Junction Temperature, TJ…..…………150°C Storage Temperature Range, TSTG… .…-65°C to+150°C Reflow Temperature (soldering, 10sec)………… 260°C Power Dissipation (1) Electrostatic Discharge, VESD Human body mode (2) Note: (1) : Recommended PCB Layout. (2) : Human body model : C = 100pF, R = 1500Ω, 3 positive pulses plus 3 negative pulses
Electrical Characteristics
PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT VDD =3.3V HP-IN --- 5.5 11 VDD = 5V HP-IN --- 6.5 14 Stereo BTL --- 7 13 VDD =3.3V Stereo SE --- 3.5 8 Stereo BTL --- 8 16 Supply Current I DD VDD = 5V Stereo SE --- 4 10 mA DC Differential Output Voltage V O(DIFF) V DD = 5V,Gain = 2 --- 5 50 mV Stereo BTL --- 8 16 HP-IN --- 6.5 14 Supply Current in Mute Mode I DD(MUTE) V DD = 5V Stereo SE --- 4 10 mA IDD in Shutdown I SD V DD = 5V --- 2 5 µA (AC Operation Characteristics, VDD = 5.0V, TA=+25°C, RL = 4Ω, unless otherwise noted) PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT THD = 1%, BTL, RL = 4Ω --- 1.8 --- THD = 1%, BTL, RL = 8Ω --- 1.12 --- THD = 10%, BTL, RL = 4Ω --- 2 --- THD = 10%, BTL, RL = 8Ω --- 1.4 --- W THD = 10%, SE, RL L = 8Ω --- 400 --- Output power (each channel) see Note P (OUT) mW PO = 1.6W, BTL, RL = 4Ω --- 500 --- PO = 1W, BTL, RL = 8Ω --- 150 --- PO = 75mW, SE, RL = 32Ω --- 20 --- Total harmonic distortion plus noise THD+N Maximum output power bandwidth B OM G = 1, THD =1% --- 20 --- kHz Phase margin RL = 4Ω, Open Load --- 60 --- ° Power supply ripple rejection PSRR f = 120Hz --- 75 --- dB Mute attenuation --- 85 --- dB Channel-to-channel output separation f = 1kHz --- 82 --- dB Line/HP input separation --- 80 --- dB BTL attenuation in SE mode --- 85 --- dB Input impedance ZI --- 2 --- MΩ Signal-to-noise ratio P O = 500mW, BTL --- 90 --- dB Output noise voltage V n Output noise voltage --- 55 --- µV (rms) Note :Output power is measured at the output terminals of the IC at 1kHz.
Ver: 1.6 Aug 04, 2005 TEL: 886-3-5788833 http://www.gmt.com.tw G1421Global Mixed-mode Technology Inc. (AC Operation Characteristics, VDD = 3.3V, TA=+25°C, RL = 4Ω, unless otherwise noted) PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT THD = 1%, BTL, RL = 4Ω --- 0.8 --- THD = 1%, BTL, RL = 8Ω --- 0.5 --- THD = 10%, BTL, RL = 4Ω --- 1 --- THD = 10%, BTL, RL = 8Ω --- 0.6 --- W THD = 10%, SE, RL L = 8Ω --- 180 --- Output power (each channel) see Note P (OUT) mW PO = 1.6W, BTL, RL = 4Ω --- 270 --- PO = 1W, BTL, RL = 8Ω --- 100 --- PO = 75mW, SE, RL = 32Ω --- 20 --- Total harmonic distortion plus noise THD+N Maximum output power bandwidth B OM G = 1, THD 1% --- 20 --- kHz Phase margin RL = 4Ω, Open Load --- 60 --- ° Power supply ripple rejection PSRR f = 120Hz --- 75 --- dB Mute attenuation --- 85 --- dB Channel-to-channel output separation f = 1kHz --- 80 --- dB Line/HP input separation --- 80 --- dB BTL attenuation in SE mode --- 85 --- dB Input impedance ZI --- 2 --- MΩ Signal-to-noise ratio P O = 500mW, BTL --- 90 --- dB Output noise voltage V n Output noise voltage --- 55 --- µV (rms) Note :Output power is measured at the output terminals of the IC at 1kHz.
Ver: 1.6 Aug 04, 2005 TEL: 886-3-5788833 http://www.gmt.com.tw G1421Global Mixed-mode Technology Inc. 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 Output P ow er (W) Power Dissipation (W) VD D =3.3V SE Eac h Channel RL=4Ω RL=8Ω RL=32Ω Figure 65 Recommended Minimum FootprintPower Dissipation vs Output Power TSSOP-24 (FD)
Ver: 1.6 Aug 04, 2005 TEL: 886-3-5788833 http://www.gmt.com.tw G1421Global Mixed-mode Technology Inc. Pin Description PIN NAME I/O FUNCTION 1,12,13,24 GND/HS Ground connection for circui try, directly connected to thermal pad. 2 TJ O Source a current inversely to the j unction temperature. This pin should be left uncon- nected during normal operation. For more in formation, see the junction temperature measurement section of this document. 3 LOUT+ O Left channel + output in BTL mode, + output in SE mode. 4 LLINE IN I Left channel line input, selected when HP/ pin is held low. 5 LHP IN I Left channel headphone input, se lected when HP/pin is held high. 6 LBYPASS Connect to voltage divider for left channel internal mid-supply bias. 7 LVDD I Supply voltage input for left c hannel and for primary bias circuits.
8 SHUTDOWN I Shutdown mode control signal inpu t, places entire IC in shutdown mode when held
high, IDD = 5µA. 9 MUTE OUT O Follows MUTE IN pin, provides buffered output. 10 LOUT- O Left channel - output in BTL mode, hi gh impedance state in SE mode. Supply VDD/2 to the phone jacket in HP-IN mode. 11 MUTE IN I Mute control si gnal input, hold low for normal operation, hold high to mute. 14 SE/ I Mode control signal input, hold lo w for BTL mode, hold high for SE mode. 15 ROUT- O Right channel - output in BT L mode, high impedance state in SE mode.
16 HP/ I MUX control input, hold high to select headphone inputs (5,20), hold low to select line
inputs (4,21).
17 HP-IN This pin can activate the HP-IN m ode to supplied the VDD/2 at LOUT- onto the phone
jacket. So the DC blocking capacitors can be removed in HP-IN type (like SE mode except no DC blocking capacitors). Hold high to activate this function. If this function is not used, it should be strongly tied to low. 18 RVDD I Supply voltage input for right channel. 19 RBYPASS Connect to voltage divider for right channel internal mid-supply bias. 20 RHP IN I Right channel headphone input, se lected when HP/pin is held high. 21 RLINE IN I Right channel line input, selected when HP/pin is held low. 22 ROUT+ O Right channel + output in BTL mode, + output in SE mode. 23 VOL I The output power can be clamped by setting a low bound voltage to this pin. The high bound voltage will be generated internally. T he output voltage will be clamped between high/low bound voltages. Then the output power is limited. It is weakly pull-low inter- nally, let this pin floating or tied to GND can deactivate this function. Thermal Pad Recommend connecting the Thermal P ad to the GND for excellent power dissipation.
Ver: 1.6 Aug 04, 2005 TEL: 886-3-5788833 http://www.gmt.com.tw G1421Global Mixed-mode Technology Inc. Block Diagram Parameter Measurement Information LEFT MUX MUTEIN RF RI CI CB 4.7µF LLINEIN LHPIN LBYPASS VOL SHUTDOWN HP-IN HP/LINE SE/BTL LVDD LOUT- LOUT+ RL 4/8/32ohm BTL Mode Test Circuit AC source LEFT MUX MUTEIN RF RI CI CB 4.7µF LLINEIN LHPIN LBYPASS VOL SHUTDOWN HP-IN HP/LINE SE/BTL LVDD LOUT- LOUT+ RL 4/8/32ohm BTL Mode Test Circuit AC source LEFT MUX _ 3 LLINEIN LHPIN LBYPASS 18RVDD LOUT- LOUT+ RIGHT MUXRHPIN RLINEIN 22ROUT+ ROUT- 7LVDD BIAS CIRCUITS MODES CONTROL CIRCUITS 2TJ SE/BTL HP/LINE HP-IN SHUTDOWN RBYPASS MUTEIN MUTEOUT VOL 20k 20k LEFT MUX _ 3 LLINEIN LHPIN LBYPASS 18RVDD LOUT- LOUT+ RIGHT MUXRHPIN RLINEIN 22ROUT+ ROUT- 7LVDD BIAS CIRCUITS MODES CONTROL CIRCUITS 2TJ SE/BTL HP/LINE HP-IN SHUTDOWN RBYPASS MUTEIN MUTEOUT VOL 20k 20k
Ver: 1.6 Aug 04, 2005 TEL: 886-3-5788833 http://www.gmt.com.tw G1421Global Mixed-mode Technology Inc. Parameter Measurement Information (Continued) LEFT MUX MUTEIN RF RI CI CB 4.7µF LLINEIN LHPIN LBYPASS VOL SHUTDOWN HP-IN HP/LINE SE/BTL LVDD LOUT- LOUT+ RL 32ohm SE Mode Test Circuit VDD AC source LEFT MUX MUTEIN RF RI CI CB 4.7µF LLINEIN LHPIN LBYPASS VOL SHUTDOWN HP-IN HP/LINE SE/BTL LVDD LOUT- LOUT+ RL 32ohm SE Mode Test Circuit VDD AC source LEFT MUX MUTEIN RF RI CI CB 4.7µF LLINEIN LHPIN LBYPASS VOL SHUTDOWN HP-IN HP/LINE SE/BTL LVDD LOUT- LOUT+ RL 32ohm HP-IN Mode (Non-DC Blocking Cap) Test Circuit VDD AC source LEFT MUX MUTEIN RF RI CI CB 4.7µF LLINEIN LHPIN LBYPASS VOL SHUTDOWN HP-IN HP/LINE SE/BTL LVDD LOUT- LOUT+ RL 32ohm HP-IN Mode (Non-DC Blocking Cap) Test Circuit VDD AC source
Ver: 1.6 Aug 04, 2005 TEL: 886-3-5788833 http://www.gmt.com.tw G1421Global Mixed-mode Technology Inc. Application Circuits With DC blocking Capacitors Application VOL HP-IN GND/HS ROUT+ RLINEIN RHPIN LVDD RVDD HP/LINE ROUT- SE/BTL GND/HS R 100KΩ 1KΩ PHONOJACK COUTR CFLRFL AUDIO SOURCE CILRIL R 100KΩCSR 4.7µF 1KΩ COUTR GND/HS TJ LOUT+ LLINEINRIR LHPIN LBYPASS RBYPASS SHUTDWON MUTE OUT LOUT- MUTE IN GND/HS CIR AUDIO SOURCE RFL 20KΩ CFR G1421 1 24 2 23 3 22 4 21 12 13 1411 10 15 91 6 205 10KΩ1µF 4.7µF 220µF 0.1µF 4.7µF 220µF 1µF 10KΩ 20KΩ VOL HP-IN GND/HS ROUT+ RLINEIN RHPIN LVDD RVDD HP/LINE ROUT- SE/BTL GND/HS R 100KΩ 1KΩ PHONOJACK COUTR CFLRFL AUDIO SOURCE CILRIL R 100KΩCSR 4.7µF 1KΩ COUTR GND/HS TJ LOUT+ LLINEINRIR LHPIN LBYPASS RBYPASS SHUTDWON MUTE OUT LOUT- MUTE IN GND/HS CIR AUDIO SOURCE RFL 20KΩ CFR G1421 1 24 2 23 3 22 4 21 12 13 1411 10 15 91 6 205 10KΩ1µF 4.7µF 220µF 0.1µF 4.7µF 220µF 1µF 10KΩ 20KΩ
Ver: 1.6 Aug 04, 2005 TEL: 886-3-5788833 http://www.gmt.com.tw G1421Global Mixed-mode Technology Inc. Application Circuits (Continued) No DC Blocking Capacitors Application Logical Truth Table INPUTS OUTPUT AMPLIFIER STATES SE/BTL HP/ LINE HP-IN Mute In Shutdown Mute Out Input L/R Out+ L Out- R Out- Mode X X X ---- High ---- X ---- ---- ---- Mute Low X X High ---- High X VDD/2 VDD/2 VDD/2 Mute High X X High ---- High X VDD/2 ---- ---- Mute X X High High ---- High X VDD/2 VDD/2 ---- Mute Low Low Low Low Low Low L/R Line BTL Output BTL Output BTL Output BTL Low High Low Low Low Low L/R HP BTL Output BTL Output BTL Output BTL High Low Low Low Low Low L/R Line SE Output ---- ---- SE High High Low Low Low Low L/R HP SE Output ---- ---- SE X Low High Low Low Low L/R Line SE Output VDD/2 ---- HP-IN X High High Low Low Low L/R HP SE Output VDD/2 ---- HP-IN GND/HS VOL ROUT+ RLINEIN RHPIN LVDD RVDD HP-IN HP/LINE ROUT- SE/BTL GND/HS PHONOJACK CFLRFL AUDIO SOURCE CILRIL GND/HS TJ LOUT+ LLINEINRIR LHPIN LBYPASS RBYPASS SHUTDWON MUTE OUT LOUT- MUTE IN GND/HS CIR AUDIO SOURCE RFR CFR G1421 1 24 2 23 32 2 4 21 12 13 1411 10 15 91 6 205 CBL RC 4.7Ω CC 0.1µF RC 4.7Ω CC 0.1µF 1µF 10KΩ 20KΩ 4.7µF 4.7µF 10KΩ1µF 20KΩ 4.7µF GND/HS VOL ROUT+ RLINEIN RHPIN LVDD RVDD HP-IN HP/LINE ROUT- SE/BTL GND/HS PHONOJACK CFLRFL AUDIO SOURCE CILRIL GND/HS TJ LOUT+ LLINEINRIR LHPIN LBYPASS RBYPASS SHUTDWON MUTE OUT LOUT- MUTE IN GND/HS CIR AUDIO SOURCE RFR CFR G1421 1 24 2 23 32 2 4 21 12 13 1411 10 15 91 6 205 CBL RC 4.7Ω CC 0.1µF RC 4.7Ω CC 0.1µF 1µF 10KΩ 20KΩ 4.7µF 4.7µF 10KΩ1µF 20KΩ 4.7µF
Ver: 1.6 Aug 04, 2005 TEL: 886-3-5788833 http://www.gmt.com.tw G1421Global Mixed-mode Technology Inc.
Application Information
There are two input signal paths – HP & Line. With the prompt setting, G1421 allows the setting of different gains for BTL and SE modes. Generally, speakers typically require approximately a factor of 10 more gain for similar volume listening levels as compared with headphones. SE Gain (HP) = -(R F(HP)/RI(HP)) BTL Gain(LINE) = -2(R F(LINE)/RI(LINE)) To achieve headphones and speakers listening parity, (RF(LINE/RI(LINE)) is suggested to be 5 times of (R F(HP)/ RI(HP)). The ratio of (R F(HP)/RI(HP)) can be determined by the applications. When the optimum distortion per- formance into the headphones (clear sound) is impor- tant, gain of –1 ((R F(HP) / RI(HP)) = 1) is suggested. Single Ended Mode Operation G1421 can drive clean, low distortion SE output power into headphone loads (generally 16 Ω or 32 Ω) as in Figure A. Please refer to Electrical Characteristics to see the performances. A coupling capacitor is needed to block the dc offset voltage, allowing pure ac signals into headphone loads. Choosing the coupling capaci- tor will also determine the 3 dB point of the high-pass filter network, as Figure B. f C=1/(2πRLCC) For example, a 68uF capacitor with 32 Ω headphone load would attenuate low frequency performance be- low 73Hz. So the coupling capacitor should be well chosen to achieve the excellent bass performance when in SE mode operation. Bridged-Tied Load Mode Operation G1421 has two linear amplifiers to drive both ends of the speaker load in Bridged-Tied Load (BTL) mode operation. Figure C shows the BTL configuration. The differential driving to the speaker load means that when one side is slewing up, the other side is slewing down, and vice versa. This configuration in effect will double the voltage swing on the load as compared to a ground reference load. In BTL mode, the peak-to-peak voltage V O(PP) on the load will be two times than a ground reference configuration. The voltage on the load is doubled, this will also yield 4 times output power on the load at the same power supply rail and loading. Another benefit of using differential driving configuration is that BTL operation cancels the dc off- sets, which eliminates the dc coupling capacitor that is needed to cancelled dc offsets in the ground reference configuration. Low-frequency performance is then lim- ited only by the input network and speaker responses. Cost and PCB space can be minimized by eliminating the dc coupling capacitors. VDD Vo(PP) Vo(PP) CC RL Figure A VDD Vo(PP) Vo(PP) CC RL Figure A -3 dB fc Figure B -3 dB fc Figure B VDD Vo(PP) VDD -Vo(PP) 2xVo(PP)RL Figure C VDD Vo(PP) VDD -Vo(PP) 2xVo(PP)RL Figure C
Ver: 1.6 Aug 04, 2005 TEL: 886-3-5788833 http://www.gmt.com.tw G1421Global Mixed-mode Technology Inc. HP-IN Mode Operation An internal weakly pull-up circuit is connected to HP-IN control pin (pin 17). When this pin is left un- connected or tied to VDD, HP-IN mode is activated, ignoring SE/ BTL setting. In normal SE/ BTL mode operations, this HP-IN pin should be tied to GND. In HP-IN mode, the linear amplifiers of LOUT+ (pin 3) /ROUT+ (pin 22) are still alive, the linear amplifier of ROUT- (pin 15) is deactivated, the linear amplifier of LOUT- (pin 10) supplies VDD/2 on this pin to cancel the dc offsets. (Please refer to Logical Truth Table and No DC CAP Application Circuit for detailed operation.) If connected VDD/2 on the LOUT- (pin 10) to the phone jacket, the dc offset can be eliminated without using coupling capacitors in headphone applications. By using HP-IN mode, cost and PCB space can be further minimized than traditional headphone applica- tions with coupling capacitors. The HP-IN configura- tion is shown on Figure D. Short circuit protection is implemented on LOUT- (pin10) to avoid the short-circuit damage caused by the sleeve of the phone jack connected to ground ac- cidentally during the module assembling. When short-circuit is detected, the linear amplifier of LOUT- (pin 10) will turn off for a period. After this period, it activates again. If the short circuit condition still exists, it will be turned off again. With this protection, the damage caused by larger dc short circuit current (from VDD/2 to GND) can be avoided. MUTE and SHUTDOWN Mode Operations G1421 implements the mute and shutdown mode operations to reduce supply current, I DD, to the ab- solute minimum level during nonuse periods for battery-power conservation. When the shutdown pin (pin 8) is pulled high, all linear amplifiers will be deactivated to mute the amplifier outputs. And G1421 enters an extra low current consumption state, I DD is smaller than 5 µA. If pulling mute-in pin (pin 11) high, it will force the activated linear ampli- fier to supply the VDD/2 dc voltage on the output to mute the AC performance. In mute mode operation, the current consumption will be a little different be- tween BTL, SE and HP-IN modes. (SE < HP-IN < BTL) Typically, the supply current is about 2.5mA in BTL mute operation. Shutdown and Mute-In pins should never be left unconnected, this floating con- dition will cause the amplifier operations unpredict- able. Maximum Power Clampping Function G1421 supports the maximum output power clamping function to avoid damaging the speaker when the am- plifier output a power beyond the speaker tolerance. The Vol pin (pin 23) is weakly pull-low internally. If inputting a non-zero voltage (low boundary voltage) to the Vol pin, G1421 will generate a high boundary voltage which the difference between the VDD/2 and the high boundary voltage is the same as the differ- ence between the VDD/2 and the low boundary volt- age. ( i.e. V OH – VDD/2 = VDD/2 – V OL ) Then the out- puts of linear amplifiers will be effectively limited be- tween the high/low boundary voltage, the maximum output power is clamped. By setting the voltage of Vol, the maximum output power can be well controlled. When the maximum power clamping function is not used, the Vol pin should be floated or tied to GND. VDD Vo(PP)+VDD/2 VDD/2 Vo(PP) VDD/2 RL Figure D VDD Vo(PP)+VDD/2 VDD/2 Vo(PP) VDD/2 RL Figure D
Ver: 1.6 Aug 04, 2005 TEL: 886-3-5788833 http://www.gmt.com.tw G1421Global Mixed-mode Technology Inc. Optimizing DEPOP Operation Circuitry has been implemented in G1421 to mini- mize the amount of popping heard at power-up and when coming out of shutdown mode. Popping oc- curs whenever a voltage step is applied to the speaker and making the differential voltage gener- ated at the two ends of the speaker. To avoid the popping heard, the bypass capacitor should be chosen promptly, 1/(C Bx100kΩ) ≦ 1/(C I*(RI+RF)). Where 100k Ω is the output impedance of the mid-rail generator, C B is the mid-rail bypass ca- pacitor, CI is the input coupling capacitor, R I is the input impedance, R F is the gain setting impedance which is on the feedback path. C B is the most im- portant capacitor. Besides it is used to reduce the popping, C B can also determine the rate at which the amplifier starts up dur ing startup or recovery from shutdown mode. De-popping circuitry of G1421 is shown on Figure E. The PNP transistor limits the voltage drop across the 50kΩ by slewing the internal node slowly when power is applied. At start-up, the voltage at BYPASS capacitor is 0. The PNP is ON to pull the mid-point of the bias circ uit down. So the capacitor sees a lower effective voltage, and thus the charg- ing is slower. This appears as a linear ramp (while the PNP transistor is c onducting), followed by the expected exponential ramp of an R-C circuit. Junction Temperature Measurement Characterizing a PCB layout with respect to thermal impedance is very difficult, as it is usually impossi- ble to know the junction temperature of the IC. G1421 TJ (pin 2) sources a current inversely pro- portional to the junction temperature. Typically TJ sources–120 µA for a 5V supply at 25 °C. And the slope is approximately 0.22 µA/°C. As the resistors have a tolerance of ±20%, these values should be calibrated on each device. When the temperature sensing function is not used, TJ pin can be left floating or tied to VDD to reduce the current con- sumption. Temperature sensing circuit is shown on Figure F. Bypass VDD 100 kΩ 100 kΩ 50 kΩ Figure E Bypass VDD 100 kΩ 100 kΩ 50 kΩ Figure E TJ VDD R R Figure F TJ VDD R R Figure F
Ver: 1.6 Aug 04, 2005 TEL: 886-3-5788833 http://www.gmt.com.tw G1421Global Mixed-mode Technology Inc.
Package Information
TSSOP-24(FD) Package NOTE: 1. Package body sizes exclude mold flash protrusions or gate burrs 2. Tolerance ±0.1mm unless otherwise specified 3. Coplanarity : 0.1mm 4. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact. 5. Die pad exposure size is according to lead frame design. 6. Follow JEDEC MO-153 DIMENSION IN MM DIMENSION IN INCH SYMBOLS MIN NOM MAX MIN NOM MAX E 6.40 BSC 0.252 BSC e 0.65 BSC 0.026 BSC Taping Specification PACKAGE Q’TY/REEL TSSOP-24 (FD) 2,500 ea GMT Inc. does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and GMT Inc. reserves the right at any time without notice to change said circuitry and specifications. Feed Direction Typical TSSOP Package Orientation Feed Direction Typical TSSOP Package Orientation E1 E D b A C L θ e Note 5 E1 E D b A C L θ e Note 5