FXPS7165D4 NXP | Alldatasheet
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Technical content
Datasheet sections
- 1 General description
- 2 Features and benefits
- 3 Applications
- 3.1 Automotive
- 3.2 Industrial
- 3.3 Medical/Consumer
- 4 Ordering information
- 4.1 Ordering options
- 5 Block diagram
- 6 Pinning information
- 6.1 Pinning
- 6.2 Pin description
- 7 Functional description
- 7.1 Voltage regulators
- 7.1.1 VCC, VREG, VREGA, undervoltage monitor
- 7.2 Internal oscillator
- 7.3 Pressure sensor signal path
- 7.3.1 Transducer
- 7.3.2 Self-test functions
- 7.3.2.1 PABS common mode verification
- 7.3.2.2 Startup digital self-test verification
- 7.3.2.3 Startup sense data fixed value verification
- 7.3.4 Digital signal processor (DSP)
- 7.3.4.1 Decimation sinc filter
- 7.3.4.2 Signal trim and compensation
- 7.3.4.3 Low-pass filter
- 7.3.4.4 Absolute pressure output data scaling
- 7.3.5 Temperature sensor
- 7.3.5.1 Temperature sensor signal chain
- 7.3.5.2 Temperature sensor output scaling equation
- 7.3.6 Common mode error detection signal chain
- 7.4 Inter-integrated circuit (I2C) interface
- 7.4.1 I2C bit transmissions
- 7.4.2 I2C start condition
- 7.4.3 I2C byte transmission
- 7.4.4 I2C acknowledge and not acknowledge
- 7.4.5 I2C stop condition
- 7.4.6 I2C register transfers
- 7.4.6.1 Register write transfers
- 7.4.6.2 Register read transfers
- 7.4.6.3 Sensor data register read wrap around
- 7.4.7 I2C timing diagram
- 7.5 Standard 32-bit SPI protocol
- 7.5.1 SPI command format
- 7.5.2 SPI response format
- 7.5.3 Command summary
- 7.5.3.1 Register read command
- 7.5.3.2 Register write command
- 7.5.3.3 Sensor data request commands
- 7.5.3.4 Reserved commands
- 7.5.4 Error checking
- 7.5.4.1 Default 8-bit CRC
- 7.5.5 Exception handling
- 7.5.5.1 Basic status field
- 7.5.5.2 Error responses
- 7.5.5.3 SPI error
- 7.5.5.4 SPI data output verification error
- 7.5.6 SPI timing diagram
- 7.6 User-accessible data array
- 7.7 Register information
- 7.7.1 COUNT - rolling counter register (address
- 7.7.2 Device status registers
- 7.7.2.1 DEVSTAT - device status register (address
- 7.7.2.2 DEVSTAT1 - device status register (address
- 7.7.2.3 DEVSTAT2 - device status register (address
- 7.7.2.4 DEVSTAT3 - device status register (address
- 7.7.3 TEMPERATURE - temperature register
- 7.7.4 DEVLOCK_WR - lock register writes register
- 7.7.5 UF_REGION_W, UF_REGION_R - UF
- 7.7.6 COMMTYPE - communication type register
- 7.7.7 SOURCEID_x - source identification
- 7.7.8 TIMING_CFG - communication timing
- 7.7.9 SPI Configuration Control Register (SPI_
- 7.7.9.1 SPI Data Field Size (DATASIZE)
- 7.7.9.2 SPI CRC Length and Seed Bits
- 7.7.10 WHO_AM_I - who am I register (address
- 7.7.11 I2C_ADDRESS - I2C slave address register
- 7.7.12 DSP Configuration Registers (DSP_CFG_
- 7.7.12.1 DSP_CFG_U1 - DSP user configuration #1
- 7.7.12.2 DSP_CFG_U4 - DSP user configuration #4
- 7.7.12.3 DSP_CFG_U5 - DSP user configuration #5
- 7.7.13 INT_CFG - interrupt configuration register
- 7.7.14 P_INT_HI, P_INT_LO - interrupt window
- 7.7.15 P_CAL_ZERO - pressure calibration
- 7.7.16 DSP_STAT - DSP specific status register
Digital absolute pressure sensor, 60 to 165 kPa Rev. 5 — 15 July 2019 Product data sheet
1 General description
The FXPS7165D4 high-performance, high-precision barometric absolute pressure (BAP) sensor consists of a compact capacitive micro-electro-mechanical systems (MEMS) device coupled with a digital integrated circuit (IC) producing a fully calibrated digital output. The sensor is based on NXP's high-precision capacitive pressure cell technology. The architecture benefits from redundant pressure transducers as an expanded quality measure. This sensor delivers highly accurate pressure and temperature readings through either a serial peripheral interface (SPI) or an inter-integrated circuit (I2C) interface. The FXPS7165D4 uses either a 3.3 V or 5.0 V power supply. Furthermore, the sensor employs an on-demand digital self-test for the digital IC and the MEMS transducers. The sensor operates over a pressure range of 60 kPa to 165 kPa and over a wide temperature range of −40 ºC to 130 ºC. The sensor comes in an industry-leading 4 mm x 4 mm x 1.98 mm, restriction of hazardous substances (RoHS) compliant, high power quad flat no lead (HQFN) package[1] suitable for small PCB integration. Its AEC-Q100[2] compliance, high accuracy, reliable performance and high media resistivity make it ideal for use in automotive, industrial, and consumer applications.
2 Features and benefits
- Absolute pressure range: 60 to 165 kPa
- Operating temperature range: –40 °C to 130 °C
- Pressure transducer and digital signal processor (DSP) – Digital self test
- I2C compatible serial interface – Slave mode operation – Standard mode, fast mode, and fast-mode plus support
- 32-bit SPI compatible serial interface – Sensor data transmission commands – 12-bit data for absolute pressure – 8-bit data for temperature – 2-bit basic status and 2-bit detailed status fields – 3, 4, or 8-bit configurable CRC
- Capacitance to voltage converter with anti-aliasing filter
- Sigma delta ADC plus sinc filter
- 800 Hz or 1000 Hz low-pass filter for absolute pressure
- Lead-free, 16-pin HQFN, 4 mm x 4 mm x 1.98 mm package
3 Applications
3.1 Automotive
- Comfort seating
- Small engine control
3.2 Industrial
- Compressed air
- Manufacturing line control
- Gas metering
- Weather stations
3.3 Medical/Consumer
- Blood pressure monitor
- Medicine dispensing systems
- White goods
4 Ordering information
Table 1. Ordering information
4.1 Ordering options
Table 2. Ordering options
5 Block diagram
Figure 1. Block diagram of FXPS7165D4
6 Pinning information
6.1 Pinning
17 TEST6
Figure 2. Pin configuration for 16-pin HQFN
6.2 Pin description
Table 3. Pin description
3 INT Interrupt output
recommends pin 3 be unterminated. Optionally, pin 3 can be tied to VSS.
8 SS_B Slave / Device select
resistor, as shown in the application diagram. pull-up device is connected to this pin. VCC with an external pull-up resistor, as shown in the application diagram.
10 MOSI SPI data in
pull-down device is connected to this pin.
11 MISO/SDA SPI/I2C data out
In SPI mode, pin 11 functions as the serial data output.
13 VCCIO I/O supply
Pin 13 must be connected to VCC, the device supply.
17 PAD Die attach pad
Pin 17 is the die attach flag, and must be connected to VSS.
7 Functional description
7.1 Voltage regulators
filter capacitor is required for VCC, as shown in Figure 23 and Figure 24. A reference generator provides a reference voltage for the ΣΔ converter.
Figure 3. Voltage regulation and monitoring
7.1.1 VCC, VREG, VREGA, undervoltage monitor
returns above the threshold, the device resumes responses.
7.2 Internal oscillator
The device includes a factory trimmed oscillator as specified in Table 101.
7.3 Pressure sensor signal path
7.3.1 Transducer
See Table 100 and Table 101 for transducer parameters.
NXP Semiconductors FXPS7165D4 Digital absolute pressure sensor, 60 to 165 kPa Product data sheet Rev. 5 — 15 July 2019
7.3.2 Self-test functions
The device includes analog and digital self-test functions to verify the functionality of the transducer and the signal chain. The self-test functions are selected by writing to the ST_CTRL[3:0] bits in the DSP_CFG_U1 register. The ST_CTRL bits select the desired self-test connection. Once the ENDINIT bit is set, the ST_CTRL bits are forced to '0000'. Future writes to the ST_CTRL bits are disabled until a device reset.
7.3.2.1 PABS common mode verification
When the PABS common mode self-test is selected, the ST_ACTIVE bit is set, the ST_ERROR is cleared and the device begins an internal measurement of the common mode signal of the P-cells and compares the result against a predetermined limit. If the result exceeds the limit, the ST_ERROR bit is set. The PABS common mode self-test repeats continuously every tST_INIT when the ST_CTRL bits are set to the specified value. Once the test is disabled, the ST_ERROR bit updates with the final test result within tST_INIT of disabling the test. The ST_ACTIVE bit remains set until the final test result is reported. Figure 4 is an example of a user-controlled self-test procedure.
Figure 4. User-controlled PABS common mode self-test flowchart
7.3.2.2 Startup digital self-test verification
NXP Semiconductors FXPS7165D4 Digital absolute pressure sensor, 60 to 165 kPa Product data sheet Rev. 5 — 15 July 2019 Table 4. Self-test control register
7.3.2.3 Startup sense data fixed value verification
Table 5. Self-test control bits for sense data fixed value verification
contents
0 1 0 0 DSP write to SNS_DATAx_ X registers inhibited. 0000h 0 1 0 1 DSP write to SNS_DATAx_ X registers inhibited. AAAAh 0 1 1 0 DSP write to SNS_DATAx_ X registers inhibited. 5555h 0 1 1 1 DSP write to SNS_DATAx_ X registers inhibited. FFFFh 7.3.3 ΣΔ converter A second order sigma delta modulator converts the voltage from the analog front end to a data stream that is input to the DSP. A simplified block diagram is shown in Figure 5. aaa-023446 z-1 1 - z-1 1 - bit quantizersecond integrator ADC V = +VREF, 0 V, -VREF Y(Z) = {0,1} β2 = 1 α2 = 1 DAC z-1 1 - z-1 first integrator V = C x Vx/CINT1 VX CTOP transducer C = CTOP - CBOT CBOT CINT1 β1 = 1 α1 = Figure 5. ΣΔ converter block diagram
7.3.4 Digital signal processor (DSP)
signal processing flow within the DSP is shown in Figure 6. Figure 6. Signal chain diagram
7.3.4.1 Decimation sinc filter
with a decimation ratio of 4. Figure 7. Sinc filter response
7.3.4.2 Signal trim and compensation
nonlinearity over temperature.
7.3.4.3 Low-pass filter
with the transfer function and coefficients shown in Equation 3.
Table 6. IIR low pass filter coefficients
1000 Hz (dB)
Figure 8. 800 Hz, 4-pole, low-pass filter response
Figure 11. 1000 Hz, 4-pole output signal delay
7.3.4.4 Absolute pressure output data scaling equation
7.3.5 Temperature sensor
7.3.5.1 Temperature sensor signal chain
The device includes a temperature sensor for signal compensation and user readability. specified in Table 100 and Table 101.
Figure 12. Temperature sensor signal chain block diagram
7.3.5.2 Temperature sensor output scaling equation
Table 7. Temperature conversion variables
7.3.6 Common mode error detection signal chain
The device includes a continuous pressure transducer common mode error detection. "DSP_STAT - DSP specific status register (address 60h)". Figure 13. Common mode error detection signal chain block diagram
7.4 Inter-integrated circuit (I2C) interface
and the total bus capacitance.
7.4.1 I2C bit transmissions
must be stable when SCL is high and change when SCL is low as shown in Figure 14. After the START signal has been transmitted by the master, the bus is considered busy. Timing for the start condition is specified in Table 101. Figure 14. I2C bit transmissions
7.4.2 I2C start condition
A bus operation is always started with a start condition (START) from the master. considered busy. Timing for the start condition is specified in Table 101. A start condition (START) and a repeat START condition (rSTART) are identical. Figure 15. I2C start condition
7.4.3 I2C byte transmission
receiver. Data is transferred with the most significant bit (MSB) first (see Figure 16). The master generates all clock pulses, including the ninth clock for the acknowledge bit. acknowledge clock pulse. Clock stretching is not used.
Figure 16. I2C byte transmissions
7.4.4 I2C acknowledge and not acknowledge transmissions
Table 101 must also be taken into account.
- No receiver is present on the bus with the transmitted address.
- The addressed receiver is unable to receive or transmit because it is performing some
real-time function and is not ready to start communication with the master.
- The receiver receives unrecognized data or commands.
- The receiver cannot receive any more data bytes.
- The master-receiver signals the end of the transfer to the slave transmitter.
repeated START to initiate a new transfer. An example ACK and NACK are shown in Figure 17. Figure 17. I2C acknowledge and not acknowledge transmission
7.4.5 I2C stop condition
A bus operation is always terminated with a stop condition (STOP) from the master. Figure 18. After the STOP has been transmitted by the master, the bus is considered free. Timing for the stop condition is specified in Table 101.
Figure 18. I2C stop condition
7.4.6 I2C register transfers
7.4.6.1 Register write transfers
- The master transmits a START condition.
- The master transmits the 7-bit slave address.
- The master transmits a '0' for the read/write bit to indicate a write operation.
- The slave transmits an ACK.
- The master transmits the register address to be written.
- The slave transmits an ACK.
- The master transmits the data byte to be written to the register address.
- The slave transmits an ACK.
- The master transmits a STOP condition.
- The master transmits a START condition.
- The master transmits the 7-bit slave address.
- The master transmits a '0' for the read/write bit to indicate a write operation.
- The slave transmits an ACK.
- The master transmits the register address to be written.
- The slave transmits an ACK.
- The master transmits the data byte to be written to the register address.
- The slave transmits an ACK.
- The master transmits the data byte to be written to the register address +1.
10.The slave transmits an ACK. 11.Repeat steps 9 and 10 until all registers are written. 12.The master transmits a STOP condition.
7.4.6.2 Register read transfers
- The master transmits a START condition.
- The master transmits the 7-bit slave address.
- The master transmits a '0' for the read/write bit to indicate a write operation.
- The slave transmits an ACK.
- The master transmits the register address to be read.
- The slave transmits an ACK.
- The master transmits a repeat START condition.
- The master transmits the 7-bit slave address.
- The master transmits a '1' for the read/write bit to indicate a read operation.
10.The slave transmits an ACK. 11.The slave transmits the data from the register addressed. 12.The master transmits a NACK. 13.The master transmits a STOP condition.
7.4.6.3 Sensor data register read wrap around
optimize the number of I2C transactions necessary for continuous reads of sensor data. Table 8. Sensor data register read wrap-around description
7.4.7 I2C timing diagram
Figure 19. I2C timing diagram
7.5 Standard 32-bit SPI protocol
Figure 20. Standard 32-Bit SPI protocol timing diagram
7.5.1 SPI command format
Table 9. SPI command format
Table 10. SPI command bit allocation
7.5.2 SPI response format
Table 11. SPI response format
7.5.3 Command summary
7.5.3.1 Register read command
address 8-bit registers in the register map.
- No SPI error is detected (see Section 7.5.5.3 "SPI error" )
- No MISO error is detected (see Section 7.5.5.4 "SPI data output verification error") If these conditions are met, the device responds to the register read request as shown responds with the error response as defined in Section 7.5.5.2 "Error responses". The register read response includes the register contents at the rising edge of SS_B for the register read command.
7.5.3.1.1 Register read command message format
Table 12. Register read command message format Table 13. Register read command message bit field descriptions RA[7:0] RA[7:1] contains the word address of the register to be read.
7.5.3.1.2 Register read response message format
Table 14. Register read response message format
Table 15. Register read response message bit field descriptions
7.5.3.2 Register write command
value specified in RD[7:0] to the register addressed by RA[7:0].
- No SPI error is detected (see Section 7.5.5.3 "SPI error")
- No MISO error is detected (see Section 7.5.5.4 "SPI data output verification error")
- The ENDINIT bit is cleared – This applies to all registers with the exception of the RESET[1:0] bits in the DEVLOCK_WR register
- No invalid register request is detected as described below If these conditions are met, the register write is executed and the device responds to the register write request as shown in Section 7.5.3.2.2 "Register write response message format". Otherwise, no register is written and the device responds with the error response as defined in Section 7.5.2 "SPI response format". The register is not written until the transfer during which the register write was requested has been completed. A register write command to a read-only register will not execute, but will result in a valid response.
7.5.3.2.1 Register write command message format
Table 16. Register write command message format Table 17. Register write command message bit field descriptions
7.5.3.2.2 Register write response message format
Table 18. Register write response message format Table 19. Register write response message bit field descriptions
7.5.3.3 Sensor data request commands
falling edge of SS_B for the sensor data request response.
7.5.3.3.1 Sensor data request command message format
Table 20. Sensor data request command message format Table 21. Sensor data request command message bit field descriptions
7.5.3.3.2 Sensor data request response message format
Table 22. Sensor data request response message format Table 23. Sensor data request response message bit field descriptions
7.5.3.4 Reserved commands
error handling conditions specified in Section 7.5.5 "Exception handling".
7.5.3.4.1 Reserved command message format
Table 24. Reserved command message format Table 25. Reserved command message bit field descriptions
7.5.3.4.2 Reserved command response message format
Table 26. Reserved command response message format
Table 27. Reserved command response message bit field descriptions
7.5.4 Error checking
7.5.4.1 Default 8-bit CRC
7.5.4.1.1 Command error checking
command is ignored and the device responds with the SPI error response.
- A seed value is preset into the LSB of the shift register.
- Using a serial CRC calculation method, the receiver rotates the received message
and CRC into the LSB of the shift register in the order received (MSB first).
- When the calculation on the last bit of the CRC is rotated into the shift register, the
shift register contains the CRC check result.
- If the shift register contains all zeros, the CRC is correct.
- If the shift register contains a value other than zero, the CRC is incorrect.
The CRC polynomial and seed are shown in Table 28. Table 28. SPI Command Message CRC
7.5.4.1.2 Response error checking
- A seed value is preset into the LSB of the shift register.
- Using a serial CRC calculation method, the transmitter rotates the transmitted
message and CRC into the LSB of the shift register (MSB first).
- Following the transmitted message, the transmitter feeds 8 zeros into the shift
register, to match the length of the CRC.
- When the last zero is fed into the input adder, the shift register contains the CRC.
The CRC polynomial and seed are shown in Table 29.
Table 29. SPI Response Message CRC
7.5.5 Exception handling
7.5.5.1 Basic status field
Table 30. Basic status field for responses to register commands
7.5.5.2 Error responses
Table 31. Error responses bit field descriptions
7.5.5.3 SPI error
- SCLK is high when SS_B is asserted
- The number of SCLK rising edges detected while SS_B is asserted is not equal to 16
- SCLK is high when SS_B is deasserted
- CRC error is detected (MOSI)
- A register write command to any register other than the DEVLOCK_WR register is received while ENDINIT is set If a SPI error is detected, the device responds with the error response as described in Section 7.5.5.2 "Error responses" with the detailed status field set to “SPI Error” as defined in Section 7.5.5.1 "Basic status field".
7.5.5.4 SPI data output verification error
The device includes a function to verify the integrity of the data output to the MISO pin. MISO_ERR flag in the DEVSTAT2 register is set. during the subsequent SPI message. Figure 21. SPI data output verification
7.5.6 SPI timing diagram
Figure 22. SPI timing diagram
7.6 User-accessible data array
incorporate independent data verification. Table 32. User-accessible data — sensor specific information
NXP Semiconductors FXPS7165D4 Digital absolute pressure sensor, 60 to 165 kPa Product data sheet Rev. 5 — 15 July 2019 BitAddress Register Type[1] 7 6 5 4 3 2 1 0 $45 INT_CFG UF2 reserved INT_PS[1:0] INT_ POLARITY reserved $47 P_INT_HI_H UF2 P_INT_HI_H[15:8] $49 P_INT_LO_H UF2 P_INT_LO_H[15:8] $4A reserved UF2 reserved $4B reserved UF2 reserved $4C P_CAL_ZERO_L UF2 P_CAL_ZERO_L[7:0] $4D P_CAL_ZERO_H UF2 P_CAL_ZERO_H[15:8] $4E reserved UF2 reserved $4F to $5E reserved UF2 reserved $5F CRC_UF2 F LOCK_UF2 0 0 0 CRC_UF2[3:0] $60 DSP_STAT R reserved PABS_HIGH PABS_LOW reserved ST_ INCMPLT ST_ACTIVE CM_ERROR ST_ERROR $61 DEVSTAT_ COPY R DSP_ERR reserved COMM_ERR MEMTEMP_ ERR SUPPLY_ ERR TESTMODE DEVRES DEVINT $62 SNSDATA0_L R SNSDATA0_L[7:0] $63 SNSDATA0_H R SNSDATA0_H[15:8] $64 SNSDATA1_L R SNSDATA1_L[7:0] $65 SNSDATA1_H R SNSDATA1_H[15:8] $66 SNSDATA0_ TIME0 R SNSDATA0_TIME[7:0] $67 SNSDATA0_ TIME1 R SNSDATA0_TIME[15:8] $68 SNSDATA0_ TIME2 R SNSDATA0_TIME[23:16] $69 SNSDATA0_ TIME3 R SNSDATA0_TIME[31:24] $6A SNSDATA0_ TIME4 R SNSDATA0_TIME[39:32] $6B SNSDATA0_ TIME5 R SNSDATA0_TIME[47:40] $6C P_MAX_L R P_MAX[7:0] $6D P_MAX_H R P_MAX[15:8] $6E P_MIN_L R P_MIN[7:0] $6F P_MIN_H R P_MIN[15:8] $70 to $77 reserved R reserved $78 FRT0 R FRT[7:0] $79 FRT1 R FRT[15:8] $7A FRT2 R FRT[23:16] $7B FRT3 R FRT[31:24] $7C FRT4 R FRT[39:32] $7D FRT5 R FRT[47:40] $7E to $9F reserved R reserved
NXP Semiconductors FXPS7165D4 Digital absolute pressure sensor, 60 to 165 kPa Product data sheet Rev. 5 — 15 July 2019 BitAddress Register Type[1] 7 6 5 4 3 2 1 0 Sensor Specific Information - User Readable Registers with OTP $A0 DSP_CFG_F F DEV_RANGE[3:0] reserved reserved reserved reserved $A1 to $AE reserved F reserved $AF CRC_F_A F LOCK_F_A REGA_BLOCKID[2:0] CRC_F_A[3:0] $B0 to $BE reserved F reserved $BF CRC_F_B F LOCK_F_B REGB_BLOCKID[2:0] CRC_F_B[3:0] Traceability Information $C0 ICTYPEID F ICTYPEID[7:0] $C1 ICREVID F ICREVID[7:0] $C2 ICMFGID F ICMFGID[7:0] $C3 reserved F reserved $C4 PN0 F PN0[7:0] $C5 PN1 F PN1[7:0] $C6 SN0 F SN[7:0] $C7 SN1 F SN[15:8] $C8 SN2 F SN[23:16] $C9 SN3 F SN[31:24] $CA SN4 F SN[39:32] $CB ASICWFR# F ASICWFR#[7:0] $CC ASICWFR_X F ASICWFR_X[7:0] $CD ASICWFR_Y F ASICWFR_Y[7:0] $CE reserved F reserved $CF CRC_F_C F LOCK_F_C REGC_BLOCKID[2:0] CRC_F_C[3:0] $D0 ASICWLOT_L F ASICWLOT_L[7:0] $D1 ASICWLOT_H F ASICWLOT_H[7:0] $D2 reserved — reserved $D3 reserved — reserved $D4 reserved — reserved $D5 reserved — reserved $D6 to $DE reserved F reserved $DF CRC_F_D F LOCK_F_D REGD_BLOCKID[2:0] CRC_F_D[3:0] $E0 USERDATA_0 UF2 USERDATA_0[7:0] $E1 USERDATA_1 UF2 USERDATA_1[7:0] $E2 USERDATA_2 UF2 USERDATA_2[7:0] $E3 USERDATA_3 UF2 USERDATA_3[7:0] $E4 USERDATA_4 UF2 USERDATA_4[7:0] $E5 USERDATA_5 UF2 USERDATA_5[7:0] $E6 USERDATA_6 UF2 USERDATA_6[7:0] $E7 USERDATA_7 UF2 USERDATA_7[7:0] $E8 USERDATA_8 UF2 USERDATA_8[7:0] $E9 USERDATA_9 UF2 USERDATA_9[7:0] $EA USERDATA_A UF2 USERDATA_A[7:0] $EB USERDATA_B UF2 USERDATA_B[7:0]
7.7 Register information
7.7.1 COUNT - rolling counter register (address 00h)
100 μs and the counter rolls over every 25.6 ms. Table 33. COUNT - rolling counter register (address 00h) bit allocation
7.7.2 Device status registers
The device status registers are read-only registers that contain device status information. These registers are readable in SPI or I2C mode.
7.7.2.1 DEVSTAT - device status register (address 01h)
Table 34. DEVSTAT - device status register (address 01h) bit allocation Table 35. DEVSTAT - device status register (address 01h) bit description
7 DSP_ERR The DSP error flag is set if a DSP specific error is present in the pressure signal DSP:
5 COMM_ERR The communication error flag is set if any bit in DEVSTAT3 is set:
4 MEMTEMP_ERR The memory error flag is set if any bit in DEVSTAT2 is set:
3 SUPPLY_ERR The supply error flag is set if any bit in DEVSTAT1 is set:
a test mode operation or by a power cycle. includes the error in the status field. is valid for read through one of the device communication interfaces (tPOR_DataValid).
7.7.2.2 DEVSTAT1 - device status register (address 02h)
Table 36. DEVSTAT1 - device status register (address 02h) bit allocation
Table 37. DEVSTAT1 - device status register (address 02h) bit description Table 100. See Section 7.1 for details on the VCC undervoltage monitor. This bit is cleared Table 100. See Section 7.1 for details on the VCC overvoltage monitor. A common timer is device communication interfaces (tPOR_DataValid). for read through one of the device communication interfaces (tPOR_DataValid). through one of the device communication interfaces (tPOR_DataValid). through one of the device communication interfaces (tPOR_DataValid).
0 CONT_ERR The continuity monitor passes a low current through a connection around the perimeter of
7.7.2.3 DEVSTAT2 - device status register (address 03h)
Table 38. DEVSTAT2 - device status register (address 03h) bit allocation
Table 39. DEVSTAT2 - device status register (address 03h) bit description 7 F_OTP_ERR The NXP factory OTP array error bit is set if a fault is detected in the factory OTP array. interface or on a data transmission that includes the error in the status field. data transmission that includes the error in the status field.
2 TEMP0_ERR The temperature error bit is set if an overtemperature or undertemperature condition
7.7.2.4 DEVSTAT3 - device status register (address 04h)
Table 40. DEVSTAT3 - device status register (address 04h) bit allocation
Table 41. DEVSTAT3 - device status register (address 04h) bit description
7 MISO_ERR In SPI mode, the MISO data mismatch flag is set when a MISO Data mismatch fault
7.7.3 TEMPERATURE - temperature register (address 0Eh)
Section 10 "Static characteristics ". Table 42. TEMPERATURE - temperature register (address 0Eh) bit allocation
7.7.4 DEVLOCK_WR - lock register writes register (address 10h)
Table 43. DEVLOCK_WR - lock register writes register (address 10h) bit allocation
Table 44. DEVLOCK_WR - lock register writes register (address 10h) bit description
7 ENDINIT The ENDINIT bit is a control bit used to indicate that the user has completed all device and
- An error detection is enabled for all user writable registers. The error detection code is continuously calculated on the user writable registers and verified against a previously calculated error detection code.
- Self-test is disabled and inhibited.
- Register writes are inhibited with the exception of the RESET[1:0] bits in the DEVLOCK_WR register. 3 SUP_ERR_DIS The supply error disable bit allows the user to disable reporting of the supply errors in the SPI status fields. 1 to 0 RESET[1:0] To reset the device, three consecutive register write operations must be performed in the order shown in Table 45, or the device will not reset. The response to a register write returns the new register value, including the values written to the RESET[1:0] bits. After the third register write command, the device initiates a reset and thus does not transmit an acknowledge. The response to a register read returns '00' for RESET[1:0] and terminates the reset sequence. The reset control bits are not included in the read/write array error detection.
Table 45. Device reset command sequence
7.7.5 UF_REGION_W, UF_REGION_R - UF region selection registers (address
the user read/write array error detection. UF_REGION_R register is readable in SPI mode or I2C mode. Table 46. UF_REGION_W - UF region selection register (address 14h) bit allocation
Table 47. UF_REGION_R - UF region selection register (address 15h) bit allocation ensure proper reading of the UF0, UF1 and F registers.
- Write the desired address range to be read to the REGION_LOAD[3:0] bits in the
Table 48. REGION_LOAD Bit Definitions
- Add a delay (Refer to appropriate Application Note for specific communication
- Optional: Execute a register read of the UF_REGION_R register and confirm the
Table 49. REGION_ACTIVE Bit Definitions
- Execute a Register Read of the desired registers from the UF0, UF1 or F register
section. Complete all desired Register Reads of the selected UF Region.
- Repeat steps 1 through 4 for the next desired UF region to read.
- The user must take care to ensure that the desired registers are addressed. For example, if the REGION_LOAD bits are set to Ah and the user executes a read of address $C2, the contents of registers $A2 will be transmitted. No error detection is included other than a read of the REGION_ACTIVE bits.
- For COMMTYPE options with multiple protocol options (COMMTYPE = '000' or '001'), no error detection is included other than a read of the REGION_ACTIVE bits. The user must take care to ensure that the REGION_LOAD, bits are not inadvertently changed by an alternative protocol while executing register reads.
- In SPI and I2C modes, once the ENDINIT bit is set, writes to registers other than the RESET[1:0] bits are inhibited. For this reason, reads of the UF0, UF1 and F registers will only be possible for the region selected by the REGION_ACTIVE bits at the time ENDINIT is set.
7.7.6 COMMTYPE - communication type register (address 16h)
to prevent disabling a necessary communication method. Table 50. COMMTYPE - communication type register (address 16h) bit allocation Table 51. COMMTYPE - communication type register (address 16h) bit description
110 I2C (pin 3 acts as an Interrupt)
111 I2C (pin 3 acts as an interrupt)
7.7.7 SOURCEID_x - source identification registers (address 1Ah, 1Bh)
Table 52. SOURCEID_0 - source identification register (address 1Ah) bit allocation Table 53. SOURCEID_1 - source identification register (address 1Bh) bit allocation
7.7.8 TIMING_CFG - communication timing register (address 22h)
writable in SPI mode or I2C mode. Table 54. TIMING_CFG - communication timing register (address 22h) bit allocation
7.7.9 SPI Configuration Control Register (SPI_CFG, Address 3Dh)
Table 55. SPI_CFG Register (address 3Dh) bit allocation
7.7.9.1 SPI Data Field Size (DATASIZE)
The SPI data field size bit controls the size of the SPI data field as shown in Table 56. Table 56. DATASIZE Bit Definition
7.7.9.2 SPI CRC Length and Seed Bits
polynomial value is enabled for both MISO and MOSI on the next SPI Mode command. for both MISO and MOSI on the next SPI Mode command. Table 57. SPI CRC Definition
7.7.10 WHO_AM_I - who am I register (address 3Eh)
unique product identifier. This register is included in the read/write array error detection. Table 58. WHO_AM_I - device identification register (address 3Eh) bit allocation transmitted in response to a read command. Table 59. WHO_AM_I register values
7.7.11 I2C_ADDRESS - I2C slave address register (address 3Fh)
in the read/write array error detection.
Table 60. I2C_ADDRESS - I2C slave address register (address 3Fh) bit allocation
7.7.12 DSP Configuration Registers (DSP_CFG_Ux)
and DSP_CFG_U3 registers are for factory use only and are used for internal tests.
7.7.12.1 DSP_CFG_U1 - DSP user configuration #1 register (address 40h)
Table 101. Reads of the SNSDATA_x registers and sensor data requests should be Table 61. DSP_CFG_U1 - DSP user configuration #1 register (address 40h) bit allocation Table 62. Low-pass filter selection bits (LPF[3:0])
Table 63. User range selection bits (USER_RANGE[1:0])
7.7.12.2 DSP_CFG_U4 - DSP user configuration #4 register (address 43h)
Table 64. DSP_CFG_U4 - DSP user configuration #4 register (address 43h) bit allocation Table 65. DSP_CFG_U4 - DSP user configuration #4 register (address 43h) bit description 7 to 4 reserved These bits are reserved. 2 INT_OUT The interrupt pin configuration bit selects the mode of operation for the interrupt pin. 1 to 0 reserved These bits are reserved.
7.7.12.3 DSP_CFG_U5 - DSP user configuration #5 register (address 44h)
configuration information. This register is included in the read/write array error detection. Table 66. DSP_CFG_U5 - DSP user configuration #5 register (address 44h) bit allocation Table 67. DSP_CFG_U5 - DSP user configuration #5 register (address 44h) bit description Table 68. The self-test control bits are not included in the read/write array error detection. 3 to 0 reserved These bits are reserved.
Table 68. Self Test Control Bits (ST_CTRL[3:0])
7.7.13 INT_CFG - interrupt configuration register (address 45h)
is set (see Section 7.7.4 "DEVLOCK_WR - lock register writes register (address 10h)"). The register is included in the read/write array error detection. Table 69. INT_CFG - interrupt configuration register (address 45h) bit allocation
Table 70. INT_CFG - interrupt configuration register (address 45h) bit description from the internal oscillator, so the tolerance on this oscillator applies. exist after the most recent evaluated sample. timer is zero, the interrupt pin is deasserted. The pulse stretch counter continuously decrements until it reaches zero. the most recent evaluated sample. programmed for activation either within or outside of a window.
7.7.14 P_INT_HI, P_INT_LO - interrupt window comparator threshold registers
is included in the read/write array error detection. Table 71. P_INT_HI, P_INT_LO - interrupt window comparator threshold registers (address 46h to 49h) bit allocation "Absolute pressure output data scaling equation". that threshold only. The interrupt comparison still functions for the opposite threshold.
7.7.15 P_CAL_ZERO - pressure calibration registers (address 4Ch, 4Dh)
is set (see Section 7.7.4 "DEVLOCK_WR - lock register writes register (address 10h)").
Table 72. P_CAL_ZERO - pressure calibration registers (address 4Ch, 4Dh) bit allocation to the values in the 16-bit SNSDATA registers. this register does not result in a compressed output range or a railed output.
7.7.16 DSP_STAT - DSP specific status register (address 60h)
Table 73. DSP_STAT - DSP specific status register (address 60h) bit allocation Table 74. DSP_STAT - DSP specific status register (address 60h) bit description interface or on a data transmission that includes the error in the status field.
interface or on a data transmission that includes the error in the status field. 0 — An analog or digital self-test has been activated since the last reset. 1 — No analog or digital self-test has been activated since the last reset. interface or on a data transmission that includes the error in the status field.
7.7.17 DEVSTAT_COPY - device status copy register (address 61h)
Table 75. DEVSTAT_COPY - device status copy register (address 61h) bit allocation
7.7.18 SNSDATA0_L, SNSDATA0_H - sensor data #0 registers (address 62h, 63h)
regarding the 16-bit sensor data. Table 76. SNSDATA0_L, SNSDATA0_H - sensor data #0 registers (addresses 62h, 63h) bit allocation
7.7.19 SNSDATA1_L, SNSDATA1_H - sensor data #1 registers (address 64h, 65h)
regarding the 16-bit sensor data. Table 77. SNSDATA1_L, SNSDATA1_H - sensor data #1 registers (address 64h, 65h) bit allocation
7.7.20 SNSDATA0_TIMEx - time stamp registers (address 66h to 6Bh)
I2C automatic sensor data register read wrap-around mode as documented in Table 8. stamp registers each time sensor data 0 data is latched for transmission via SPI. Table 78. SNSDATA0_TIMEx - time stamp register (address 66h to 6Bh) bit allocation
7.7.21 P_MAX, P_MIN - maximum and minimum absolute pressure value registers
register that changes the value of the LPF[2:0] or ST_CTRL[3:0]. SNSDATA_x registers. The error will always be within 2 kPa of each other. in sequence, P_xxx_L register first, followed by the P_xxx_H register. Table 79. P_Max and P_Min registers (address 6Ch to 6Fh) bit allocation
7.7.22 FRT - free running timer registers (addresses 78h to 7Dh)
Table 80. FRT - free running timer registers (addresses 78h to 7Dh) bit allocation
7.7.23 DSP_CFG_F Register
mode when ENDINIT is not set.
Table 81. Range Indication Bits (RANGE[3:0])
7.7.24 IC type register (Address C0h)
detection. This register is readable in SPI mode or I2C mode when ENDINIT is not set. Table 82. IC TYPE REGISTER (ICTYPEID address C0h) bit allocation
7.7.25 IC manufacturer revision register (Address C1h)
Table 83. IC MANUFACTURER REVISION REGISTER (ICREVID address C1h) bit allocation
7.7.26 IC manufacturer identification register (address C2h)
mode when ENDINIT is not set. Table 84. IC MANUFACTURER IDENTIFICATION REGISTER (ICMFGID address C2h) bit allocation
7.7.27 Part number register (address C4h, C5h)
mode when ENDINIT is not set. Table 85. PN0 Register (address C4h) bit allocation Table 86. PN1 Register (address C5h) bit allocation
7.7.28 Device serial number registers
Table 87. SN0 Register (address C6h) bit allocation
Table 88. SN1 Register (address C7h) bit allocation Table 89. SN2 Register (address C8h) bit allocation Table 90. SN3 Register (address C9h) bit allocation Table 91. SN4 Register (address CAh) bit allocation
7.7.29 ASIC wafer ID registers
wafer number, wafer X and Y coordinates and the wafer lot number for the device ASIC. registers are readable in SPI mode or I2C mode when ENDINIT is not set. Table 92. ASICWFR# Register (address CBh) bit allocation Table 93. ASICWFR_X Register (address CCh) bit allocation
Table 94. ASICWFR_Y Register (address CDh) bit allocation Table 95. ASICWLOT_L Register (address D0h) bit allocation Table 96. ASICWLOT_H Register (address D1h) bit allocation
7.7.30 USERDATA_0 to USERDATA_E - user data registers
7.7.31 USERDATA_10 to USERDATA_1E - user data registers
7.7.32 Lock and CRC Registers
the lock bit, the block identifier and the block OTP array CRC use for error detection. programmed to OTP using the Write OTP Enable register.
Table 97. Lock and CRC Register bit definitions
7.7.33 Reserved registers
a valid response. The data for reserved bits may be '0' or '1'. the reserved bits must always be '0' for normal device operation and performance.
7.7.34 Invalid register addresses
Section 7.6 "User-accessible data array" will not execute, but results in a valid response. The data for the registers will be '00h'. response. The data for the registers is the current content of the registers.
7.8 Read/write register array CRC verification
8 Maximum ratings
conditions for extended periods might affect device reliability. voltages higher than maximum-rated voltages to this high-impedance circuit. Table 98. Maximum ratings [1] Parameter verified by parametric and functional validation. [2] Parameter verified by qualification testing (Per AEC-Q100 Rev H or per NXP specification). [3] Functionality verified by modeling, simulation and/or design verification. [5] CDM tested at ±750 V for corner pins and ±500 V for all other pins. This device is sensitive to mechanical shock. Improper handling can cause permanent damage to the part. This is an ESD sensitive device. Improper handling can cause permanent damage to the part.
9 Operating range
Table 99. Electrical characteristics—supply and I/O VCC_min ≤ (VCC - VSS) ≤ VCC_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified. TA VCC = 5.0 V, unless otherwise stated. [1] Parameter tested 100 % at final test. [2] Parameter verified by parametric and functional validation.
10 Static characteristics
Table 100. Static characteristics VCC_min ≤ (VCC - VSS) ≤ VCC_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified.
PACC_HiT Absolute pressure accuracy VCC = 5.0 V. PACC_Typ Absolute pressure accuracy VCC = 5.0 V. PACC_LoT Absolute pressure accuracy VCC = 5.0 V. [1] Parameter verified by pass/fail testing at final test. [2] Functionality verified by modeling, simulation and/or design verification. [3] Parameter verified by parametric and functional validation. [4] Parameter verified by characterization. [5] Parameter tested 100 % at final test.
11 Dynamic characteristics
Table 101. Dynamic characteristics VCC_min ≤ (VCC – VSS) ≤ VCC_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified.
NXP Semiconductors FXPS7165D4 Digital absolute pressure sensor, 60 to 165 kPa Product data sheet Rev. 5 — 15 July 2019 Symbol Parameter Condition Min Typ Max Units tSCLL_100 tSCLL_400 tSCLL_1000 Clock (SCL) low time (30 % of VCC to 30 % of VCC) 100 kHz mode 400 kHz mode 1000 kHz mode [1] [1] [1] 4.70 1.30 0.50 μs μs μs tSRISE_100 tSRISE_400 tSRISE_1000 Clock (SCL) and data (SDA) rise time (30 % of VCC to 70 % of VCC) 100 kHz mode 400 kHz mode 1000 kHz mode [1] [1] [1] 1000 300 120 ns ns ns tSFALL_100 tSFALL_400 tSFALL_1000 Clock (SCL) and data (SDA) fall time (70 % of VCC to 30 % of VCC) 100 kHz mode 400 kHz mode 1000 kHz mode [1] [1] [1] 300 300 120 ns ns ns tSETUP_100 tSETUP_400 tSETUP_1000 Data input setup time (SDA = 30/70 % of VCC to SCL = 30 % of VCC) 100 kHz mode 400 kHz mode 1000 kHz mode [1] [1] [1] 250 100 ns ns ns tHOLD_100 tHOLD_400 tHOLD_1000 Data input hold time (SCL = 70 % of VCC to SDA = 30/70 % of VCC) 100 kHz mode 400 kHz mode 1000 kHz mode [1] [1] [1] 900 900 300 ns ns ns tSTARTSETUP_100 tSTARTSETUP_400 tSTARTSETUP_1000 Start condition setup time (SDA = 30/70 % of VCC to SCL = 30 % of VCC) 100 kHz mode 400 kHz mode 1000 kHz mode [1] [1] [1] 4.70 0.60 0.26 μs μs μs tSTARTHOLD_100 tSTARTHOLD_400 tSTARTHOLD_1000 Start condition hold time (SCL = 70 % of VCC to SDA = 30/70 % of VCC) 100 kHz mode 400 kHz mode 1000 kHz mode [1] [1] [1] 4.00 0.60 0.26 μs μs μs tSTOPSETUP_100 tSTOPSETUP_400 tSTOPSETUP_1000 Stop condition setup time (SDA = 30/70 % of VCC to SCL = 30 % of VCC) 100 kHz mode 400 kHz mode 1000 kHz mode [1] [1] [1] 4.00 0.60 0.26 μs μs μs tVALID_100 tVALID_400 tVALID_1000 SCLK low to data valid (SCL = 30 % of VCC to SDA = 30/70 % of VCC) 100 kHz mode 400 kHz mode 1000 kHz mode [1] [1] [1] 3.45 0.90 0.45 μs μs μs tFREE_100 tFREE_400 tFREE_1000 Bus free time (SDA = 70 % of VCC to SDA = 70 % of VCC) 100 kHz mode 400 kHz mode 1000 kHz mode [1] [1] [1] 4.00 1.30 0.50 μs μs μs CBUS Bus capacitive load [2] — — 400 pF SPI tSCLK Serial interface timing[3] Clock (SCLK) period (10 % of VCC to 10 % of VCC) [1] — 90 — ns tSCLKH Clock (SCLK) period (90 % of VCC to 90 % of VCC) [1] — 30 — ns tSCLKL Serial interface timing[3] Clock (SCLK) period (10 % of VCC to 10 % of VCC) [1] — 30 — ns tSCLKR Clock (SCLK) period (10 % of VCC to 90 % of VCC) [1] — 10 25 ns tSCLKF Serial interface timing[3] Clock (SCLK) period (90 % of VCC to 10 % of VCC) [1] — 10 25 ns tLEAD Serial interface timing[3] SS_B asserted to SCLK high (SS_B = 10 % of VCC to SCLK = 10 % of VCC) [1] — 50 — ns tACCESS Serial interface timing[3] SS_B asserted to SCLK high (SS_B = 10 % of VCC to MISO = 10/90 % of VCC) [1] — — 50 ns tSETUP Serial interface timing[3] SS_B asserted to SCLK high (MOSI = 10/90 % of VCC to SCLK = 10 % of VCC) [1] — 20 — ns
NXP Semiconductors FXPS7165D4 Digital absolute pressure sensor, 60 to 165 kPa Product data sheet Rev. 5 — 15 July 2019 Symbol Parameter Condition Min Typ Max Units tHOLD_IN MOSI data hold time (SCLK = 90 % of VCC to MOSI = 10/90 % of VCC) [1] — 10 — ns tHOLD_OUT Serial interface timing[3] MOSI data hold time (SCLK = 90 % of VCC to MISO = 10/90 % of VCC) [1] 0 — — ns tVALID Serial interface timing[3] SCLK low to data valid (SCLK = 10 % of VCC to MISO = 10/90 % of VCC) [1] — — 30 ns tLAG Serial interface timing[3] SCLK low to SS_B high (SCLK = 10 % of VCC to SS_B = 90 % of VCC) [1] — 60 — ns tDISABLE Serial interface timing[3] SS_B high to MISO disable (SS_B = 90 % of VCC to MISO = Hi Z) [1] — — 60 ns tSSN Serial interface timing[3] SS_B high to SS_B low (SS_B = 90 % of VCC to SS_B = 90 % of VCC) [1] — 500 — ns tSLKSS Serial interface timing[3] SCLK low to SS_B low (SCLK = 10 % of VCC to SS_B = 90 % of VCC) [1] — 50 — ns tSSCLK Serial interface timing[3] SS_B high to SCLK high (SS_B = 90 % of VCC to SCLK = 90 % of VCC) [1] — 50 — ns tLAT_SPI Data latency — — 1 ns Signal chain tSigChain Signal chain sample time [4] — 48 — μs fc0 Cutoff frequency, filter option #0, 4-pole [2] [4] — 800 — Hz fc1 PABS low-pass filter Cutoff frequency, filter option #1, 4-pole tSigDelay Signal delay (sinc filter to output delay, excluding the PABS LPF) [4] — — 128 μs tST_INIT PABS startup common mode verification test time [4] — — 20 ms tST_CMCONT PABS continuous common mode verification response time PABS error equivalent to 50 kPa [4] — — 4 s tST_Resp_1000_4 Self-test response time: self-test activation/deactivation to final value LPF = 1000 Hz, 4-pole [4] — — 2.016 ms tST_FP_Resp Fixed pattern response time: self-test activation/deactivation [4] — — 100 μs fPackage Package resonance frequency [4] 27.1 — — kHz Supply and support circuitry tVCC_POR VCC = VCCMIN to POR release [2] — — 1 ms tPOR_I2C/POR_SPI POR to first SPI command [4] 0.400 — 0.700 ms tPOR_DataValid POR to sensor data valid [4] — — 6 ms tRANGE_DataValid Reset recovery (all modes, excluding VCC voltage ramp time) DSP setting change to sensor data valid [2] — — 6 ms tSOFT_RESET_I2C Soft reset activation time, command complete to reset (no ACK follows) [4] — — 700 ns tSOFT_RESET_SPI Soft reset activation time, SS_B high to reset [4] — — 700 ns tCC_POR VCC undervoltage detection delay [4] — — 5 μs tUVOV_RCV Undervoltage/overvoltage recovery delay [4] — 100 — μs
[1] Parameter verified by characterization. [2] Parameter verified by functional evaluation. [4] Functionality verified by modeling, simulation and/or design verification.
12 Media compatibility—pressure sensors only
respective biasing and bypass components. cases, the bubble may bend the bond wires and result in a permanent shift. Figure 23. I2C application diagram of FXPS7165D4 Table 102. External component recommendations for I2C
Figure 24. SPI application diagram for FXPS7165D4 Table 103. External component recommendations for SPI
Figure 25. Package outline HQFN (SOT1573-1)
Figure 26. Package outline detail HQFN (SOT1573-1)
Figure 27. Package outline note HQFN (SOT1573-1)
NXP Semiconductors FXPS7165D4 Digital absolute pressure sensor, 60 to 165 kPa Product data sheet Rev. 5 — 15 July 2019
15 References
[1] Assembly guidelines for quad flat no-lead (HQFN) and small outline no-lead (SON) packages — NXP Application Note (AN) 1902, Rev. 8.0 - 6 February 2018, 51 pages, https://www.nxp.com/docs/en/application-note/AN1902.pdf [2] AEC documents on Automotive Electronics Council Component Technical Committee’s site: http://www.aecouncil.com/AECDocuments.html [3] I2C-Bus specification and user manual — NXP User Manual (UM) 10204, Rev. 6 - 4 April 2014, 64 pages, https://www.nxp.com/docs/en/user-guide/UM10204.pdf
Table 104. Revision history
- Section 7.7.10, Table 58: Revised bit 7 from "0" to "1" and bit 5 from "1" to "0" for factory default (read value).
- Section 7.7.12: Removed section titled "Self-test control bits."
- Section 7.7.12.3, Table 68: Revised entire table.
- Section 7.7.15, Equation 6: Revised denominator from "PABSSENSE × UserGain" to "PABSSENSE."
- Section 7.7.21: Added new second paragraph "The values of P_Max and P_Min obtained during a SPI or I2C register read might not always be the same value as the instantaneous pressure value obtained from the SNSDATA_x registers. The error will always be within 2 kPa of each other."
- Section 7.7.21, Table 79: Revised table title from "SNSDATA0_TIMEx - time stamp register (address 66h to 6Bh) bit allocation" to "P_Max and P_Min registers (address 6Ch to 6Fh) bit allocation." FXPS7165D4 v.4 20190507 Product data sheet - FXPS7165D4 v.3 FXPS7165D4 v.3 20190506 Preliminary data sheet - FXPS7165D4 v.2 FXPS7165D4 v.2 20190408 Preliminary data sheet - FXPS7165D4 v.1 FXPS7165D4 v.1 20190327 Preliminary data sheet - -
NXP Semiconductors FXPS7165D4 Digital absolute pressure sensor, 60 to 165 kPa Product data sheet Rev. 5 — 15 July 2019
17 Legal information
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Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
17.3 Disclaimers
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NXP Semiconductors FXPS7165D4 Digital absolute pressure sensor, 60 to 165 kPa Product data sheet Rev. 5 — 15 July 2019 to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — While NXP Semiconductors has implemented advanced security features, all products may be subject to unidentified vulnerabilities. Customers are responsible for the design and operation of their applications and products to reduce the effect of these vulnerabilities on customer’s applications and products, and NXP Semiconductors accepts no liability for any vulnerability that is discovered. Customers should implement appropriate design and operating safeguards to minimize the risks associated with their applications and products.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. NXP — is a trademark of NXP B.V.
NXP Semiconductors FXPS7165D4 Digital absolute pressure sensor, 60 to 165 kPa Product data sheet Rev. 5 — 15 July 2019 Tables Tab. 5. Self-test control bits for sense data fixed Tab. 8. Sensor data register read wrap-around Tab. 13. Register read command message bit field Tab. 15. Register read response message bit field Tab. 17. Register write command message bit field Tab. 19. Register write response message bit field Tab. 20. Sensor data request command message Tab. 21. Sensor data request command message bit Tab. 22. Sensor data request response message Tab. 23. Sensor data request response message bit Tab. 25. Reserved command message bit field Tab. 26. Reserved command response message Tab. 27. Reserved command response message bit Tab. 30. Basic status field for responses to register Tab. 32. User-accessible data — sensor specific Tab. 33. COUNT - rolling counter register (address Tab. 34. DEVSTAT - device status register (address Tab. 35. DEVSTAT - device status register (address Tab. 36. DEVSTAT1 - device status register (address Tab. 37. DEVSTAT1 - device status register (address Tab. 38. DEVSTAT2 - device status register (address Tab. 39. DEVSTAT2 - device status register (address Tab. 40. DEVSTAT3 - device status register (address Tab. 41. DEVSTAT3 - device status register (address Tab. 42. TEMPERATURE - temperature register Tab. 43. DEVLOCK_WR - lock register writes Tab. 44. DEVLOCK_WR - lock register writes Tab. 46. UF_REGION_W - UF region selection Tab. 47. UF_REGION_R - UF region selection Tab. 50. COMMTYPE - communication type register Tab. 51. COMMTYPE - communication type register Tab. 52. SOURCEID_0 - source identification Tab. 53. SOURCEID_1 - source identification Tab. 54. TIMING_CFG - communication timing Tab. 55. SPI_CFG Register (address 3Dh) bit Tab. 58. WHO_AM_I - device identification register Tab. 60. I2C_ADDRESS - I2C slave address register Tab. 61. DSP_CFG_U1 - DSP user configuration #1 Tab. 63. User range selection bits (USER_ Tab. 64. DSP_CFG_U4 - DSP user configuration #4 Tab. 65. DSP_CFG_U4 - DSP user configuration #4 Tab. 66. DSP_CFG_U5 - DSP user configuration #5 Tab. 67. DSP_CFG_U5 - DSP user configuration #5
NXP Semiconductors FXPS7165D4 Digital absolute pressure sensor, 60 to 165 kPa Product data sheet Rev. 5 — 15 July 2019 Tab. 69. INT_CFG - interrupt configuration register Tab. 70. INT_CFG - interrupt configuration register Tab. 71. P_INT_HI, P_INT_LO - interrupt window comparator threshold registers (address 46h Tab. 72. P_CAL_ZERO - pressure calibration Tab. 73. DSP_STAT - DSP specific status register Tab. 74. DSP_STAT - DSP specific status register Tab. 75. DEVSTAT_COPY - device status copy Tab. 76. SNSDATA0_L, SNSDATA0_H - sensor data #0 registers (addresses 62h, 63h) bit Tab. 77. SNSDATA1_L, SNSDATA1_H - sensor data #1 registers (address 64h, 65h) bit allocation ...47 Tab. 78. SNSDATA0_TIMEx - time stamp register Tab. 79. P_Max and P_Min registers (address 6Ch to Tab. 80. FRT - free running timer registers Tab. 82. IC TYPE REGISTER (ICTYPEID address Tab. 83. IC MANUFACTURER REVISION REGISTER (ICREVID address C1h) bit Tab. 84. IC MANUFACTURER IDENTIFICATION REGISTER (ICMFGID address C2h) bit Tab. 92. ASICWFR# Register (address CBh) bit Tab. 93. ASICWFR_X Register (address CCh) bit Tab. 94. ASICWFR_Y Register (address CDh) bit Tab. 95. ASICWLOT_L Register (address D0h) bit Tab. 96. ASICWLOT_H Register (address D1h) bit Tab. 102. External component recommendations for Tab. 103. External component recommendations for Figures Fig. 4. User-controlled PABS common mode self- Fig. 12. Temperature sensor signal chain block Fig. 13. Common mode error detection signal chain Fig. 17. I2C acknowledge and not acknowledge
NXP Semiconductors FXPS7165D4 Digital absolute pressure sensor, 60 to 165 kPa Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2019. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 July 2019 Document identifier: FXPS7165D4
7.7.17 DEVSTAT_COPY - device status copy
7.7.18 SNSDATA0_L, SNSDATA0_H - sensor data
7.7.19 SNSDATA1_L, SNSDATA1_H - sensor data
7.7.20 SNSDATA0_TIMEx - time stamp registers
7.7.21 P_MAX, P_MIN - maximum and minimum
absolute pressure value registers (address