Sensor

FXPS7140P7

NXP Semiconductors

DSI3 and PSI5 compatible absolute and relative pressure sensor Rev. 3.4 - 29 November 2023

Manufacturer: NXP Semiconductors

Document: 137 Pages / 1Mb

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FXPS71407 NXP | Alldatasheet

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Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 137

Technical content

Datasheet sections

1 General description
2 Features
3 Ordering information
3.1 Ordering options
4 Block diagram
5 Pinning information
5.1 Pinning
6 Functional description
6.1 User accessible data array
6.2 Register definitions
6.2.1 COUNT – rolling counter register (address
6.2.2 DEVSTATx – device status registers
6.2.3 COMMREV – communication protocol
6.2.4 TEMPERATURE – temperature register
6.2.5 DEVLOCK_WR – lock register writes
6.2.6 WRITE_OTP_EN – write OTP enable
6.2.7 BUSSW_CTRL – bus switch control
6.2.8 PSI5_TEST – PSI5 test register (address
6.2.9 UF_REGION_x – UF region selection
6.2.10 COMMTYPE – communication type register
6.2.11 PHYSADDR – physical address register
6.2.12 SOURCEID_x – source identification
6.2.13 TIMING_CFG – communication timing
6.2.14 CHIPTIME – chip time and bit time register
6.2.15 BDM_CFG – DSI3 background diagnostic
6.2.16 PSI5_CFG – PSI5 configuration register
6.2.17 PDCM_RSPSTx_x – DSI3 and PSI5 start
6.2.18 PDCM_CMD_B_x – DSI3 and PSI5
6.2.19 WHO_AM_I – who am I register (address
6.2.20 DSP_CFG_U1 – DSP user configuration #1
6.2.21 DSP_CFG_U3 – DSP user configuration #3
6.2.22 DSP_CFG_U4 – DSP user configuration #4
6.2.23 DSP_CFG_U5 – DSP user configuration #5
6.2.24 INT_CFG – interrupt configuration register
6.2.25 P_CAL_ZERO_x – pressure calibration
6.2.26 DSP_STAT – DSP-specific status register
6.2.27 DEVSTAT_COPY – device status copy
6.2.28 SNSDATA0_L, SNSDATA0_H – sensor
6.2.29 SNSDATA1_L, SNSDATA1_H – sensor
6.2.30 SNSDATA0_TIMEx – sensor data
6.2.31 P_MAX, P_MIN – minimum and maximum
6.2.32 FRTx – free-running timer registers
6.2.33 ICTYPEID – IC type register (address $C0)
6.2.34 ICREVID – IC manufacturer revision
6.2.35 ICMFGID – IC manufacturer identification
6.2.36 PNx – part number registers (address $C4,
6.2.37 SNx – device serial number registers
6.2.38 ASIC wafer ID registers (address $CB to
6.2.39 USERDATA_0 to USERDATA_E – user
6.2.39.1 PSI5 initialization phase 2 data
6.2.40 USERDATA_10 to USERDATA_1E – user
6.2.41 CRC_UF2, CRC_F_A to CRC_F_F – lock
6.2.42 Reserved registers
6.2.43 Invalid register addresses
6.3 OTP and read/write register array CRC
6.3.1 NXP OTP registers
6.3.2 User OTP only registers
6.3.3 OTP modifiable registers
6.4 Voltage regulators
6.4.1 VBUF regulator capacitor and capacitor
6.4.2 BUS_I, VBUF, VREG, VREGA,
6.5 Internal oscillator

DSI3 and PSI5 compatible absolute and relative pressure sensor Rev. 3.4 — 29 November 2023 Product data sheet

1 General description

FXPS71407 is a DSI3 and PSI5 compatible pressure sensor.

2 Features

Pressure range options: – 40 kPa to 140 kPa absolute pressure range – –40 °C to 125 °C operating temperature range
DSI3 compatible – Discovery mode support for physical location identification – Command and response mode support for device configuration – Periodic data collection mode support for sensor data transfers – Background diagnostics mode support during periodic data collection mode
PSI5 version 2.1 compatible – Compatible modes: P10P-500/3L, P10P-500/4H, A10P-228/1L, P10CRC-xxx/xx, and many others – Programmable time slots with 1 µs resolution – Selectable baud rate: 125 kBd or 189 kBd – 10-bit data length for relative pressure – Selectable error detection: even parity, or 3-bit CRC – Two-wire programming mode
Pressure transducer and DSP – Redundant pressure transducers – Capacitance to voltage converter with anti-aliasing filter – Sigma delta ADC plus sinc filter – Selectable 370 Hz, 2-pole, or 400 Hz, 3-pole and 4-pole 800 Hz, 1000 Hz low-pass filter for absolute pressure – 0.16 Hz, 1-pole LPF for P0 value – 10-bit ΔP/P0 output
Pb-free 16-pin QFN 4 mm x 4 mm x 1.98 mm package

3 Ordering information

Table 1. Ordering information

3.1 Ordering options

Table 2. Ordering options [1] To order parts in tape and reel, add the T1 suffix to the part number. [4] Refer to Table 105 for part number to protocol register values. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

4 Block diagram

5 Pinning information

5.1 Pinning

Figure 2. Pin configuration for HQFN16 NXP recommends that this pin be unterminated. Optionally, this pin can be connected to BUS_I/VCC. mode, it is recommended that this pin be unterminated. Optionally, this pin can be tied to VSS. the daisy chain. An external pulldown resistor is required on the gate of the N-channel FET as shown in Figure 61. If unused, or in DSI3 mode, NXP recommends that this pin be unterminated. Optionally, this pin can be tied to VSS. BUSRTN/VSS 4, 15 Supply return These pins are the supply return nodes. TEST6 12 Test pin It is recommended that this pin be unterminated. Optionally, this pin can be tied to VSS. NC 6, 7, 14 No connect These pins are not internally connected and can be left unconnected in the application. TEST2 8 Test pin In DSI3 or PSI5 mode, it is recommended that this pin be unterminated. Optionally, this pin can be connected to VBUF. TEST3 9 Test pin In DSI3 or PSI5 mode, it is recommended that this pin be unterminated. Optionally, this pin can be connected to VSS. TEST4 10 Test pin In DSI3 or PSI5 mode, it is recommended that this pin be unterminated. Optionally, this pin can be connected to VSS. TEST5 11 Test pin In DSI3 or PSI5 mode, this pin must be left unconnected. pin and BUSRTN as shown in Section 11 "Application information". This pin also modulates the response current for PSI5 communication and provides the supply for OTP programming. Note: BUS_I and VCC are the same. PAD 17 Die attach pad This pin is the die attach flag, and must be connected to VSS. See Section 12.1 "Footprint" for die attach pad connection details. Table 3. Pin description FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

6 Functional description

6.1 User accessible data array

OTP blocks incorporate independent data verification. Table 4. User accessible data array FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

6.2 Register definitions

6.2.1 COUNT – rolling counter register (address $00)

value in the register increases by one count every 100 µs and the counter rolls over every 25.6 ms. This register is readable in DSI3 mode or PSI5 diagnostic mode. Table 5. COUNT – rolling count register – (address $00) bit allocation

6.2.2 DEVSTATx – device status registers (address $01-$04)

The device status registers are read-only registers which contain device status information. These registers are readable in DSI3 mode or PSI5 diagnostic mode. Table 6. DEVSTAT – device status register – (address $01) bit allocation FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

is cleared based on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in Table 7. 0 No response until the supply monitor timer expires. supply monitor timer expires. the status field if and only if the timer has reached zero. timer reaches zero and normal transmissions resume. timer reaches zero and normal transmissions resume. Table 7. SUPPLY_ERR – supply error flag through any communication interface or on a data transmission that includes the error in the status field.

0 Normal operation

1 Device reset occurred

Table 8. DEVRES – device reset communication interfaces (tPOR_DataValid).

1 Device initialization in process

Table 9. DEVINIT – device initialization Table 10. DEVSTAT 1– device status register – (address $02) bit allocation If no error is present, the register contents are cleared when read twice. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

0 No error detected

1 VBUF voltage low

Table 11. VBUFUV_ERR – VBUF undervoltage error

1 BUS_IN voltage low

Table 12. BUSINUV_ERR – BUS IN undervoltage error

1 VBUF voltage high

Table 13. VBUFOV_ERR – VBUF overvoltage error DEVLOCK_WR register as shown in Table 7.

1 Internal analog regulator voltage out of range

Table 14. INTREGA_ERR – internal analog regulator voltage out of range error DEVLOCK_WR register as shown in Table 7. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

1 Internal digital regulator voltage out of range

Table 15. INTREG_ERR – internal digital regulator voltage out of range error DEVLOCK_WR register as shown in Table 7.

1 Internal OTP regulator voltage out of range

Table 16. INTREGF_ERR – internal OTP regulator voltage out of range error

1 Error detected in the continuity of the monitor circuit

Table 17. CONT_ERR – continuity monitor error Table 18. DEVSTAT2 – device status register – (address $03) bit allocation

1 Error detected in the factory OTP array

1 Error detected in the user OTP array

Table 20. U_OTP_ERR – user OTP array error

1 Error detected in the user read/write array

Table 21. U_RW_ERR – user read/write array error U_W_ACTIVE bit is automatically cleared once the write to OTP is complete.

0 No OTP write in process

1 OTP write in process

Table 22. U_W_ACTIVE – user OTP write in process status bit

1 Overtemperature or undertemperature error condition detected

Table 23. TEMP0_ERR – temperature error Table 24. DEVSTAT3 – device status register – (address $04) bit allocation FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 25. OSCTRAIN_ERR – oscillator training error

6.2.3 COMMREV – communication protocol revision register (address $05)

communication protocol used. This register is readable in DSI3 mode or PSI5 diagnostic mode. Table 26. COMMREV – communication protocol revision register – (address $05) bit allocation

6.2.4 TEMPERATURE – temperature register ($0E)

This includes the performance of the temperature register values. This register is readable in DSI3 mode or PSI5 diagnostic mode. Table 27. TEMPERATURE – temperature register – (address $0E) bit allocation

6.2.5 DEVLOCK_WR – lock register writes register (address $10)

This register is readable and writable in DSI3 mode or PSI5 diagnostic mode. Table 28. DEVLOCK_WR – lock register writes register – (address $10) bit allocation FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

DEVLOCK_WR register. Once set, the ENDINIT bit can only be cleared by a device reset.

An error detection is enabled for all user writable registers. The error detection code is continuously calculated on the user writable registers and verified against a previously calculated error detection code.
The P0 filter is forced to its final stage.
Self-test is disabled and inhibited.
Register writes are inhibited with the exception of the RESET[1:0] bits in the DEVLOCK_WR register. In DSI3 mode, when the ENDINIT bit is set, the device is forced to PDCM according to the device settings and no longer responds to CRM commands. In all PSI5 modes, the ENDINIT bit is automatically set when the device exits initialization phase 3. SUP_ERR_DIS – supply error reporting disable bit The supply error disable bit allows the user to disable reporting of the supply errors in the DSI3 PDCM fields. See Table 7. RESET[1:0] – reset control bits In DSI3 mode or PSI5 mode, a series of three consecutive register write operations to the reset control bits will result in a device reset. To reset the device, the following register write operations must be performed in consecutive commands and in the order shown in Table 29 or the device will not be reset. Register write to DEVLOCK_WR RES_1 RES_0 Effect Register Write 1 0 0 No effect Register Write 2 1 1 No effect Register Write 3 0 1 Device RESET

Table 29. Register write operations

6.2.6 WRITE_OTP_EN – write OTP enable register (address $11)

the user read/write array error detection. This register is readable and writable in DSI3 mode or PSI5 diagnostic mode. Table 30. WRITE_OTP_EN – write OTP enable register – (address $11) bit allocation OTP will be written as shown in Table 31. Table 31. Writes for OTP registers FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

including COMMTYPE and excluding PHYSADDR. excluding COMMTYPE and including PHYSADDR. excluding COMMTYPE and excluding PHYSADDR. Table 31. Writes for OTP registers...continued support these two user modes, the EX_PADDR bit is used as described in Table 31. register write commands, but no new values can be written to the OTP.

Read the appropriate CRC_UFx register and confirm the LOCK_Uxx bit is not set.
Write the desired values to the user array registers for only the region to be written using the procedures in

Section 6.2.9 "UF_REGION_x – UF region selection registers (address $14, $15)".

Execute a write to the WRITE_OTP_EN register with the appropriate bits set for the desired region to

UOTP_WR_INIT bit will remain set.

Delay tOTP_WRITE_MAX to allow the device to complete the writes to OTP.
Verify that the OTP write has successfully completed by reading back all of the OTP registers using register
Repeat steps 1 through 4 for all regions to be programmed.
Read the CRC_UF2 register and confirm the LOCK_UF2 bit is not set.
Write the desired values to the user array registers.
Execute a write to the WRITE_OTP_EN register with region 2 selected and the EX_COMMTYPE and

Delay tOTP_WRITE_MAX to allow the device to complete the writes to OTP.
Verify that the OTP write successfully completed by reading back all of the OTP registers using register read

6.2.7 BUSSW_CTRL – bus switch control register (address $12)

switch output driver. This register is included in the user read/write array error detection. This register is readable and writable in DSI3 mode or PSI5 diagnostic mode. Table 32. BUSSW_CTRL – bus switch control register – (address $12) bit allocation The BUSSW_CTRL bit controls the state of the BUSSW_L and BUSSW_H pins. Table 33. State of BUSSW_L and BUSSW_H pins Note: In DSI3 and PSI5 DPM modes, the bus switch is activated upon receipt of the register write command.

6.2.8 PSI5_TEST – PSI5 test register (address $13)

the user read/write array error detection. This register is readable and writable in DSI3 mode, or PSI5 diagnostic mode. Table 34. PSI5_TEST – PSI5 test register – (address $13) bit allocation response transmission to allow for the PSI5 transceiver to be tested in other modes. When the PSI5_TEST bit is set, the device and system proceed through following process.

The device switches the BUS_I transceiver to PSI5 mode.
The system must hold the BUS_I node constant for 2 ms minimum to allow the BUS_I command receiver to capture the average voltage. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

The system must transmit a sync pulse meeting the specifications in Section 9 "Static characteristics".
The device will transmit a response to the sync pulse with the following configuration: – The sync pulse will be pulled down as configured by the SYNC_PD bit in the PSI5_CFG register. – The response will start in the time slot selected in the PDCM_RSPST0 register. – The response bit time will be as configured in the CHIPTIME register. – The response current will be as configured by the PSI5_ILOW bit in the PSI5_CFG register. – Two start bits will be transmitted as specified in Section 11.3.3.2 "PSI5 data transmission". – 10 bits of data equal to 2AAh will be transmitted. – Error checking bits will be transmitted as configured by the P_CRC bit in the PSI5_CFG register.
Once the transmission is complete, the PSI5_TEST bit is cleared, and the device returns to the communication mode as defined in the COMMTYPE register. If the bit is set from DSI3 mode, this process occurs once the device has replied to the write message, regardless of whether the reply attempted was successful. If PSI5 mode is enabled in the COMMTYPE register, this bit has no impact on device operation or performance.

6.2.9 UF_REGION_x – UF region selection registers (address $14, $15)

active register is a read-only register that contains the status bits for the UF0 and UF1 regions to be accessed. This register is included in the user read/write array error detection. Table 35. UF_REGION_W – UF region selection register – (address $14) bit allocation UF_REGION_R register is readable in DSI3 mode or PSI5 diagnostic mode. Table 36. UF_REGION_R – UF region selection register – (address $15) bit allocation

Write the desired address range to be read to the REGION_LOAD[3:0] bits in the UF_REGION_W register

using one of the communication interfaces available via the COMMTYPE register. Table 37. Communication interfaces available via the COMMTYPE register FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 37. Communication interfaces available via the COMMTYPE register...continued

Delay a minimum of tSSN_UF01.
Optional: Execute a register read of the UF_REGION_R register and confirm the REGION_ACTIVE[3:0] bits

match the values written to the REGION_LOAD[3:0] bits in the UF_REGION_W register. Table 38. Optional communication interfaces available via the COMMTYPE register

Execute a register read of the desired registers from the UF0, UF1, or F register section. Complete all desired

Repeat steps 1 through 4 for the next desired UF region to read.

The user must take care to ensure that the desired registers are addressed. For example, if the REGION_LOAD bits are set to Ah and the user executes a read of address $C2, the contents of registers $A2 will be transmitted. No error detection is included other than a read of the REGION_ACTIVE bits.
For COMMTYPE options with multiple protocol options (COMMTYPE = '000 or '001'), no error detection is included other than a read of the REGION_ACTIVE bits. The user must take care to ensure that the REGION_LOAD, bits are not inadvertently changed by an alternative protocol while executing register reads.

6.2.10 COMMTYPE – communication type register (address $16)

This register is readable and writable in DSI3 mode or PSI5 diagnostic mode. Table 39. COMMTYPE – communication type register – (address $16) bit allocation the device as shown in Table 40. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 40. Available protocols [1] Refer to Section 11.2 "DSI3 protocol". [2] Refer to Section 11.3 "PSI5 protocol". to OTP, will not take effect until a device reset to prevent from disabling a necessary communication method. Table 41 describes how communication mode register changes are handled. Table 41. Communication mode register changes

In DSI3 mode (COMMTYPE = 0) and PSI5 mode (COMMTYPE = 1), registers accesses by protocol are completed in the order received. Care must be taken to prevent from incorrect addressing of the F, UF0 and UF1 registers.
If the COMMTYPE register is preprogrammed in OTP to a specific communication type, the user must prevent writes to this register when writing the UF2 register to OTP. If a preprogrammed COMMTYPE register is overwritten and then written to OTP, the UF2 CRC verification will fail.

6.2.11 PHYSADDR – physical address register (address $18)

slave for use in DSI3. This register is included in the read/write array error detection. during command and response mode. value will always be reset to the OTP array value after a reset. Table 42. PHYSADDR – physical address register – (address $18) bit allocation

6.2.12 SOURCEID_x – source identification registers (address $1A, $1B)

These registers are readable and writable in DSI3 mode or PSI5 diagnostic mode. Table 43. SOURCEID_0 – source identification register – (address $1A) bit allocation Table 44. SOURCEID_1 – source identification register – (address $1B) bit allocation The SIDx_EN bits enable the data source for the associated source identification. Section 11.2.4.2 "DSI3 periodic data collection mode response transmission" for PDCM response format details. Table 45. PDCM field sizes Section 11.3.3.2 "PSI5 data transmission" for PSI5 response format details. Table 46. PSI5 response format In PSI5 mode, the SOURCEID_x register values control data transmissions as shown Table 47. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

0 NA NASOURCEID_0

0 NA NASOURCEID_1

Table 47. SOURCEID_x register values [1] See Section 6.2.17 "PDCM_RSPSTx_x – DSI3 and PSI5 start time registers (address $26 to $29)". [2] See Section 6.2.21 "DSP_CFG_U3 – DSP user configuration #3 register (address $42)".

6.2.13 TIMING_CFG – communication timing register (address $22)

This register is readable and writable in DSI3 mode or PSI5 diagnostic mode. Table 48. TIMING_CFG – communication timing register – (address $22) bit allocation the CK_CAL_EN bit is set in the TIMING_CFG register. Table 49. Data collection mode periods for oscillator training met. See Section 6.5.1 "Oscillator training" for details regarding oscillator training. Section 6.5.1 "Oscillator training" for details regarding oscillator training. In PSI5 asynchronous mode, oscillator training is not applicable. In PSI5 diagnostic and programming mode, oscillator training is not applicable. In PSI5 daisy chain command phase, oscillator training is not applicable. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

that enable multiple protocols as shown in Table 50. Table 50. Protocol to use for oscillator training described in Table 52. See Section 6.5.1 "Oscillator training" for details regarding oscillator training. Table 51. Command and response mode period Section 6.5.1 "Oscillator training" for details regarding oscillator training. 0 0 The oscillator value is maintained at the last trained value prior to clearing the CK_CAL_RST bit. 1 x Oscillator is trained as specified in Section 6.5.1 "Oscillator training". Table 52. CK_CAL_EN and CK_CAL_RST oscillator training

6.2.14 CHIPTIME – chip time and bit time register (address $23)

configuration information. This register is included in the read/write array error detection. This register is readable and writable in PSI5 diagnostic mode. Table 53. CHIPTIME – chip time and bit time register – (address $23) bit allocation FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

accommodate synchronized sampling or simultaneous sampling.

0 Synchronous sampling mode (latency relative to time slot)

1 Simultaneous sampling mode (latency relative to sync pulse)

Table 54. SS_EN data latency methods In PSI5 mode, the CHIPTIME bits set the bit time for the PSI5 response data as described in Table 55. Table 55. Bit time for the PSI5 response data

6.2.15 BDM_CFG – DSI3 background diagnostic mode configuration register (address $24)

diagnostic mode" for details regarding background diagnostic mode. This register is readable and writable in DSI3 mode or PSI5 diagnostic mode. Table 56. BDM_CFG – DSI3 background diagnostic mode configuration register – (address $24) bit and response chips to be sent per periodic data collection mode sampling period. Table 57. Background diagnostic command bits and response chips FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 57. Background diagnostic command bits and response chips...continued The background diagnostic mode enable bit enables background diagnostic mode as described in Table 58.

0 Disabled

1 Enabled

Table 58. Background diagnostic mode enabled In PSI5 mode, the BDM_EN bit is readable and writable, but has no impact on device operation or performance.

6.2.16 PSI5_CFG – PSI5 configuration register (address $25)

information. This register is included in the read/write array error detection. This register is readable and writable in DSI3 mode or PSI5 diagnostic mode. Table 59. PSI5_CFG – PSI5 configuration register – (address $25) bit allocation pulse is detected. See Section 6.2.17 for more information regarding the sync pulse pulldown.

1 Enabled for all PSI5 operating modes

Table 60. Sync pulse pulldown enable bit select In PSI5 mode, the transmission mode selection bits select the PSI5 transmission mode as shown in Table 61. Table 61. Transmission mode selection bits select Section 9 "Static characteristics" as shown in Table 62. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

0 Normal response current

1 Low response current

Table 62. PSI5 low response current pressure PSI5 data range as shown in Table 63. Table 63. PSI5 relative pressure PSI5 data range information as shown in Table 64. Table 64. PSI5 error message information time registers (address $26 to $29)" for details regarding response message error detection.

0 Parity

1 CRC

Table 65. PSI5 response message error detection In DSI3 mode, the P_CRC bit is readable and writable, but has no impact on device operation or performance. D33 through D48 of PSI5 initialization phase 2 as shown in Table 66.

0 D33 through D48 are not transmitted

Table 66. D33 through D48 of PSI5 initialization phase 2 Section 6.2.17 only if the DAISY_CHAIN bit is not set. In DSI3 mode, the ASYNC bit is readable and writable, but has no impact on device operation or performance. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

6.2.17 PDCM_RSPSTx_x – DSI3 and PSI5 start time registers (address $26 to $29)

These registers are readable and writable in DSI3 mode or PSI5 diagnostic mode. Table 67. PDCM_RSPSTx_x – DSI3 and PSI5 start time registers – (address $26 to $29) bit allocation response start time for the associated data and SOURCEID. The value is stored in 1.0 µs increments. Table 68. Periodic data collection mode response start time for the associated data and SOURCEID which cause data contention in the system. Table 69. Default states for SOURCEID_x, SNSDATAxm, PCDM_REPSTx PSI5 Version 1.3 specification, or time slots which will cause data contention.

1 SOURCEID_0 SNSDATA0 Asynchronous mode tASYNC

SOURCEID_1 SNSDATA1 PDCM_RSPST1[12:0] Transmit data with a start time of 20 µs. Table 70. PSI5 data transmission start times responds to for each source ID as shown in Table 71. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 71. BRC_RSP[1:0] response responses when BDM commands are received.

If the last command prior to a BDM command is a BRC0, a device programmed to respond only to BRC0 commands will not respond to the first BDM command and will then respond to every other BDM command until the next BRC command is received.
If the last command prior to a BDM command is a BRC0, a device programmed to respond only to BRC1 commands will respond to the first BDM command, and will then response to every other BDM command until the next BRC command is received.
If the last command prior to a BDM command is a BRC1, a device programmed to respond only to BRC0 commands will respond to the first BDM command, and will then response to every other BDM command until the next BRC command is received.
If the last command prior to a BDM command is a BRC1, a device programmed to respond only to BRC1 commands will not respond to the first BDM command and will then respond to every other BDM command until the next BRC command is received. In PSI5 mode, the BRC_RSP[1:0] bits are readable and writable, but have no impact on device operation or performance.

6.2.18 PDCM_CMD_B_x – DSI3 and PSI5 command blocking time registers (address $38, $39)

These registers are readable and writable in DSI3 mode or PSI5 diagnostic mode. Table 72. PDCM_CMD_B_x – DSI3 and PSI55 command blocking time registers – (address $38, $39) bit response transmissions are occurring to provide the most stable BUS_I voltage. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 73. DSI3 mode sync pulse blocking time sync pulse receiver and command blocking. decoding in the system and to ensure proper sampling of the PSI5 voltage. Table 74. PSI5 mode sync pulse blocking time

6.2.19 WHO_AM_I – who am I register (address $3E)

The Who_Am_I register is a user programmed read/write register which contains the unique product identifier. The register is readable in all modes. This register is included in the read/write array error detection. This register is readable and writable in DSI3 mode or PSI5 diagnostic mode. Table 75. WHO_AM_I – who am I register – (address $3E) bit allocation command. For all other register values, the actual register value is transmitted in response to a read command. Table 76. Response to a register read command

6.2.20 DSP_CFG_U1 – DSP user configuration #1 register (address $40)

configuration information. This register is included in the read/write array error detection. SNSDATA_x registers and sensor data requests should be prevented during this time. This register is readable and writable in DSI3 mode or PSI5 diagnostic mode. Table 77. DSP_CFG_U1 – DSP user configuration #1 register – (address $40) bit allocation FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 77. DSP_CFG_U1 – DSP user configuration #1 register – (address $40) bit allocation...continued details regarding the low-pass filter. Table 78. LPF[3:0] – low-pass filter selection bits

6.2.21 DSP_CFG_U3 – DSP user configuration #3 register (address $42)

configuration information. This register is included in the read/write array error detection. SNSDATA_x registers and sensor data requests should be prevented during this time. This register is readable and writable in DSI3 mode or PSI5 diagnostic mode. Table 79. DSP_CFG_U3 – DSP user configuration #3 register – (address $42) bit allocation Table 80. DSP data type 0 selection bits FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 81. DSP data type 1 selection bits Note: Interpolation is not included on the DATATYPE1 output.

6.2.22 DSP_CFG_U4 – DSP user configuration #4 register (address $43)

configuration information. This register is included in the read/write array error detection. This register is readable and writable in DSI3 mode or PSI5 diagnostic mode. Table 82. DSP_CFG_U4 – DSP user configuration #4 register – (address $43) bit allocation phase will be reset to phase 0. Table 83. P0 filter reset bit

0 Enabled

1 Bypassed

Table 84. P0_RLD – P0 filter rate limiting bypass bit output pin is high impedance. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

0 Open drain, active high with pulldown current

1 Open drain, active low with pullup current

Table 85. INT_OUT – interrupt pin configuration

6.2.23 DSP_CFG_U5 – DSP user configuration #5 register (address $44)

configuration information. This register is included in the read/write array error detection. This register is readable and writable in DSI3 mode or PSI5 diagnostic mode. Table 86. DSP_CFG_U5 – DSP user configuration #5 register – (address $44) bit allocation Table 87. The self-test control bits are not included in the read/write array error detection. Table 87. Self-test control bits

6.2.24 INT_CFG – interrupt configuration register (address $45)

The interrupt configuration register contains configuration information for the interrupt output. Table 88. INT_CFG – interrupt configuration register – (address $45) bit allocation FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 88. INT_CFG – interrupt configuration register – (address $45) bit allocation...continued derived from the internal oscillator, so the tolerance on this oscillator applies. Table 89. Interrupt output pulse stretch condition does not exist after the most recent evaluated sample. condition exists after the most recent evaluated sample. thresholds, a window comparator can be programmed for activation either within or outside a window.

0 Interrupt activated if the value is outside the window

1 Interrupt activated if the value is inside the window

Table 90. Interrupt window comparator polarity

6.2.25 P_CAL_ZERO_x – pressure calibration registers (address $4C, $4D)

Table 91. P_CAL_ZERO_x – pressure calibration registers – (address $4C) bit allocation FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 91. P_CAL_ZERO_x – pressure calibration registers – (address $4C) bit allocation...continued pressure signal value as shown in Equation 1. Equation 1 applies to the values in the 16-bit SNSDATA registers. See Section 6.6.4.7 "Output scaling equations" for the default transfer functions for each data output type. output range or a railed output.

6.2.26 DSP_STAT – DSP-specific status register (address $60)

The DSP status register is a read-only register which contains sensor data-specific status information. This register is readable in DSI3 mode or PSI5 diagnostic mode. Table 92. DSP_STAT – DSP-specific status register – (address $60) bit allocation ST_CTRL[0] = 1) or the PSI5 internal self-test procedure has started. 0 An analog or digital self-test has been activated since the last reset. Table 93. Self-test incomplete FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

self-test active bit is cleared when no self-test mode is active. "Common mode error detection signal chain" for details regarding the common mode error detection. bit can only be cleared by a device reset.

6.2.27 DEVSTAT_COPY – device status copy register (address $61)

for details regarding the DEVSTAT register contents. the same effect as a read of the DEVSTAT register. Table 94. DEVSTAT_COPY – device status copy register – (address $61) bit allocation

6.2.28 SNSDATA0_L, SNSDATA0_H – sensor data #0 registers (address $62, $63)

equations" for details regarding the 16-bit sensor data. These registers are readable in DSI3 mode or PSI5 diagnostic mode. Table 95. SNSDATA0_L, SNSDATA0_H – sensor data #0 registers – (address $62, $63) bit allocation

6.2.29 SNSDATA1_L, SNSDATA1_H – sensor data #1 registers (address $64, $65)

equations" for details regarding the 16-bit sensor data. These registers are readable in DSI3 mode or PSI5 diagnostic mode. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 96. SNSDATA0_L, SNSDATA0_H – sensor data #0 registers – (address $62, $63) bit allocation

6.2.30 SNSDATA0_TIMEx – sensor data 0 timestamp (address $66 to $69, $6A, $6B)

The sensor data 0 timestamp registers are read-only registers which contain a 48-bit timestamp. These registers are readable in DSI3 mode or PSI5 diagnostic mode. Table 97. SNSDATA0_TIMEx – sensor data 0 timestamp – (address $66 to $69, $6A, $6B) bit allocation

6.2.31 P_MAX, P_MIN – minimum and maximum absolute pressure value registers (address

DATATYPE1[1:0], or ST_CTRL[3:0]. These registers are readable in DSI3 mode or PSI5 diagnostic mode. Table 98. P_MAX_x – maximum absolute pressure value register – (address $6C, $6D) bit allocation Table 99. P_MIN_x – maximum absolute pressure value register – (address $6E, $6F) bit allocation FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 99. P_MIN_x – maximum absolute pressure value register – (address $6E, $6F) bit allocation...continued

6.2.32 FRTx – free-running timer registers (address $78, $79, $7A to $7D)

running timer is clocked by the main oscillator frequency and increments every 100 ns. These registers are readable in DSI3 mode or PSI5 diagnostic mode. Table 100. FRTx – free-running timer registers (address $78, $79, $7A to $7D) bit allocation

6.2.33 ICTYPEID – IC type register (address $C0)

The IC type register is a factory programmable OTP register which contains the IC type as defined in Table 101. This register is included in the factory programmed OTP array error detection. Table 101. ICTYPEID – IC type register – (address $C0) bit allocation

6.2.34 ICREVID – IC manufacturer revision register (address $C1)

the factory programmed OTP array error detection. Table 102. ICREVID – IC manufacturer revision register – (address $C1) bit allocation FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

6.2.35 ICMFGID – IC manufacturer identification register (address $C2)

IC manufacturer. This register is included in the factory programmed OTP array error detection. Table 103. ICMFGID – IC manufacturer identification register – (address $C2) bit allocation

6.2.36 PNx – part number registers (address $C4, $C5)

device part number. These registers are included in the factory programmed OTP array error detection. read process for these registers. Table 104. PNx – part number registers – (address $C4, $C5) bit allocation Table 105. Part number registers protocol

6.2.37 SNx – device serial number registers (address $C6 to $C9, $CA)

of the device. Serial numbers begin at 1 for all produced devices in each lot and are sequentially assigned. read process for these registers. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 106. SNx – device serial number registers – (address $C6 to $C9, $CA) bit allocation

6.2.38 ASIC wafer ID registers (address $CB to $CD, $D0, $D1)

read process for these registers. Table 107. ASICWFR# – ASIC wafer ID register – (address $CB) bit allocation Table 108. ASICWFR_x – ASIC wafer x, y coordinates ID registers – (address $CC, $CD) bit allocation Table 109. ASICWLOT_x – ASIC wafer lot ID registers – (address $D0, $D1) bit allocation

6.2.39 USERDATA_0 to USERDATA_E – user data registers (address $E0 to $E9, $EA to $EE)

registers are included in the user programmed OTP array error detection. read process for these registers. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 110. USERDATA_X – user data registers (address $E0 to $E9, $EA to $EE) bit allocation

6.2.39.1 PSI5 initialization phase 2 data transmissions of user data

initialization phase 2 transmissions. Table 111. Phase 2 USERDATA_X – user data registers (address $E0 to $E9, $EA to $EE) bit allocation

6.2.40 USERDATA_10 to USERDATA_1E – user data registers (address $F0 to $F9, $FA to $FE)

These registers are readable and writable in DSI3 mode, or PSI5 diagnostic mode when ENDINIT is not set. register read process for these registers. Table 112. USERDATA_10 to USERDATA_1E – user data registers (address $F0 to $F9, $FA to $FE) – bit

6.2.41 CRC_UF2, CRC_F_A to CRC_F_F – lock and CRC registers (address $5F, $AF to $FF)

identifier, and the block OTP array CRC use for error detection. Table 113. CRC_UF2, CRC_F_A to CRC_F_F – lock and CRC registers – (address $5F, $AF to $FF) bit FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 114. Register block before and after programming

6.2.42 Reserved registers

A register read command to a reserved register or a register with reserved bits will result in a valid response. The data for reserved bits may be 0 or 1. normal device operation and performance.

6.2.43 Invalid register addresses

array" will result in a valid response. The data for the registers will be 00h. data array" will not execute, but will result in a valid response. The data for the registers will be 00h. the registers will be the current contents of the register.

6.3 OTP and read/write register array CRC verification

6.3.1 NXP OTP registers

independent 4-bit CRC for each 16 byte block. Table 115. Internal OTP registers

6.3.2 User OTP only registers

Table 116. User OTP only registers

6.3.3 OTP modifiable registers

The following registers are user read/write registers as well as OTP registers with writable mirror registers. from right to left (MSB first) and from top to bottom (lowest address first) in the register map. Table 117. Registers verified by the OTP CRC Table 118. Registers verified by the ENDINIT calculated CRC

6.4 Voltage regulators

filter capacitor is required for VBUF, as shown in Section 11.5 "DSI3 switch connected daisy chain mode ". undervoltage detection thresholds. A reference generator provides a reference voltage for the ΣΔ converter. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Figure 3. Voltage regulation and monitoring

6.4.1 VBUF regulator capacitor and capacitor monitor

Figure 6. VBUF capacitor monitor timing, PSI5 asynchronous mode

6.4.2 BUS_I, VBUF, VREG, VREGA, undervoltage monitor

DSI3 – If any supply falls below the specified threshold during a command transmission in command and response mode, the command is ignored, and no DSI3 response transmission occurs. Once the supply returns above the threshold, the device will resume decoding commands as specified in Section 6.2.2 "DEVSTATx – device status registers (address $01-$04)". – If any supply falls below the specified threshold during a response transmission in command and response mode, the response is terminated. No attempt is made to resend the response. Once the supply returns above the threshold, the device will resume decoding commands as specified in Section 6.2.2 "DEVSTATx – device status registers (address $01-$04)". – If any supply falls below the specified threshold during a command transmission in periodic data collection mode, the command is ignored and no periodic response occurs during that period. Once the supply returns above the threshold, the device will resume periodic transmissions in response to commands as specified in Section 6.2.2 "DEVSTATx – device status registers (address $01-$04)". Any partially received background diagnostic mode command is flushed and the device will begin decoding a new background diagnostic mode command. – If any supply falls below the specified threshold during a periodic response transmission in periodic data collection mode, the response is terminated. No attempt is made to resend the response. Once the supply returns above the threshold, the device will resume periodic transmissions in response to commands as specified in Section 6.2.2 "DEVSTATx – device status registers (address $01-$04)". Any partially received background diagnostic mode command is flushed and the device will begin decoding a new background diagnostic mode command. – If any supply falls below the specified threshold during a background diagnostic mode response transmission in periodic data collection mode, the response is terminated. No attempt is made to resend the response. Once the supply returns above the threshold, the device will resume periodic transmissions in response to commands as specified in Section 6.2.2 "DEVSTATx – device status registers (address $01- FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

decoding a new background diagnostic mode command.

PSI5 – If any supply falls below the specified threshold, PSI5 transmissions are terminated for the present response. Once the supply returns above the threshold, the device will resume responses as specified in Section 6.2.2 "DEVSTATx – device status registers (address $01-$04)". See Figure 7 for an example of a supply line interruption during a DSI3 or PSI5 response. aaa-023415 response terminated time IBUS_I POR BUS_I micro-cut occurs BUS_I undervoltage detected BUS_I VBUF VREG VREGA

Figure 7. BUS_I micro-cut response (DSI3 or PSI5)

6.5 Internal oscillator

The device includes a factory trimmed oscillator as specified in Section 10 "Dynamic characteristics".

6.5.1 Oscillator training

feature can be enabled for DSI3 and PSI5 modes.

6.5.1.1 DSI3 oscillator training

CK_CAL_EN bit is set and the command and response mode period is between 500 µs and 4 ms, inclusive.

The device counts the number of oscillator cycles in nCRM_PER_4ms_TYP periods (nOSC_4ms).
nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training window (OscTrainWIN)

command ending the nCRM_PER_OSC calculation. reset to its untrained value with the untrained tolerance specified in Section 10 "Dynamic characteristics". Figure 8. Command and response mode oscillator training timing diagram In periodic data collection mode, oscillator training is completed over 4 ms periods if the CK_CAL_EN bit is set.

The device counts the number of oscillator cycles in nPDCM_PER_4ms_TYP periods (nOSC_4ms).

Figure 9. Periodic data collection mode oscillator training timing diagram

6.5.1.2 PSI5 oscillator training

bits of the user read/write register array. The sync pulse period is preprogrammed into the PDCM_PER[2:0] bits. The device then calculates the number of transmission periods for every 4 ms (nPSI5_PER_4ms_TYP).

The device counts the number of oscillator cycles in nPSI5_PER_4ms_TYP periods (nOSC_4ms).
nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training window (OscTrainWIN)

command ending the nPDCM_PER_OSC calculation. Figure 10. PSI5 oscillator training timing diagram FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

NXP Semiconductors FXPS71407 DSI3 and PSI5 compatible absolute and relative pressure sensor mode, the device will not respond to sync pulses during initialization phase 1, but oscillator training will be enabled tRS_PM after reset.

6.5.2 Oscillator training error handling

If the user enables oscillator training, but the conditions are not correct to complete oscillator training, the OSCTRAIN_ERR bit is set in the DEVSTAT register. The following conditions will result in the OSCTRAIN_ERR bit being set.

The CLK_CAL_EN bit in the TIMING_CFG register is set and the measured period (nOSC_4ms) for any mode is outside the oscillator training window (OscTrainWIN).
The result of the comparison is filtered with an up and down counter.
If nOSC_4ms is outside the oscillator training window, the counter is incremented.
If nOSC_4ms is inside the oscillator training window, the counter is decremented.
If the counter reaches 64 counts, the OSCTRAIN_ERR bit is set.
The up and down counter has a maximum value of 127 and a minimum value of 0.
The command and response mode period established by the PDCM_PER and CRM_PER settings does not fall within the 500 µs to 4 ms window.
The command and response mode period established by the PDCM_PER and CRM_PER settings is not a whole number divisor of 4 ms.

6.6 Pressure sensor signal path

6.6.1 Transducer

See Section 9 "Static characteristics" and Section 10 "Dynamic characteristics" for transducer parameters.

6.6.2 Self-test functions

The device includes analog and digital self-test functions to verify the functionality of the transducer and the signal chain. The self-test functions are selected by writing to the ST_CTRL[3:0] bits in the DSP_CFG_U5 register. The ST_CTRL bits select the desired self-test connection as described below. Once the ENDINIT bit is set, the ST_CTRL bits are forced to 0000. Future writes to the ST_CTRL bits are disabled until a device reset.

6.6.2.1 Startup PABS common mode verification

When the PABS common mode self-test is selected, the ST_ACTIVE bit is set, the ST_ERROR is cleared, and the device begins an internal measurement of the common mode signal of the P-cells and compares the result against a predetermined limit. If the result exceeds the limit, the ST_ERROR bit is set. The PABS common mode self-test will repeat continuously every tST_INIT when the ST_CTRL bits are set to the specified value. Once the test is disabled, the ST_ERROR bit will be updated with the final test result within tST_INIT of disabling the test. The ST_ACTIVE bit will remain set until the final test result is reported. Figure 11 is an example of a user controlled self-test procedure: FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

(1) Current Self Test iteration unaffected, future iterations disabled. Figure 11. User-controlled PABS common mode self-test flowchart

6.6.2.2 Startup digital self-test verification

when the ENDINIT bit is not set. Table 119. Startup digital self-test verification FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

6.6.2.3 Startup sense data fixed value verification

be selected when the ENDINIT bit is not set. Table 120. Startup sense data fixed value verification

6.6.2.4 PSI5 automatic startup self-test procedure

case, the ST_ERROR bit can only be cleared by a device reset. After the self-test, the P0 filter startup is reset to the first phase and the filter is initialized for tST_P0INIT. input to the DSP. A simplified block diagram is shown in Figure 12. Figure 12. ΣΔ converter block diagram

6.6.4 Digital signal processor

Figure 13. Signal chain diagram Table 121. Digital signal processor details

6.6.4.1 Decimation sinc filter

Figure 14. Sinc filter response

6.6.4.2 Signal trim and compensation

The device includes digital trim to compensate for sensor offset, sensitivity, and nonlinearity over temperature. Table 122. Signal trim and compensation

6.6.4.3 Low-pass filter

Data from the sinc filter is processed by an infinite impulse response (IIR) low-pass filter. The filter coefficients are selected with the LPF[3:0] bits in the DSP_CFG_U1 registers. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

characteristics". Filter characteristics for the highest sample rate are illustrated in the following figures.

1000 Hz (dB)

400 Hz 3-Pole LPF Output: Magnitude Response

400 Hz 3-Pole Output: Signal Delay

370 Hz 2-Pole LPF Output: Magnitude Response

370 Hz 2-Pole Output: Signal Delay

800 Hz 4-Pole LPF Output: Magnitude Response

800 Hz 4-Pole Output: Signal Delay

1000 Hz 4-Pole LPF Output: Magnitude Response

1000 Hz 4-Pole Output: Signal Delay

Figure 18. 1000 Hz, 4-pole low-pass filter response

6.6.4.4 P0 low-pass filter and gradient filter

Figure 19. P0 low-pass filter block diagram Equation 6 applies to the low-pass filter block shown in Figure 19. Table 124. Low-pass filter details and timing for the startup phases FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 124. Low-pass filter details and timing for the startup phases...continued Note: When rate limiting is disabled, the output of the rate limiting is set to the output of the P0 low-pass filter. Figure 20. 0.16 Hz, 1-Pole P0 low-pass filter response the ambient pressure, absolute pressure for each ΔP/P0 range is shown in Section 6.6.4.5 "ΔP/P0 calculation". FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Figure 21. P0 and PABS range

6.6.4.6 Data interpolation

An example of the output interpolation is shown in Figure 22. Figure 22. Output interpolation example

6.6.4.7 Output scaling equations

6.6.4.7.1 Absolute pressure scaling equation

Equation 11 is used to convert absolute pressure readings with the variables as specified in Table 125. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Note: The specified values apply only if the P_CAL_ZERO value is set to 0000h. Table 125. Absolute pressure readings variables

6.6.4.7.2 Relative pressure scaling equation

Equation 12 is used to convert relative pressure readings with the variables as specified in Table 126. Note: The specified values apply only if the P_CAL_ZERO value is set to 0000h. Table 126. Relative pressure readings variables FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 126. Relative pressure readings variables...continued

6.6.5 Temperature sensor

6.6.5.1 Temperature sensor signal chain

characteristics" and Section 10 "Dynamic characteristics". Figure 23. Temperature sensor signal chain block diagram

6.6.5.2 Temperature sensor output scaling equations

Table 127. Conversion variables

6.6.6 Common mode error detection signal chain

Figure 24. Common mode error detection signal chain block diagram

6.7 Pressure sensor accuracy (drift over temperature and life)

The absolute pressure accuracy is specified in Figure 25 and Figure 26. drift over temperature is guaranteed by production testing. Figure 26 have been obtained by qualification testing to conform to the AEC-Q100[4] standards. for lifetime performance is (1 kPa × multiplying factor) = 2 kPa. Figure 25. Absolute pressure accuracy as a function of temperature FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

7 Limiting values

may be damaged or the lifetime may be reduced. Table 128. Limiting values [1] Functionality verified by characterization. [2] Parameter verified by qualification testing. [3] Parameter verified by functional evaluation. [4] Functionality verified by modeling, simulation and/or design verification.

8 Recommended operating conditions

Table 129. Operating conditions [1] Parameter verified by final test. [2] Parameter verified by functional evaluation. [3] Functionality verified by modeling, simulation and/or design verification. [4] Parameter verified by qualification testing. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

9 Static characteristics

4 V, VBUS_I = 20 V)

Table 130. Static characteristics...continued [1] Parameter verified by final test. [2] Parameter verified by functional evaluation. [3] Functionality verified by characterization. [4] Parameter verified by qualification. [5] See Section 6.7 for accuracy over temperature and life, including nonlinearity, full scale = PABS range. [6] Functionality verified by modeling, simulation and/or design verification. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

[8] See Table 156, PSI5 data values for DATA_EXT = 0 and DATA_EXT = 1.

10 Dynamic characteristics

[1] Parameter verified by functional evaluation. [2] Functionality verified by modeling, simulation and/or design verification. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

NXP Semiconductors FXPS71407 DSI3 and PSI5 compatible absolute and relative pressure sensor occupy boundaries between material surfaces within the sensor package. When decompression occurs, the gas molecules may collect, form bubbles and possibly result in delamination of the gel from the material it protects. If a bubble is located on the pressure transducer surface, or on the bond wires, the sensor measurement may shift from its calibrated transfer function. In some cases, these temporary shifts could be outside the tolerances listed in the data sheet. In rare cases, the bubble may bend the bond wires and result in a permanent shift.

11.1 Media compatibility – pressure sensors only

For more information regarding media compatibility, contact your local sales representative. Note: The devices contain a gel that protects the pressure transducer and its inter-die connection wires from corrosion, which might otherwise result in catastrophic failure modes. NXP has observed that direct exposure to materials with the same or nearly-the-same solubility can potentially result in a corruption of the protective gel. A corruption can be less than catastrophic in nature, however may result in an offset of the pressure measurement from its factory calibrated value. An offset can potentially be larger than the allowed tolerances published in this data sheet. Further, NXP does not recommend direct exposure to strong acid or strong base compounds as they can potentially result in a similar corruption as described above, or may result in a dissolution of the protective gel and/or the metal lid adhesive and/or the plastic device body. Such a dissolution can be catastrophic in nature, damaging the transducer surfaces and/or internal wire bonds and/or the control die surfaces. A potential dissolution may result in a similar offset, or cause the device to indicate overflow/underflow status, or may cause the device to cease operating in the worst case. For a list of compounds known to generate out-of-tolerance offsets and/or catastrophic device failure, please contact an NXP sales representative.

11.2 DSI3 protocol

The DSI3 standard[1] describes two function classes: signal function class and power function class. The device is a slave conforming to the signal function class requirements. The device does not support power function class. This section describes the DSI3 signal function class features supported by the device.

11.2.1 DSI3 physical layer

11.2.1.1 Command receiver

The command receive block converts voltage transitions on the BUS_I pin to a digital pulse train for decoding by the DSI data link layer. The supply voltage can vary throughout the specified range, so the communication high voltage (VHIGH) must be sampled and averaged with a low-pass filter. The communication low voltage is then determined by comparing the supply voltage to the sampled and averaged VHIGH voltage. Figure 27 shows a block diagram of the command receiver physical layer. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

Figure 29. DSI3 command receiver timing diagram: microcut

11.2.1.2 Response transmitter

characteristics" and Section 10 "Dynamic characteristics". Figure 30. DSI3 transmitter block diagram

11.2.1.3 Discovery mode current sense

timing parameters are specified in Section 9 "Static characteristics" and Section 10 "Dynamic characteristics". method for resistor connected daisy chain devices". FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Figure 31. Discovery mode current sense circuit block diagram Figure 32. DSI3 discovery mode sensing timing diagram

11.2.2 Address assignment

11.2.2.1 Address assignment method for parallel connected slaves

11.2.2.2 Address assignment method for bus switch connected daisy chain devices

Section 11.2.2.1 "Address assignment method for parallel connected slaves", or an unprogrammed address. regarding command and response mode. command addressed to Address $0 (global command), which writes the PADDR[3:0] bits to a nonzero value. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

NXP Semiconductors FXPS71407 DSI3 and PSI5 compatible absolute and relative pressure sensor Once a physical address is assigned to the device, command and response mode is used with the assigned physical address for further configuration. On power up, the device bus switch output defaults to deactivated.

11.2.2.3 DSI3 discovery mode: address assignment method for resistor connected daisy chain

A device connected in daisy chain via a resistor has an unprogrammed address and uses discovery mode to obtain its physical address (PADDR[3:0]). The master device must initiate discovery mode automatically after power is applied to the bus segment by sending a sequence of discovery commands. Discovery mode timing is defined in Section 10 "Dynamic characteristics". If the ENDINIT bit is not set and the PADDR[3:0] field is set to '0000', the device will detect a discovery command tSTART_DISC after a power-on-reset and for intervals of tPER_Disc until discovery mode has ended (the maximum value of tSTART_DISC). Figure 31 shows a timing diagram of the discovery protocol for a four-device segment. The discovery mode follows this sequence: 1. The master powers up the bus segment to a known state. 2. The master transmits the discovery command. 3. After a predetermined delay (tSTART_DISC_RSP), all devices without a physical address activate a current ramp to the 2x response current at a ramp rate of iDISC_RAMP. 4. Each device monitors the current through its sense resistor (ΔiSENSE). a. If the current is above iRESP, the device disables its response current, increments its physical address counter, and waits for the next Discovery Command. b. If the current is low (ΔiSENSE less than iRESP), the device continues to ramp its response current to 2 x iRESP in time tDISC_RAMP_RSP and maintains the current at 2 x iRESP for time tDISC_IDLE_RSP. c. After time tDISC_IDLE_RSP, if a device has not detected a current through its current sense resistor of iRESP, the device accepts physical address '1' and disables its response current. 5. After a predefined period (tPER_DISC), the master transmits another discovery command. 6. Steps 3 and 4 are repeated, with the device accepting the address in its address assignment counter if the sense current is low. 7. The master repeats step 5 until it has transmitted discovery commands for all the devices it expects on the bus. 8. Device initialization can now begin using command and response mode. Once the discovery mode is complete, a physical address is assigned to the device, and command and response mode is used with the assigned physical address for further configuration. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

Figure 33. DSI3 discovery mode timing diagram

11.2.3 DSI3 command and response mode

DSI3 command and response mode is the main communication method used for initialization of the device.

11.2.3.1 DSI3 command and response mode command reception

11.2.3.1.1 Bit encoding

Figure 35 shows the bit encoding used for command and response mode commands from the master device. Figure 35. Command and response mode command bit encoding

11.2.3.1.2 Command message format

The command and response mode command format is shown in Table 132. Table 132. Command and response mode – command format Table 133. Command and response mode – field definitions

11.2.3.1.3 Error checking

not match the transmitted CRC, the command is ignored and the device does not respond.

A seed value is preset into the least significant bits of the shift register.
Using a serial CRC calculation method, the receiver rotates the received message and CRC into the least

significant bits of the shift register in the order received (MSB first).

When the calculation on the last bit of the CRC is rotated into the shift register, the shift register contains the
If the shift register contains all zeros, the CRC is correct.
If the shift register contains a value other than zero, the CRC is incorrect.

The CRC polynomial and seed for command and response mode are shown in Table 134. Table 134. Command and response mode command CRC Some example CRC calculations are shown in Table 135. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 135. Command and response mode – CRC calculation examples

11.2.3.2 DSI3 command and response mode response transmission

Figure 36. Command and response mode response example

11.2.3.2.1 Symbol encoding

three symbol (nine chip), 12-bit data packet. Figure 37. Response symbol encoding bits. Table 136 shows the symbol encoding used by the device. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

1010 A 1 2 2

1011 B 2 2 1

1100 C 1 2 0

1101 D 2 0 0

1110 E 1 0 1

1111 F 1 2 1

Table 136. Symbol mapping

11.2.3.2.2 Response message format

The command and response mode response format is shown in Table 137 . Table 137. Command and response mode – response format Table 138. Command and response mode – field definitions

11.2.3.2.3 Error checking

A seed value is preset into the least significant bits of the shift register.
Using a serial CRC calculation method, the transmitter rotates the transmitted message into the least

significant bits of the shift register, MSB first.

Following the transmitted message, the transmitter feeds eight zeros into the shift register, to match the
When the last zero is fed into the input adder, the shift register contains the CRC.

The CRC polynomial and seed for command and response mode are shown in Table 139. Table 139. Command and response mode response CRC

11.2.3.3 DSI3 command and response mode timing

Section 10 "Dynamic characteristics". Figure 38. Command and response mode timing diagram

11.2.3.4 DSI3 command and response mode command summary

11.2.3.4.1 Register read command

calculated, the device responds to the command. the DSI global device address of 0000. array". If an attempt is made to read a register that is not readable, the device will respond with all zero data. PA[3:0] DSI physical address. This field contains the physical address. This field must match the PADDR[3:0] bits in the PHYSADDR register. Otherwise, the command is ignored. RA[7:1] RA[7:1] contains the upper 7 bits of the byte address for the register to be read. Table 140. Register read command format PA[3:0] DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register. Table 141. Register read command: response format array" will result in a valid response. The data for the registers will be 0000h.

11.2.3.4.2 Register write command

write command to the PHYSADDR register". array". Writable registers along with their byte addresses are shown in Section 6.1 "User accessible data array". PA[3:0] DSI physical address. This field contains the physical address. This field must match the PADDR[3:0] bits in the PHYSADDR register. Otherwise, the command is ignored. RA[7:0] RA[7:0] contains the byte address of the register to be read. RD[7:0] RD[7:0] contains the data to be written to the register addressed by RA[7:0]. Table 142. Register write command format PA[3:0] DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register. Table 143. Register write command: response format data array" will not execute, but will result in a valid response. The data for the registers will be 0000h. the registers will be the current contents of the register.

11.2.3.4.3 Global register write command to the PHYSADDR register

The register write command is written to the PHYSADDR register.
The PADDR[3:0] bits of the PHYSADDR register are equal to '0000' prior to the register write being

If these conditions are met, the device will execute the register write and respond to the command. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

RA[7:0] RA[7:0] must be set to the PHYSADDR register address. RD[3:0] RD[3:0] contains the new physical address for the device. Table 144. Global register write command format PA[3:0] The new DSI physical address programmed to the PADDR[3:0] bits in the PHYSADDR register. RD[7:0] The data contained in the PHYSADDR register after the register write is executed. Table 145. Global register write command – response format

11.2.3.4.4 Enter periodic data collection mode command

the global address of '0000'. Otherwise, the command is ignored. Table 146. Enter periodic data collection mode command format PA[3:0] DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register. Table 147. Enter periodic data collection mode command: response format

11.2.3.4.5 Reserved commands

will be echoed and the correct CRC will be transmitted. The data included in the response is undefined. register. Otherwise, the command is ignored. Table 148. Reserved commands FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

PA[3:0] DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register. Table 149. Reserved command response format

11.2.4 DSI3 periodic data collection mode and background diagnostic mode

optional background diagnostic mode is enabled.

11.2.4.1 DSI3 periodic data collection mode and background diagnostic mode command

well as background diagnostic mode command fragments as described below.

11.2.4.1.1 Bit encoding

11.2.4.1.2 Command message format

either a '1' or a '0'. Figure 39 shows the broadcast read commands supported by the device. Figure 39. Background diagnostic mode command bit encoding

Background diagnostic mode commands are transmitted and decoded in 2-bit or 4-bit fragments depending on the state of the BDM_FRAGSIZE bit in the BDM_CFG register.
The device responds with the periodic data collection mode response if and only if the command is a broadcast read command or a command fragment.
A broadcast read command or any command length other than 2 or 4 bits resets the background diagnostic mode command decode.
The device responds with a background diagnostic mode response only when a full 32-bit command is received and the decoded command is a valid command and response mode command. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

11.2.4.1.3 Error checking

No error checking is employed for the broadcast read commands.

11.2.4.2 DSI3 periodic data collection mode response transmission

Figure 40. Periodic data mode response transmission

11.2.4.2.1 Symbol encoding

11.2.4.2.2 Response message format

registers (address $1A, $1B)".

If enabled in the PDCMFORMAT[2:0] bits, the SOURCEID field includes the value stored in the SOURCEID_x[3:0] bits of the SOURCEID_x register.
If enabled in the PDCMFORMAT[2:0] bits, the keep alive counter field is a 2-bit rolling message counter that is independently incremented for each SOURCEID. The initial value of the counter is '00'. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

Section 11.2.7 "DSI3 exception handling" for details on exception handling.

The sensor data field includes the sensor data as selected by the DATATYPEx bits for the SOURCEID. Sensor data field values[3:0] Description DEVSTAT state SUP_ERR_ DIS state Error priority STATUS field size = 4 STATUS field size = 0 0 0 0 0 Normal mode N/A N/A 16 Sensor data 0 0 0 1 Normal mode, user array not locked (UF2 region has not been locked) N/A N/A 15 Sensor data The sensor data field error code is transmitted for a minimum of one transmission 0 0 1 0 Self-test incomplete or self- test active or self-test error present Bit set in DSP_ STAT: ST_INCMPLT or ST_ACTIVE or ST_ERROR N/A 14 Sensor data The sensor data field error code is transmitted for a minimum of one transmission 0 0 1 1 Oscillator training error Bit set in DEVSTAT3 N/A 13 Sensor data The sensor data field error code is transmitted for a minimum of one transmission 0 1 0 0 PABS out of range error Bit set in DSP_ STAT: PABS_HIGH or PABS_ LOW or PABS_ MISMATCH N/A 12 Sensor data The sensor data field error code is transmitted for a minimum of one transmission 0 1 0 1 Temperature error Bit set in DEVSTAT2 N/A 11 Sensor data The sensor data field error code is transmitted for a minimum of one transmission 0110 to 0111 Reserved N/A N/A 9.10 Sensor data The sensor data field error code is transmitted for a minimum of one transmission 1 0 0 0 User OTP memory error (UF2) U_OTP_ERR set in DEVSTAT2 N/A 8 The sensor data field error code is transmitted for a minimum of one transmission 1 0 0 1 User R/W memory error (UF2) U_RW_ERR set in DEVSTAT2 N/A 7 The sensor data field error code is transmitted for a minimum of one transmission 1 0 1 0 NXP OTP memory error F_OTP_ERR set in DEVSTAT2 N/A 6 The sensor data field error code is transmitted for a minimum of one transmission 1 0 1 1 Test mode active TESTMODE bit set in DEVSTAT N/A 5 The sensor data field error code is transmitted for a minimum of one transmission 0 No response until the supply monitor timer expires. The sensor data field error code is transmitted for a minimum of one transmission (See Section 6.2.2 "DEVSTATx – device status registers (address $01- $04)") 1 1 0 0 Supply error Bit set in DEVSTAT1 No response until the supply monitor timer expires. (See Section 6.2.2 "DEVSTATx – device status registers (address $01- $04)") 1 1 0 1 Reset error DEVRES Set N/A 3 The sensor data field error code is transmitted for a minimum of one transmission 1110 to 1111 Reserved N/A N/A 1,2 The sensor data field error code is transmitted for a minimum of one transmission

Table 150. Periodic data collection mode status field definition

11.2.4.2.3 Error checking

first, consistent with the transmission order of the message.

A seed value is preset into the least significant bits of the shift register.
Using a serial CRC calculation method, the transmitter rotates the transmitted message into the least

Following the transmitted message, the transmitter feeds eight zeros into the shift register, to match the
When the last zero is fed into the input adder, the shift register contains the CRC.

The CRC polynomial and seed for periodic data collection mode are shown in Table 151. Table 151. Periodic data collection mode response CRC Some example CRC calculations are shown in Table 152. Table 152. Periodic data collection mode – CRC calculation examples

11.2.4.3 DSI3 periodic data collection mode timing

Section 10 "Dynamic characteristics". Figure 41. Periodic data collection mode timing diagram

11.2.4.4 Background diagnostic mode response transmission

11.2.4.4.1 Symbol encoding

11.2.4.4.2 Response message format

If a complete, 32-bit command is received, and decoded to a valid command and response mode command, the device provides a background diagnostic mode response. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

Responses are initiated by the master transmitting 1-bit broadcast read commands following a completed background diagnostic mode command transmission.
Responses are transmitted in one or two symbol fragments (depending on the state of the BDM_FRAGSIZE bit) following the 1-bit broadcast read command, using the same timing window within the frame that the background diagnostic mode command used.
Responses are transmitted if and only if broadcast read commands are received.
Four or eight consecutive broadcast read commands are required following a valid background diagnostic mode command to complete a response transmission (depending on the state of the BDM_FRAGSIZE bit).
If any command other than the broadcast read command is received, no response is transmitted and the remainder of the broadcast read command response is terminated.
The data to be transmitted in the response is latched just before the first symbol of the background diagnostic mode response. See Section 11.2.4.5 "DSI3 background diagnostic mode timing" for background diagnostic mode timing.

11.2.4.4.3 Error checking

11.2.4.5 DSI3 background diagnostic mode timing

BDM_FRAGSIZE is set to '1' (4 bits). Timing parameters are specified in Section 10 "Dynamic characteristics". Figure 42. Background diagnostic mode timing diagram FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

11.2.4.6 DSI3 periodic data collection mode and background diagnostic mode command

read command". The register write command is not supported in background diagnostic mode.

11.2.4.7 DSI3 PDCM data transmission modes

11.2.4.7.1 Simultaneous sampling mode (SS_EN = 1)

11.2.4.7.2 Synchronous sampling mode with minimum latency (SS_EN = 0)

Figure 44. Synchronous sampling mode with minimum latency

11.2.5 Initialization timing

NXP Semiconductors FXPS71407 DSI3 and PSI5 compatible absolute and relative pressure sensor

11.2.6 Maximum number of devices on a network

The theoretical maximum number of devices on a DSI3 network is 16: 1 master and 15 slaves. The practical limit for the number of devices on a bus is dependent on the minimum common capability of the devices on the bus. The capability of the device is different depending on the bus configuration and operating mode. The impact of the device capability on the practical limit for the number of devices on the network is described in chain network", and Section 11.2.6.3 "Resistor connected daisy chain network using discovery mode".

11.2.6.1 Preconfigured, parallel connected network

The number of devices in a preconfigured, parallel connected network is not directly limited by the capability of the device. The practical limit is determined by a combination of the following:

The capability of the master device, including, but not limited to: – The bus operating voltage – The bus supply current – The bus current limit – The bit rate – The response current detection capability (distinguishing response current from quiescent current)
The total quiescent current of all slaves on the network.

11.2.6.2 Bus switch connected daisy chain network

The number of devices in a bus switch connected daisy chain network is not directly limited by the capability of the device. The practical limit is determined by a combination of the following:

The capability of the master device, including, but not limited to: – The bus operating voltage – The bus supply current – The bus current limit – The bit rate – The response current detection capability (distinguishing response current from quiescent current)
The total quiescent current of all slaves on the network.
The current handling capability and resulting voltage drop of the external bus switches in the network.

11.2.6.3 Resistor connected daisy chain network using discovery mode

The number of devices in a resistor connected daisy chain network is limited by the capability of the device. The maximum number of equivalent devices connected to the BUS_O pin of a device is three. This is limited by the total quiescent current drawn from the BUS_O pin during discovery mode (IBUS_O_q). The practical limit is determined by a combination of the above restriction and the following:

The capability of the master device, including, but not limited to: – The bus operating voltage – The bus supply current – The bus current limit – The bit rate – The response current detection capability (distinguishing response current from quiescent current)
The total quiescent current of all slaves on the network.
The maximum allowed quiescent current drawn from the BUS_O pin of other slaves in the system.
The resulting voltage drop of the Discovery mode resistors in all slaves in the network. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

11.2.7 DSI3 exception handling

Table 153 summarizes the exception conditions detected by the device and the response for each exception.

ST_INCMPLT set, PDCM disabled. The device must be reinitialized VBUS_I error N/A VBUS_I < VBUS_I_UV_F • Response current deactivated
BUSIN_UV_ERR set, PDCM Status set as specified in Section 11.2.4.2.2
The device ignores commands in CRM VBUF error N/A VBUF < VBUF_UV_F • Response current deactivated
VBUFUV_ERR set, PDCM Status set as specified in Section 11.2.4.2.2
The device ignores commands in CRM Internal regulator error N/A Internal regulator undervoltage condition • The device is held in reset
No response to DSI commands
If activated, BUSSW_L or BUSSW_H is deactivated
The device must be reinitialized when the internal regulator returns above the threshold OTP error detection fault (Factory array) N/A Error detected in factory programmed OTP array.
Periodic data collection mode response data set to error response
F_OTP_ERR set, PDCM Status set as specified in Section 11.2.4.2.2 OTP error detection fault (User array) N/A Error detected in user programmed OTP array and the LOCK_U bit is set.
Periodic data collection mode response data set to error response
U_OTP_ERR set, PDCM Status set as specified in Section 11.2.4.2.2 No N/A N/AUser R/W array error detection fault Yes Error detected in user read write registers and the ENDINIT bit is set.
Periodic data collection mode response data set to error response
U_RW_ERR set, PDCM status set as specified in Section 11.2.4.2.2 No ST activated during initialization • Internal self-test circuitry enabled
Self-test activation incomplete status cleared
Sensor data registers (SNSDATAx_x) contain self-test active data
ST_ACTIVE set Self-test activated Yes ST activated in periodic data collection mode
Periodic data collection mode sensor response data normal
Self-test activation ignored No In initialization, before self-test • Normal responses to command and response modeSelf-test never activated after POR Yes In PDCM, self-test incomplete • Periodic data collection mode sensor response data normal
ST_INCMPLT set, PDCM status set as specified in Section 11.2.4.2.2

Table 153. DSI3 exception handling

11.2.7.1 Daisy chain and discovery mode error handling

Table 154 shows the effect of internal failure modes on the discovery and daisy chain initialization procedures. Table 154. DSI3 error handling – discovery mode and daisy chain mode FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

11.3 PSI5 protocol

11.3.1 Communication interface overview

a PSI5 compatible two-wire interface, with parallel or serial (daisy chain) connections to the satellite modules. Figure 46 shows one possible system configuration for multiple satellite modules in parallel. Figure 46. PSI5 satellite interface diagram

11.3.2 Data transmission physical layer

device to the PSI5 master are accomplished via modulation of the current on the power supply line.

11.3.2.1 Synchronization pulse

Figure 47. Synchronous communication overview

11.3.2.1.1 Synchronization pulse detection

initiates the timers associated with response messages. Figure 48. Synchronization pulse detection circuit

The valid sync pulse detection signal is set.
The detection counter is reset and disabled for tSYNC_OFF (referenced from tTRIG). tSYNC_OFF can be

11.3.2.1.2 Synchronization pulse pulldown function

and is activated for tPD_ON. mode until the run command is received.

11.3.3 Data transmission data link layer

11.3.3.1 Bit encoding

'0' data are transmitted, There will also be a transition at the start of a bit time. Figure 51. Manchester data bit encoding

11.3.3.2 PSI5 data transmission

PSI5 data transmission frames are composed of two start bits, a 10-bit data word, and error detection bit(s). Figure 52. Example Manchester encoded data transfer – psi5-x10x

11.3.3.3 Error detection

NXP Semiconductors FXPS71407 DSI3 and PSI5 compatible absolute and relative pressure sensor

11.3.3.3.1 Parity error detection

When parity error detection is selected, even parity is employed. The number of logic '1' bits in the transmitted message must be an even number. 11.3.3.3.2 3-bit CRC error detection When CRC error detection is selected, a 3-bit CRC is appended to each response message. The 3-bit CRC uses a generator polynomial of g(x) = x3+x+1, with a nondirect seed value = '111'. Message data from the transmitted message is read into the CRC calculator LSB first, and the data is augmented with three '0's. Start bits are not used in the CRC calculation. Table 155 shows some example CRC calculation values for 10-bit data transmissions. Data transmitted CRC Hex D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C2 C1 C0 000h 0 0 0 0 0 0 0 0 0 0 1 1 0 0CCh 0 0 1 1 0 0 1 1 0 0 0 1 1 151h 0 1 0 1 0 1 0 0 0 1 0 0 0 1E0h 0 1 1 1 1 0 0 0 0 0 0 1 1 1F4h 0 1 1 1 1 1 0 1 0 0 0 1 0 220h 1 0 0 0 1 0 0 0 0 0 1 0 0 275h 1 0 0 1 1 1 0 1 0 1 1 1 1 333h 1 1 0 0 1 1 0 0 1 1 0 0 1 3FFh 1 1 1 1 1 1 1 1 1 1 1 0 0 Table 155. PSI5 3-bit CRC calculation examples

11.3.3.4 PSI5 data field and data range values

Description

(EMSG_EXT = 0 in PSI5_CFG) P0 data transmissions in initialization phase 3 +511 1FFh +511 — 1FFh +510 1FEh +510 — 1FEh +509 1FDh +509 — 1FDh +508 1FCh +508 — 1FCh +507 1FBh +507 — 1FBh +506 1FAh +506 — 1FAh +505 1F9h +505 — 1F9h +504 1F8h +504 — 1F8h +503 1F7h +503 — 1F7h +502 1F6h +502 — 1F6h +501 1F5h +501 — 1F5h Reserved Reserved — +500 1F4h +500 — 1F4h Sensor defect error Sensor defect error — +499 1F3h +499 — 1F3h +498 1F2h +498 — 1F2h +497 1F1h +497 — 1F1h Reserved Reserved — Table 156. PSI5 data values FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

NXP Semiconductors FXPS71407 DSI3 and PSI5 compatible absolute and relative pressure sensor 10-bit data value, DATA_EXT = 0 10-bit data value, DATA_EXT = 1 Decimal Hex Decimal Binary Hex Description (EMSG_EXT = 1 in PSI5_CFG) (EMSG_EXT = 0 in PSI5_CFG) P0 data transmissions in initialization phase 3 +496 1F0h +496 — 1F0h +495 1EFh +495 — 1EFh Communication error (OSCTRAIN_ERR bit) +494 1EEh +494 — 1EEh Test mode enabled (TESTMODE bit set) +493 1EDh +493 — 1EDh PABS out of range error (PABS_HIGH, PABS_LOW or PABS_MISMATCH bit set) +492 1ECh +492 — 1ECh Temperature error (TEMP0_ERR bit set) +491 1EBh +491 — 1EBh Memory error (F_OTP_ERR, U_OTP_ERR or U_RW_ERR set) Reserved (error mapped to 1F4h) — +490 1EAh +490 — 1EAh Sensor self-test error (ST_ERROR bit set) Sensor self-test error — +489 1E9h +489 — 1E9h Reserved Reserved — +488 1E8h +488 — 1E8h Sensor busy Sensor busy — +487 1E7h +487 — 1E7h Sensor ready Sensor ready — +486 1E6h +486 — 1E6h Sensor ready, but unlocked Sensor ready, but unlocked — +485 1E5h +485 — 1E5h +484 1E4h +484 — 1E4h +483 1E3h +483 — 1E3h Reserved Reserved +482 1E2h +482 — 1E2h Bidirectional communication: RC error Bidirectional communication: RC error +481 1E1h +481 — 1E1h Bidirectional communication: RC OK Bidirectional communication: RC OK +308 to +480 134h to 1E0h — Unused Unused — +307 133h +480 — 1E0h Maximum positive sensor value Maximum positive sensor value — — · +3 03h +3 — 03h +2 02h +2 — 02h +1 01h +1 — 01h Positive sensor values Positive sensor values — 0 0 0 — 0 Zero[1] Zero — –1 3FFh –1 — 3FFh –2 3FEh –2 — 3FEh –3 3FDh –3 — 3FDh Negative sensor values Negative sensor values — — · –102 39Ah –480 — 220h Maximum negative sensor value Maximum negative sensor value — –103 to –480 399h to 220h — Unused Unused — –481 21Fh –481 1000011111 21Fh P0: D2:D0, in 3 LSBs –496 210h –496 1000010000 210h Initialization data codes 10-bit status data nibble 1 to 16 (0000 to 1111) (Dx) P0: D5:D3, in 3 LSBs –497 20Fh –497 1000001111 20Fh P0: D8:D6, in 3 LSBs –512 200h –512 1000000000 200h Initialization data IDs Block ID 1 to 16 (10-bit mode) (IDx) P0: D11:D9, in 3 LSBs Table 156. PSI5 data values...continued [1] Not equivalent to ΔP/P0 = 0. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

11.3.4 Initialization

Initialization phase 1: No data transmissions occur
Initialization phase 2: Sensor self-test and transmission of configuration information
Initialization phase 3: Transmission of the sensor busy and/or sensor ready/sensor defect messages followed by the P0 value Once initialization is completed the device begins normal mode operation, which continues as long as the supply voltage remains within the specified limits. In asynchronous mode, initialization data is transmitted for source ID 0 only. In synchronous mode, initialization data is transmitted for each enabled source ID. In daisy chain mode, initialization data is transmitted in the source ID 0 time slot as defined by the sensor address as documented in Section 11.3.6 "Daisy chain mode". aaa-023836 POR Init 2 Init 3 Normal ModeInit 1 IIDLE VIDLE Normal Mode Sync Pulses VIDLE SYNC GROUND IIDLE + IMOD Sync Pulses Ignored or Program Mode Entry . . .

Figure 53. PSI5 sensor 10-bit initialization

Power-on reset
Device initialization
Program mode entry verification
P0 filter initialization
Self-test Figure 54 and Figure 55 show the PSI5 initialization timing, the P0 out of range error is delayed by an internal counter (2 s). The delay is included as an additional mitigation to avoid any unwanted ‘out-of-range event’ due to a small transient change in P0 around the thresholds. The counter is reset at the start of phase 0, and is not reset depending on the P0 value and continues for 2 seconds. P0 value is compared to the threshold after the counter stops and an error message is transmitted if it is out of range. During normal operation (after the initialization) an error message is transmitted immediately when P0 goes out-of-range. Figure 54 shows the timing for internal and external initialization in synchronous mode. Figure 55 shows the timing for internal and external initialization in asynchronous mode. Timing parameters are specified in Section 10 "Dynamic characteristics". FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

Figure 54. PSI5 initialization timing, synchronous mode Figure 55. PSI5 initialization timing, asynchronous mode

11.3.4.1 PSI5 initialization phase 1

During PSI5 initialization phase 1, the device begins internal initialization and self-checks, but transmits no data.

Internal delay to ensure that analog circuitry has stabilized (tPOR_PSI5)
P0 filter initialization begins (tPSI5ST_START)
Monitor for the programming mode entry sequence (tPME)
If the programming mode entry sequence is not detected, the device enters initialization phase 2 (tPSI5_INIT2)

11.3.4.2 PSI5 initialization phase 2

Table 157. PSI5 initialization phase 2 data transmission order The initialization phase 2 time is calculated using Equation 14.

TransNibble = # of transmissions per data nibble
2:1 for ID, and 1 for data
k = The repetition rate for the data fields
DataFields = 32 data fields or 48 data fields (if INIT2_EXT is set)
tS-S = Sync pulse period

11.3.4.2.1 PSI5 initialization phase 2 data transmissions

Table 158. Initialization phase 2 time

1111 USERDATA_7[7:4] User-specific data User

0001 USERDATA_8[7:4] User-specific data User

1111 Reserved Reserved Varies

Table 159. PSI5 initialization phase 2 data...continued Note: Constant values are transmitted for all fields marked as reserved.

11.3.4.3 Internal self-test

11.3.4.4 Initialization phase 3

initialization. Self-test terminates successfully after one successful self-test sequence. Once internal self-test is completed, the device transmits two sensor ready commands. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

NXP Semiconductors FXPS71407 DSI3 and PSI5 compatible absolute and relative pressure sensor

P0 transmission #0: 0 0 P0, D11 P0, D10 P0, D9
P0 transmission #1: 0 1 P0, D8 P0, D7 P0, D6
P0 transmission #2: 1 0 P0, D5 P0, D4 P0, D3
P0 transmission #3: 1 1 P0, D2 P0, D1 P0, D0 In all modes, the ENDINIT bit is automatically set when the device exits initialization phase 3.

11.3.5 Normal mode

11.3.5.1 Asynchronous mode

The device can be programmed to respond in asynchronous mode as specified in Section 6.2.17 "PDCM_RSPSTx_x – DSI3 and PSI5 start time registers (address $26 to $29)". In asynchronous mode, the device transmits data at a fixed rate (tASYNC) and will not respond to normal sync pulses. However, during initialization phase 1, the device will monitor sync pulses to decode the programming mode entry command and allow entry into programming mode.

11.3.5.2 Simultaneous sampling mode

The device can be programmed to respond in simultaneous sampling mode by programming the SS_EN bit to simultaneous sampling mode. In simultaneous sampling mode, the most recent interpolated sensor data sample is latched at tTRIG (rising edge of sync pulse) and transmitted starting at the time programmed in the PDCM_RSPSTx registers, relative to tTRIG. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

Figure 56. Simultaneous sampling mode

11.3.5.3 Synchronous sampling mode with minimum latency

programming the SS_EN bit to synchronous sampling mode. transmitted starting at the time programmed in the PDCM_RSPSTx registers, relative to tTRIG. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Figure 57. Synchronous sampling mode with minimum latency

11.3.6 Daisy chain mode

programmed in the PDCM_RSPSTx registers, relative to tTRIG (rising edge of sync pulse).

After a power on delay of tRS_PM, the device waits for a PSI5 set address command defined in Table 161 and Table 162. – The set address command must be preceded by at least 31 consecutive sync pulses. All other commands must be preceded by either 31 consecutive sync pulses or five consecutive missing sync pulses. – The daisy chain programming command and response formats are defined in Section 11.3.8.2 "PSI5 programming mode – data link layer" using a sync pulse period of ts-s_DC. The response settings are defined in Table 162, with the exception of the time slot. – The response to the PSI5 set address command and all other valid commands uses the address-based time slot specified in Table 163. – If a framing error or CRC error is detected on a received command, the device does not respond. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

After receiving a valid address and completing the response, the device will decode and respond to all Table 163 commands sent to the sensor address it is set to. All responses will be transmitted in the address- based time slot specified in Table 163.
When the run mode command is received, the device responds to the command using the address-based time slot(s) specified in Table 163. The device then ignores all commands and proceeds through initialization phase 2 and initialization phase 3 in response to sync pulses. The following response format is used, regardless of the state of the relevant bits in the device configuration registers: Parameter Reference Value Time Slot Section 6.2.17 "PDCM_RSPSTx_x – DSI3 and PSI5 start time registers (address $26 to $29)" Address-based time slot specified in Table 163 Data Size Section 6.2.12 "SOURCEID_x – source identification registers (address $1A, $1B)" Data size controlled by the PDCMFORMAT bits Error Checking Section 6.2.16 "PSI5_CFG – PSI5 configuration register (address $25)" Even parity Baud Rate Section 6.2.14 "CHIPTIME – chip time and bit time register (address $23)" Baud rate controlled by the CHIPTIME bits

Table 160. Frame parameter to reference

Upon completion of initialization phase 3, the ENDINIT bit is set, the device enters normal mode and responds to all sync pulses with sensor data using the format above. SAdr FC Response (OK)CMD Type A2 A1 A0 F2 F1 F0 Command RC RD1 Short 0 0 0 A2 A1 A0 Set sensor address (daisy chain) OK SAdr Short 1 1 1 0 0 0 Broadcast message – run mode OK 000h Short SAdr <> 1 SAdr <> 6 0 0 0 Activate low-side bus switch BUSSW_CTRL[1:0] = '11 OK 000h Short SAdr <> 1 SAdr <> 6 1 1 1 Activate high-side bus switch BUSSW_CTRL[1:0] = '10' OK 111h Short SAdr <> 1 SAdr <> 6 A2 A1 A0 Set sensor address (daisy chain) OK SAdr

Table 161. Daisy chain programming commands and responses Table 162. Daisy chain programming response code definitions Table 163. Valid daisy chain addresses FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Writes to sensor address 7 are ignored.
If a successful programming mode entry command is received prior to a set address, daisy chain mode is disabled.

11.3.7 Error handling

11.3.7.1 Daisy chain error handling

Table 164 shows the effect of internal failure modes on the daisy chain initialization procedure. Communication error No effect. The device will participate in daisy chain as programmed. PABS out of range and/or mismatch error No effect. The device will participate in daisy chain as programmed. Temperature error No effect. The device will participate in daisy chain as programmed. Memory error No effect. The device will participate in daisy chain as programmed. Self-test error No effect. The device will participate in daisy chain as programmed. Device not locked No effect. The device will participate in daisy chain as programmed. Table 164. Daisy chain error handling

11.3.7.2 Initialization phase 2 error handling

present, the device will complete initialization phase 2 as necessary and then transition to initialization phase 3. Temperature error No effect. The device will attempt to transmit initialization phase 2 data. Memory error No effect. The device will attempt to transmit initialization phase 2 data. Table 165. Initialization phase 2 error handling

11.3.7.3 Initialization phase 3 error handling

longer present, one or more sensor ready commands will be transmitted before entering run mode. Table 166. Initialization phase 3 error handling FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Temperature error No effect. The device will attempt to transmit initialization phase 3 data. Memory error No effect. The device will attempt to transmit initialization phase 3 data. Table 166. Initialization phase 3 error handling...continued

11.3.7.4 Normal mode error handling

11.3.7.4.1 Standard error reporting

Table 167. Standard error reporting

11.3.7.4.2 PSI5 error extension option

Table 168. PSI5 error extension option

11.3.8 PSI5 diagnostic and programming mode

11.3.8.1 PSI5 programming mode entry

At least 31 sync pulses are detected, directly preceding the programming mode entry short command during the programming mode entry window shown in Section 11.3.4 "Initialization". – The window timing is defined in Section 10 "Dynamic characteristics" (tPME). – The sync pulses and programming mode entry command must be received with a sync pulse period of tS- S_PM If the programming mode entry requirement is not met:
Programming mode entry is blocked until the device is reset.
The device proceeds with PSI5 initialization phase 2 and PSI5 initialization phase 3.
The device enters normal mode, and responds as programmed to normal sync pulses. If the programming mode entry requirement is met:
Normal transmissions to sync pulses are terminated.
The device will detect commands if the start condition is met as described in Section 11.3.8.2.2 "PSI5 programming mode – command message format".
The device responds only to valid PSI5 short and XLong commands addressed to sensor address '001', as defined in Section 11.3.8.3 "PSI5 programming mode command and response summary".

11.3.8.2 PSI5 programming mode – data link layer

11.3.8.2.1 PSI5 programming mode – command bit encoding

a logic '1' and the absence of a sync pulse is a logic '0'. Sync pulses are expected at a rate of tS-S_PM.

11.3.8.2.2 PSI5 programming mode – command message format

A minimum of five consecutive logic '0's (with no sync bits)
A minimum of 31 consecutive logic '1's (this includes logic '1's transmitted for the previous response)

The command message format is shown in Table 169. Table 169. Programming mode via PSI5 command data format three logic '0' bits in a row. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 170. Programming mode via PSI5 XLong command data format with sync bits Table 171. Programming mode via PSI5 response message settings

11.3.8.2.3 Short frame command and response format

Short frames are the simplest type of command message. No data is transmitted in a short frame command. command and response summary". The device only supports a short command for programming mode entry. Table 172. Programming mode via PSI5 short frame command and response format

11.3.8.2.4 Long frame command and response format

responses are defined in Section 11.3.8.3 "PSI5 programming mode command and response summary". The device does not support the long frame command. Table 173. Programming mode via PSI5 long frame command and response format

11.3.8.2.5 Extra long frame command and response format

The device supports register read and register write extra long commands. Table 174. Programming mode via PSI5 extra long command and response format

11.3.8.2.6 Command message CRC

CRC calculation values for 10-bit data transmissions. via PSI5 error response summary".

11.3.8.2.7 Command sync pulse blanking time

tSYNC_OFF_250 regardless of the state of the PDCM_CMD_B register value.

11.3.8.2.8 Command timeout

defined in Section 11.3.8.4 "Programming mode via PSI5 error response summary".

11.3.8.3 PSI5 programming mode command and response summary

001 Write WData to register RA7:RA0 Varies Varies OK WData RA7:RA0 Error ErrN 000h

Table 175. Programming mode via PSI5 commands and responses Table 176. Programming mode via PSI5 response code definitions FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

11.3.8.4 Programming mode via PSI5 error response summary

0000 General General error No

0001 Framing Framing error (four consecutive zeroes) Yes

0010 CRC CRC error on received message Yes

0011 Address Sensor address not supported No (Invalid address is ignored)

0100 FC Function code not supported No (N/A)

Table 177. Error response summary ErrN is transmitted in the four LSBs of RD1. All other bits in the response data field are set to '0'.

11.3.9 PSI5 OTP programming procedure

Load desired data into the desired registers using PSI5 write commands.
Write the necessary OTP program sequence to the WRITE_OTP_EN register for the desired OTP region to
Delay tPROG_TIME after the completion of the write OTP program to allow for completion of the OTP writes.
To confirm that no errors occurred during the OTP writes, read the DEVSTAT1 register.
Read back the register values that were written and compare to the desired values to confirm successful OTP

11.4 DSI3 discovery mode

Figure 58. DSI3 discovery mode application diagram

The total bus capacitance must not exceed the values specified in the DSI3 standard[1].
The external components are dependent on the bus master and bus impedance and may vary from application to application. Ref Type Typical value description Component value selection and range Comment R1 General purpose 330 Ω, 5 %, 200 PPM The optimal value of this component should be determined by the system level communication, EMC, and ESD testing Optional bus termination for high inductance bus wire connections. For optimal EMC performance, this component along with C4 are to be placed as close to the BUS_I and BUSRTN connector pins as possible. C1 Ceramic 220 pF, 10 %, 50 V minimum, X7R The optimal value of this component should be determined by the system level communication, EMC, and ESD testing. For optimal EMC performance, this component along with R1 are to be placed as close to the BUS_I and BUSRTN connector pins as possible. C2 Ceramic 0.47 µF, 10 %, 10 V minimum, X7R The optimal value of this component should be determined based on the system level micro-cut immunity requirement. To achieve the specified power supply rejection, the minimum value including all tolerances is 0.22 µF. The maximum specified value including all tolerances is 2 µF. For optimal EMC performance, this component is to be placed as close to the VBUF and BUSRTN pins as possible. C3 Ceramic 100 pF, 10 %, 50 V minimum, X7R The optimal value of this component should be determined by the system level communication, EMC, and ESD testing For optimal EMC performance, this component is to be placed as close to the BUS_O and BUSRTN connector pins as possible. C4 Ceramic 2.2 nF, 10 %, 50 V minimum, X7R The optimal value of this component should be determined by the system level communication, EMC, and ESD testing Optional bus termination for high inductance bus wire connections. For optimal EMC performance, this component along with R1 are to be placed as close to the BUS_I and BUSRTN connector pins as possible.

11.5 DSI3 switch connected daisy chain mode

Figure 59. DSI3 switch connected daisy chain application diagram

The total bus capacitance must not exceed the values specified in the DSI3 standard[1].
The external components are dependent on the bus master and bus impedance and may vary from application to application. Ref Type Typical value description Component value selection and range Comment R1 General purpose 330 Ω, 5 %, 200 PPM The optimal value of this component should be determined by the system level communication, EMC, and ESD testing Optional bus termination for high inductance bus wire connections. For optimal EMC performance, this component along with C4 are to be placed as close to the BUS_I and BUSRTN connector pins as possible. R2 General purpose 100 kΩ, 5 %, 200 PPM The optimal value of this component should be determined by the system level communication, EMC, and ESD testing Pullup resistor for external high-side daisy chain FET C1 Ceramic 220 pF, 10 %, 50 V minimum, X7R The optimal value of this component should be determined by the system level communication, EMC, and ESD testing. For optimal EMC performance, this component along with R1 are to be placed as close to the BUS_I and BUSRTN connector pins as possible. C2 Ceramic 0.47 µF, 10 %, 10 V minimum, X7R The optimal value of this component should be determined based on the system level micro-cut immunity requirement. To achieve the specified power supply rejection, the minimum value including all tolerances is 0.22 µF. The maximum specified value including all tolerances is 2 µF. For optimal EMC performance, this component is to be placed as close to the VBUF and BUSRTN pins as possible. C3 Ceramic 100 pF, 10 %, 50 V minimum, X7R The optimal value of this component should be determined by the system level communication, EMC, and ESD testing For optimal EMC performance, this component is to be placed as close to the BUS_O and BUSRTN connector pins as possible. C4 Ceramic 2.2 nF, 10 %, 50 V minimum, X7R The optimal value of this component should be determined by the system level communication, EMC, and ESD testing Optional bus termination for high inductance bus wire connections. For optimal EMC performance, this component along with R1 are to be placed as close to the BUS_I and BUSRTN connector pins as possible. M1 P-channel MOSFET NTR4502PT1G, or similar The optimal value of this component should be determined by the system level communication, EMC, and ESD testing High-side daisy chain transistor

11.6 PSI5 parallel or universal mode

Figure 60. PSI5 parallel or universal mode application diagram

The total bus capacitance must not exceed the values specified in the PSI5 standard[2].
R1 must be sized to handle both the programming current at the maximum rated temperature for programming and the operating current at the maximum rated temperature for operation.
If the high baud rate is used, it is recommended to reduce the value of C2. The actual value will depend on the bus configuration and number of slaves. Ref Type Typical value description Component value selection and range Comment R1 General purpose 10 Ω, 5 %, 200 PPM The optimal value of this component should be determined by the system level communication, EMC, and ESD testing. For proper device function, the minimum value can be 0 Ω. The maximum value is determined by the minimum bus voltage provided at the module pin and the minimum operating voltage of the device. To meet the minimum PSI5 operating voltage at the module pin, the maximum resistance including all tolerances is 20.5 Ω. If the low response current is used, the maximum resistance including all tolerances is 33.3 Ω. VCC filtering and signal damping C1 Ceramic 2.2 nF, 10 %, 50 V minimum, X7R The optimal value of this component should be determined by the system level communication, EMC, and ESD testing VCC power supply decoupling and signal damping. For optimal EMC performance, this component is to be placed as close to the BUS_I and BUSRTN connector pins as possible. C2 Ceramic 15 nF, 10 %, 50 V minimum, X7R — VCC power supply decoupling. For optimal EMC performance, this component is to be placed as close to the BUS_I and BUSRTN pins as possible. C3 Ceramic 0.47 µF, 10 %, 10 V minimum, X7R The optimal value of this component should be determined based on the system level micro-cut immunity requirement. To achieve the specified power supply rejection, the minimum value including all tolerances is 0.22 µF. The maximum specified value including all tolerances is 2 µF. For optimal EMC performance, this component is to be placed as close to the VBUF and BUSRTN pins as possible.

11.7 PSI5 daisy chain mode

Figure 61. PSI5 daisy chain mode application diagram

R1 must be sized to handle both the programming current at the maximum rated temperature for programming and the operating current at the maximum rated temperature for operation.
If the high baud rate is used, it is recommended to reduce the value of C2. The actual value will depend on the bus configuration and number of slaves. Ref Type Typical value description Component value selection and range Comment R1 General purpose 10 Ω, 5 %, 200 PPM The optimal value of this component should be determined by the system level communication, EMC, and ESD testing. For proper device function, the minimum value can be 0 Ω. The maximum value is determined by the minimum bus voltage provided at the module pin and the minimum operating voltage of the device. To meet the minimum PSI5 operating voltage at the module pin, the maximum resistance including all tolerances is 20.5 Ω. If the low response current is used, the maximum resistance including all tolerances is 33.3 Ω. VCC filtering and signal damping R2 General purpose 20 kΩ, 5 %, 200 PPM The optimal value of this component should be determined by the system level communication, EMC, and ESD testing Gate resistor for external low side daisy chain FET R3 General purpose 100 kΩ, 5 %, 200 PPM The optimal value of this component should be determined by the system level communication, EMC, and ESD testing Gate pulldown resistor for external low side daisy chain FET C1 Ceramic 2.2 nF, 10 %, 50 V minimum, X7R The optimal value of this component should be determined by the system level communication, EMC, and ESD testing VCC power supply decoupling and signal damping. For optimal EMC performance, this component is to be placed as close to the BUS_I and BUSRTN connector pins as possible. C2 Ceramic 15 nF, 10 %, 50 V minimum, X7R The optimal value of this component should be determined by the system level communication, EMC, and ESD testing VCC power supply decoupling. For optimal EMC performance, this component is to be placed as close to the BUS_I and BUSRTN pins as possible. C3 Ceramic 0.47 µF, 10 %, 10 V minimum, X7R The optimal value of this component should be determined based on the system level micro-cut immunity requirement. To achieve the specified power supply rejection, the minimum value including all tolerances is 0.22 µF. The maximum specified value including all tolerances is 2 µF. For optimal EMC performance, this component is to be placed as close to the VBUF and BUSRTN pins as possible. M1 N-channel MOSFET NTR4501NT1G, or similar The optimal value of this component should be determined by the system level communication, EMC, and ESD testing Low-side daisy chain transistor

for download at https://www.nxp.com/docs/en/package-information/SOT1573-2(SC).pdf . Figure 62. Package outline SOT1573-2 (SC) FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Figure 64. Package outline notes HQFN (SOT1573-2(SC))

12.1 Footprint

13 Soldering

Figure 65. SOT1573-2(SC) PCB design guidelines - Solder mask opening pattern FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Figure 66. SOT1573-2(SC) PCB design guidelines - I/O pads and solderable area FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

14 Mounting recommendations

A plugged port exhibits no change in pressure and can be cross checked in the user software. Refer to NXP application note AN1902[6] for proper printed circuit board attributes and recommendations.

15 References

NXP Semiconductors FXPS71407 DSI3 and PSI5 compatible absolute and relative pressure sensor Legal information Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL https://www.nxp.com. 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This document supersedes and replaces all information supplied prior to the publication hereof. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at https://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

NXP Semiconductors FXPS71407 DSI3 and PSI5 compatible absolute and relative pressure sensor Suitability for use in automotive applications — This NXP product has been qualified for use in automotive applications. If this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as “Critical Applications”), then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer. Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to customer’s incorporation of any product in a Critical Application. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. NXP B.V. — NXP B.V. is not an operating company and it does not distribute or sell products. Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

NXP Semiconductors FXPS71407 DSI3 and PSI5 compatible absolute and relative pressure sensor Tables Tab. 5. COUNT – rolling count register – (address Tab. 6. DEVSTAT – device status register – Tab. 10. DEVSTAT 1– device status register – Tab. 12. BUSINUV_ERR – BUS IN undervoltage Tab. 14. INTREGA_ERR – internal analog regulator Tab. 15. INTREG_ERR – internal digital regulator Tab. 16. INTREGF_ERR – internal OTP regulator Tab. 18. DEVSTAT2 – device status register – Tab. 22. U_W_ACTIVE – user OTP write in process Tab. 24. DEVSTAT3 – device status register – Tab. 26. COMMREV – communication protocol revision register – (address $05) bit Tab. 27. TEMPERATURE – temperature register – Tab. 28. DEVLOCK_WR – lock register writes Tab. 30. WRITE_OTP_EN – write OTP enable Tab. 32. BUSSW_CTRL – bus switch control Tab. 34. PSI5_TEST – PSI5 test register – (address Tab. 35. UF_REGION_W – UF region selection Tab. 36. UF_REGION_R – UF region selection Tab. 37. Communication interfaces available via the Tab. 38. Optional communication interfaces Tab. 39. COMMTYPE – communication type Tab. 42. PHYSADDR – physical address register – Tab. 43. SOURCEID_0 – source identification Tab. 44. SOURCEID_1 – source identification Tab. 48. TIMING_CFG – communication timing Tab. 49. Data collection mode periods for oscillator Tab. 52. CK_CAL_EN and CK_CAL_RST oscillator Tab. 53. CHIPTIME – chip time and bit time register Tab. 56. BDM_CFG – DSI3 background diagnostic mode configuration register – (address Tab. 57. Background diagnostic command bits and Tab. 59. PSI5_CFG – PSI5 configuration register – Tab. 66. D33 through D48 of PSI5 initialization Tab. 67. PDCM_RSPSTx_x – DSI3 and PSI5 start time registers – (address $26 to $29) bit Tab. 68. Periodic data collection mode response start time for the associated data and Tab. 69. Default states for SOURCEID_x, FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

NXP Semiconductors FXPS71407 DSI3 and PSI5 compatible absolute and relative pressure sensor Tab. 72. PDCM_CMD_B_x – DSI3 and PSI55 command blocking time registers – Tab. 75. WHO_AM_I – who am I register – (address Tab. 77. DSP_CFG_U1 – DSP user configuration Tab. 79. DSP_CFG_U3 – DSP user configuration Tab. 82. DSP_CFG_U4 – DSP user configuration Tab. 86. DSP_CFG_U5 – DSP user configuration Tab. 88. INT_CFG – interrupt configuration register Tab. 91. P_CAL_ZERO_x – pressure calibration Tab. 92. DSP_STAT – DSP-specific status register – Tab. 94. DEVSTAT_COPY – device status copy Tab. 95. SNSDATA0_L, SNSDATA0_H – sensor data #0 registers – (address $62, $63) bit Tab. 96. SNSDATA0_L, SNSDATA0_H – sensor data #0 registers – (address $62, $63) bit Tab. 97. SNSDATA0_TIMEx – sensor data 0 timestamp – (address $66 to $69, $6A, Tab. 98. P_MAX_x – maximum absolute pressure value register – (address $6C, $6D) bit Tab. 99. P_MIN_x – maximum absolute pressure value register – (address $6E, $6F) bit Tab. 100. FRTx – free-running timer registers (address $78, $79, $7A to $7D) bit Tab. 101. ICTYPEID – IC type register – (address Tab. 102. ICREVID – IC manufacturer revision Tab. 103. ICMFGID – IC manufacturer identification Tab. 104. PNx – part number registers – (address Tab. 106. SNx – device serial number registers – Tab. 107. ASICWFR# – ASIC wafer ID register – Tab. 108. ASICWFR_x – ASIC wafer x, y coordinates ID registers – (address $CC, $CD) bit Tab. 109. ASICWLOT_x – ASIC wafer lot ID registers Tab. 110. USERDATA_X – user data registers (address $E0 to $E9, $EA to $EE) bit Tab. 111. Phase 2 USERDATA_X – user data registers (address $E0 to $E9, $EA to $EE) Tab. 112. USERDATA_10 to USERDATA_1E – user data registers (address $F0 to $F9, $FA to Tab. 113. CRC_UF2, CRC_F_A to CRC_F_F – lock and CRC registers – (address $5F, $AF to Tab. 114. Register block before and after Tab. 118. Registers verified by the ENDINIT Tab. 124. Low-pass filter details and timing for the Tab. 132. Command and response mode – command Tab. 133. Command and response mode – field Tab. 134. Command and response mode command Tab. 135. Command and response mode – CRC Tab. 137. Command and response mode – response Tab. 138. Command and response mode – field FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

NXP Semiconductors FXPS71407 DSI3 and PSI5 compatible absolute and relative pressure sensor Tab. 139. Command and response mode response Tab. 145. Global register write command – response Tab. 146. Enter periodic data collection mode Tab. 147. Enter periodic data collection mode Tab. 150. Periodic data collection mode status field Tab. 151. Periodic data collection mode response Tab. 152. Periodic data collection mode – CRC Tab. 154. DSI3 error handling – discovery mode and Tab. 157. PSI5 initialization phase 2 data Tab. 161. Daisy chain programming commands and Tab. 162. Daisy chain programming response code Tab. 169. Programming mode via PSI5 command Tab. 170. Programming mode via PSI5 XLong Tab. 171. Programming mode via PSI5 response Tab. 172. Programming mode via PSI5 short frame Tab. 173. Programming mode via PSI5 long frame Tab. 174. Programming mode via PSI5 extra long Tab. 175. Programming mode via PSI5 commands Tab. 176. Programming mode via PSI5 response Figures Fig. 5. VBUF capacitor monitor timing, PSI5 Fig. 6. VBUF capacitor monitor timing, PSI5 Fig. 8. Command and response mode oscillator Fig. 9. Periodic data collection mode oscillator Fig. 11. User-controlled PABS common mode self- Fig. 23. Temperature sensor signal chain block Fig. 24. Common mode error detection signal chain Fig. 25. Absolute pressure accuracy as a function Fig. 26. Absolute pressure accuracy multiplier over Fig. 28. DSI3 command receiver timing diagram: Fig. 29. DSI3 command receiver timing diagram: Fig. 31. Discovery mode current sense circuit block FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

NXP Semiconductors FXPS71407 DSI3 and PSI5 compatible absolute and relative pressure sensor Fig. 32. DSI3 discovery mode sensing timing Fig. 34. Command and response mode command Fig. 35. Command and response mode command Fig. 36. Command and response mode response Fig. 38. Command and response mode timing Fig. 39. Background diagnostic mode command bit Fig. 41. Periodic data collection mode timing Fig. 42. Background diagnostic mode timing Fig. 44. Synchronous sampling mode with minimum Fig. 52. Example Manchester encoded data Fig. 54. PSI5 initialization timing, synchronous Fig. 55. PSI5 initialization timing, asynchronous Fig. 57. Synchronous sampling mode with minimum Fig. 59. DSI3 switch connected daisy chain Fig. 60. PSI5 parallel or universal mode application Fig. 61. PSI5 daisy chain mode application diagram ..120 Fig. 63. Package outline detail HQFN Fig. 64. Package outline notes HQFN Fig. 65. SOT1573-2(SC) PCB design guidelines - Fig. 66. SOT1573-2(SC) PCB design guidelines - I/ Fig. 67. SOT1573-2(SC) PCB design guidelines - FXPS71407 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 3.4 — 29 November 2023

NXP Semiconductors FXPS71407 DSI3 and PSI5 compatible absolute and relative pressure sensor

6.6.5.2 Temperature sensor output scaling

6.7 Pressure sensor accuracy (drift over

11.1 Media compatibility – pressure sensors only ... 74

11.2.2.1 Address assignment method for parallel

11.2.2.2 Address assignment method for bus switch

11.2.2.3 DSI3 discovery mode: address assignment

method for resistor connected daisy chain

11.2.3.1 DSI3 command and response mode

11.2.3.2 DSI3 command and response mode

11.2.3.4 DSI3 command and response mode

11.2.4 DSI3 periodic data collection mode and

11.2.4.1 DSI3 periodic data collection mode and

background diagnostic mode command

11.2.4.2 DSI3 periodic data collection mode

11.2.4.4 Background diagnostic mode response

11.2.4.6 DSI3 periodic data collection mode and

background diagnostic mode command

11.2.6.3 Resistor connected daisy chain network

11.2.7.1 Daisy chain and discovery mode error

11.3.5.3 Synchronous sampling mode with minimum

11.3.8.3 PSI5 programming mode command and

11.3.8.4 Programming mode via PSI5 error

NXP Semiconductors FXPS71407 DSI3 and PSI5 compatible absolute and relative pressure sensor Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2023 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Date of release: 29 November 2023 Document identifier: FXPS71407

Product Information

FXPS7140P7 specifications and overview.

Summary

DSI3 and PSI5 compatible absolute and relative pressure sensor Rev. 3.4 - 29 November 2023

Description

DSI3 and PSI5 compatible absolute and relative pressure sensor Rev. 3.4 - 29 November 2023

Source title FXPS7140P7 Datasheet(PDF) - NXP Semiconductors

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