Sensor

FXPS7115D4S

NXP Semiconductors

Digital absolute pressure sensor, 40 kPa to 115 kPa Rev. 1.1 - 7 June 2023

Manufacturer: NXP Semiconductors

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PDF pages: 72

Technical content

Datasheet sections

1 General description
2 Features and benefits
3 Applications
3.1 Automotive
3.2 Industrial
3.3 Medical/Consumer
4 Ordering information
4.1 Ordering options
5 Block diagram
6 Pinning information
6.1 Pinning
6.2 Pin description
7 Functional description
7.1 Voltage regulators
7.1.1 VCC, VREG, VREGA, undervoltage
7.2 Internal oscillator
7.3 Pressure sensor signal path
7.3.1 Self-test functions
7.3.1.1 PABS common mode verification
7.3.1.2 Startup digital self-test verification
7.3.1.3 Startup sense data fixed value verification
7.3.3 Digital signal processor (DSP)
7.3.3.1 Decimation sinc filter
7.3.3.2 Signal trim and compensation
7.3.3.3 Low-pass filter
7.3.3.4 Absolute pressure output data scaling
7.3.4 Temperature sensor
7.3.4.1 Temperature sensor signal chain
7.3.4.2 Temperature sensor output scaling
7.3.5 Common mode error detection signal chain
7.4 Inter-integrated circuit (I2C) interface
7.4.1 I2C bit transmissions
7.4.2 I2C start condition
7.4.3 I2C byte transmission
7.4.4 I2C acknowledge and not acknowledge
7.4.5 I2C stop condition
7.4.6 I2C register transfers
7.4.6.1 Register write transfers
7.4.6.2 Register read transfers
7.4.6.3 Sensor data register read wrap around
7.4.7 I2C timing diagram
7.5 Standard 32-bit SPI protocol
7.5.1 SPI command format
7.5.2 SPI response format
7.5.3 Command summary
7.5.3.1 Register read command
7.5.3.2 Register write command
7.5.3.3 Sensor data request commands
7.5.3.4 Reserved commands
7.5.4 Error checking
7.5.4.1 Default 8-bit CRC
7.5.5 Exception handling
7.5.5.1 Basic status field
7.5.5.2 Detailed status field
7.5.5.3 SPI error
7.5.5.4 SPI data output verification error
7.5.6 SPI timing diagram
7.6 User-accessible data array
7.7 Register information
7.7.1 COUNT - rolling counter register (address
7.7.2 Device status registers
7.7.2.1 DEVSTAT - device status register (address
7.7.2.2 DEVSTAT1 - device status register
7.7.2.3 DEVSTAT2 - device status register
7.7.2.4 DEVSTAT3 - device status register
7.7.3 TEMPERATURE - temperature register
7.7.4 DEVLOCK_WR - lock register writes
7.7.5 WRITE_OTP_EN – write OTP enable
7.7.6 UF_REGION_W, UF_REGION_R - UF
7.7.7 SOURCEID_x - source identification
7.7.7.1 Data source enable bits (SIDx_EN)
7.7.8 SPI Configuration Control Register (SPI_
7.7.8.1 SPI Data Field Size (DATASIZE)
7.7.8.2 SPI CRC Length and Seed Bits
7.7.9 WHO_AM_I - who am I register (address
7.7.10 I2C_ADDRESS - I2C client address
7.7.11 DSP Configuration Registers (DSP_CFG_
7.7.11.1 Self-test control bits
7.7.11.2 DSP_CFG_U1 - DSP user configuration #1
7.7.11.3 DSP_CFG_U3 - DSP user configuration #3
7.7.11.4 DSP_CFG_U4 - DSP user configuration #4
7.7.11.5 DSP_CFG_U5 - DSP user configuration #5
7.7.12 INT_CFG - interrupt configuration register
7.7.13 P_INT_HI, P_INT_LO - interrupt window

Digital absolute pressure sensor, 40 kPa to 115 kPa Rev. 1.1 — 7 June 2023 Objective data sheet

1 General description

The FXPS7115D4S high-performance, high-precision barometric absolute pressure (BAP) sensor consists of a compact capacitive micro-electro-mechanical systems (MEMS) device coupled with a digital integrated circuit (IC) producing a fully calibrated digital output. The sensor is based on NXP's high-precision capacitive pressure cell technology. The architecture benefits from redundant pressure transducers as an expanded quality measure. This sensor delivers highly accurate pressure and temperature readings through either a serial peripheral interface (SPI) or an inter-integrated circuit (I2C) interface. Furthermore, the sensor employs an on-demand digital self-test for the digital IC and the MEMS transducers. The sensor operates over a pressure range of 40 kPa to 115 kPa and over a wide temperature range of −40 ºC to 130 ºC. The sensor comes in an industry-leading 4 mm x 4 mm x 1.98 mm, restriction of hazardous substances (RoHS) compliant, high power quad flat no lead (HQFN) package[1] suitable for small PCB integration. Its AEC-Q100[2] compliance, high accuracy, reliable performance, and high media resistivity make it ideal for use in automotive, industrial, and consumer applications.

2 Features and benefits

Absolute pressure range: 40 kPa to 115 kPa
Operating temperature range: –40 °C to 130 °C
Pressure transducer and digital signal processor (DSP) – Digital self-test
I2C compatible serial interface – Client mode operation – Standard mode, Fast mode, and Fast-mode Plus support
32-bit SPI compatible serial interface – Sensor data transmission commands – 12-bit data for absolute pressure – 8-bit data for temperature – 2-bit basic status and 2-bit detailed status fields – 3, 4, or 8-bit configurable CRC
Capacitance to voltage converter with anti-aliasing filter
Sigma delta ADC plus sinc filter
800 Hz or 1000 Hz low-pass filter for absolute pressure
Lead-free, 16-pin HQFN, 4 mm x 4 mm x 1.98 mm package

3 Applications

3.1 Automotive

Engine management digital MAP and BAP
Small engine control

3.2 Industrial

Compressed air
Manufacturing line control
Gas metering
Weather stations

3.3 Medical/Consumer

Blood pressure monitor
Medicine dispensing systems
White goods

4 Ordering information

Table 1. Ordering information

4.1 Ordering options

Table 2. Ordering options [1] Product under development, consult your NXP sales representatives for samples. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

5 Block diagram

Figure 1. Block diagram of FXPS7115D4S

6 Pinning information

6.1 Pinning

17 TEST6

6.2 Pin description

3 INT Interrupt output

unterminated. Optionally, pin 3 can be tied to VSS. 2, 12 TESTx Test pin. NXP recommends pins 2, and 12 be unterminated. Optionally, these pins can be tied to VSS. 5 TESTx Test pin. NXP recommends pin 5 be tied to VCC. Optionally, this pin can be tied to VSS.

8 SS_B Client / Device select

pull-up resistor, as shown in the application diagram.

10 MOSI SPI data in

11 MISO/SDA SPI/I2C data out

external pull-up resistor, as shown in the application diagram. In SPI mode, pin 11 functions as the serial data output.

13 VCCIO I/O supply

Pin 13 must be connected to VCC, the device supply.

17 PAD Die attach pad

Pin 17 is the die attach flag, and must be connected to VSS. Table 3. Pin description

7 Functional description

7.1 Voltage regulators

for VCC, as shown in Figure 25 and Figure 26. A reference generator provides a reference voltage for the ΣΔ converter. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Figure 3. Voltage regulation and monitoring

7.1.1 VCC, VREG, VREGA, undervoltage monitor

transactions are terminated. Once the supply returns above the threshold, the device resumes responses.

7.2 Internal oscillator

The device includes a factory trimmed oscillator.

7.3 Pressure sensor signal path

7.3.1 Self-test functions

register. The ST_CTRL bits select the desired self-test connection. disabled until a device reset. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

7.3.1.1 PABS common mode verification

Figure 4. User-controlled PABS common mode self-test flowchart

7.3.1.2 Startup digital self-test verification

Table 4. The digital self-test values result in a constant value at the output of the signal chain. After a specified bit is set. These signals can only be selected when the ENDINIT bit is not set. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 4. Self-test control register

7.3.1.3 Startup sense data fixed value verification

selected when the ENDINIT bit is not set. Table 5. Self-test control bits for sense data fixed value verification input to the DSP. A simplified block diagram is shown in Figure 5. Figure 5. ΣΔ converter block diagram The sigma delta modulator operates at a frequency of 1 MHz, with the transfer function in Equation 1. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

7.3.3 Digital signal processor (DSP)

within the DSP is shown in Figure 6. Figure 6. Signal chain diagram

7.3.3.1 Decimation sinc filter

sinc filters; the first with a decimation ratio of 24 and the second with a decimation ratio of 4. Figure 7. Sinc filter response

7.3.3.2 Signal trim and compensation

The device includes digital trim to compensate for sensor offset, sensitivity, and nonlinearity over temperature.

7.3.3.3 Low-pass filter

1000 Hz (dB)

Table 6. IIR low pass filter coefficients Figure 8. 800 Hz, 4-pole, low-pass filter response FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Figure 11. 1000 Hz, 4-pole output signal delay

7.3.3.4 Absolute pressure output data scaling equation

specified values apply only if the P_CAL_ZERO value is set to 0000h. PABSkPa = The absolute pressure output in kPa. PABSLSB = The absolute pressure output in LSB. PABSOFFLSB = The internal trimmed absolute pressure output value at 0 kPa in LSB. PABSSENSE = The trimmed absolute pressure sensitivity in LSB/kPa. Table 7. Scaling parameters

7.3.4 Temperature sensor

7.3.4.1 Temperature sensor signal chain

simplified block diagram. Temperature sensor parameters are specified in Table 104 and Table 105. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Figure 12. Temperature sensor signal chain block diagram

7.3.4.2 Temperature sensor output scaling equation

Equation 5 is used to convert temperature readings with the variables specified in Table 8. Table 8. Temperature conversion variables

7.3.5 Common mode error detection signal chain

"DSP_STAT - DSP specific status register (address 60h)". Figure 13. Common mode error detection signal chain block diagram

7.4 Inter-integrated circuit (I2C) interface

resistor values and the total bus capacitance.

7.4.1 I2C bit transmissions

host, the bus is considered busy. Timing for the start condition is specified in Table 105. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Figure 14. I2C bit transmissions

7.4.2 I2C start condition

the host, the bus is considered busy. Timing for the start condition is specified in Table 105. A start condition (START) and a repeat START condition (rSTART) are identical. Figure 15. I2C start condition

7.4.3 I2C byte transmission

functions for this device are completed within the acknowledge clock pulse. Clock stretching is not used. Figure 16. I2C byte transmissions FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

7.4.4 I2C acknowledge and not acknowledge transmissions

clock pulse. Set up and hold times as specified in Table 105 must also be taken into account.

No receiver is present on the bus with the transmitted address.
The addressed receiver is unable to receive or transmit because it is performing some real-time function

and is not ready to start communication with the host.

The receiver receives unrecognized data or commands.
The receiver cannot receive any more data bytes.
The host-receiver signals the end of the transfer to the client transmitter.

An example ACK and NACK are shown in Figure 17. Figure 17. I2C acknowledge and not acknowledge transmission

7.4.5 I2C stop condition

host, the bus is considered free. Timing for the stop condition is specified in Table 105. Figure 18. I2C stop condition

7.4.6 I2C register transfers

7.4.6.1 Register write transfers

The host transmits a START condition.

NXP Semiconductors FXPS7115D4S Digital absolute pressure sensor, 40 kPa to 115 kPa 2. The host transmits the 7-bit client address. 3. The host transmits a '0' for the read/write bit to indicate a write operation. 4. The client transmits an ACK. 5. The host transmits the register address to be written. 6. The client transmits an ACK. 7. The host transmits the data byte to be written to the register address. 8. The client transmits an ACK. 9. The host transmits a STOP condition. CLIENT ADDRESS Host transmission Client transmission REGISTER DATAREGISTER ADDRESS AAWS A P aaa-029920 The device automatically increments the register address allowing for multiple register writes to be completed in one transaction. In this case, the register write data transfers are constructed as follows: 1. The host transmits a START condition. 2. The host transmits the 7-bit client address. 3. The host transmits a '0' for the read/write bit to indicate a write operation. 4. The client transmits an ACK. 5. The host transmits the register address to be written. 6. The client transmits an ACK. 7. The host transmits the data byte to be written to the register address. 8. The client transmits an ACK. 9. The host transmits the data byte to be written to the register address +1. 10. The client transmits an ACK. 11. Repeat steps 9 and 10 until all registers are written. 12. The host transmits a STOP condition.

7.4.6.2 Register read transfers

The device supports I2C register read data transfers. Register read data transfers are constructed as follows: 1. The host transmits a START condition. 2. The host transmits the 7-bit client address. 3. The host transmits a '0' for the read/write bit to indicate a write operation. 4. The client transmits an ACK. 5. The host transmits the register address to be read. 6. The client transmits an ACK. 7. The host transmits a repeat START condition. 8. The host transmits the 7-bit client address. 9. The host transmits a '1' for the read/write bit to indicate a read operation. 10. The client transmits an ACK. 11. The client transmits the data from the register addressed. 12. The host transmits a NACK. 13. The host transmits a STOP condition. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Objective data sheet Rev. 1.1 — 7 June 2023

7.4.6.3 Sensor data register read wrap around

DEVSTAT_COPY register as shown in Table 9. Table 9. Sensor data register read wrap-around description

7.4.7 I2C timing diagram

7.5 Standard 32-bit SPI protocol

client device. MOSI and SCLK transitions are ignored when SS_B is not asserted. Figure 20. Standard 32 Bit SPI protocol timing diagram

7.5.1 SPI command format

7.5.2 SPI response format

Table 12. SPI response format

7.5.3 Command summary

7.5.3.1 Register read command

addresses defined in Section 7.6 "User-accessible data array" to address 8-bit registers in the register map.

No SPI error is detected (see Section 7.5.5.3 "SPI error" )
No MISO error is detected (see Section 7.5.5.4 "SPI data output verification error") If these conditions are met, the device responds to the register read request as shown in Section 7.5.3.1.2 "Register read response message format". Otherwise, the device responds with the error response as defined in Section 7.5.5.2 "Detailed status field". The register read response includes the register contents at the rising edge of SS_B for the register read command. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Objective data sheet Rev. 1.1 — 7 June 2023

7.5.3.1.1 Register read command message format

Table 13. Register read command message format RA[7:0] RA[7:1] contains the word address of the register to be read. Table 14. Register read command message bit field descriptions

7.5.3.1.2 Register read response message format

Table 15. Register read response message format Table 16. Register read response message bit field descriptions

7.5.3.2 Register write command

RD[7:0] to the register addressed by RA[7:0].

No SPI error is detected (see Section 7.5.5.3 "SPI error")
No MISO error is detected (see Section 7.5.5.4 "SPI data output verification error")
The ENDINIT bit is cleared. – This applies to all registers except for the RESET[1:0] bits in the DEVLOCK_WR register
No invalid register request is detected as described below. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Objective data sheet Rev. 1.1 — 7 June 2023

not written until the transfer during which the register write was requested has been completed. A register write command to a read-only register is not executable, but results in a valid response.

7.5.3.2.1 Register write command message format

Table 17. Register write command message format Table 18. Register write command message bit field descriptions

7.5.3.2.2 Register write response message format

Table 19. Register write response message format Table 20. Register write response message bit field descriptions

7.5.3.3 Sensor data request commands

for the sensor data request response.

7.5.3.3.1 Sensor data request command message format

Table 21. Sensor data request command message format Table 22. Sensor data request command message bit field descriptions

7.5.3.3.2 Sensor data request response message format

Table 23. Sensor data request response message format – 12 bit data length Table 24. Sensor data request response message bit field descriptions

7.5.3.4 Reserved commands

7.5.3.4.1 Reserved command message format

Table 25. Reserved command message format Table 26. Reserved command message bit field descriptions

7.5.3.4.2 Reserved command response message format

Table 27. Reserved command response message format Table 28. Reserved command response message bit field descriptions

7.5.4 Error checking

7.5.4.1 Default 8-bit CRC

7.5.4.1.1 Command error checking

not match the transmitted CRC, the command is ignored and the device responds with the SPI error response.

A seed value is preset into the LSB of the shift register.
Using a serial CRC calculation method, the receiver rotates the received message and CRC into the LSB of

When the calculation on the last bit of the CRC is rotated into the shift register, the shift register contains the
If the shift register contains all zeros, the CRC is correct.
If the shift register contains a value other than zero, the CRC is incorrect.

The CRC polynomial and seed are shown in Table 29. Table 29. SPI Command Message CRC

7.5.4.1.2 Response error checking

calculator MSB first, consistent with the transmission order of the message.

A seed value is preset into the LSB of the shift register.
Using a serial CRC calculation method, the transmitter rotates the transmitted message and CRC into the

LSB of the shift register (MSB first).

Following the transmitted message, the transmitter feeds 8 zeros into the shift register, to match the length
When the last zero is fed into the input adder, the shift register contains the CRC.

The CRC polynomial and seed are shown in Table 30. Table 30. SPI Response Message CRC

7.5.5 Exception handling

Table 31. Expected initial responses after tPOR_DataValid post POR XXXX due to DEVINIT bit still set to 1. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

response from the first 5 commands are shown in Table 32. Table 32. Expected initial responses after tPOR_DataValid post soft reset be 0x6081XXXX due to DEVINIT bit still set to 1.

7.5.5.1 Basic status field

SS_B for the previous SPI command. Table 33. Basic status field for responses to register commands

7.5.5.2 Detailed status field

status field is a representation of the device status at the rising edge of SS_B for the previous SPI command. Table 34. Detailed status bit field descriptions

7.5.5.3 SPI error

SCLK is high when SS_B is asserted. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Objective data sheet Rev. 1.1 — 7 June 2023

The number of SCLK rising edges detected while SS_B is asserted is not equal to 16.
SCLK is high when SS_B is deasserted.
CRC error is detected (MOSI).
A register write command to any register other than the DEVLOCK_WR register is received while ENDINIT is set. If a SPI error is detected, the device responds with the error response as described in Section 7.5.5.2 "Detailed status field" with the detailed status field set to “SPI Error” as defined in Section 7.5.5.1 "Basic status field".

7.5.5.4 SPI data output verification error

SPI MISO mismatch fault is detected and the MISO_ERR flag in the DEVSTAT2 register is set. during the subsequent SPI message. Section 7.5.5.1 "Basic status field" during the subsequent SPI message. field", during the subsequent SPI message. Figure 21. SPI data output verification FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

7.5.6 SPI timing diagram

Figure 22. SPI timing diagram

7.6 User-accessible data array

than the nominal supply as shown in Table 103. See application note AN12727[3]. Table 35. User-accessible data — sensor specific information FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

[2] Useful for I2C read wrap around mode to support temperature data. See Table 9 and Table 67. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

7.7 Register information

7.7.1 COUNT - rolling counter register (address 00h)

value in the register increases by one count every 100 μs and the counter rolls over every 25.6 ms. Table 36. COUNT - rolling counter register (address 00h) bit allocation

7.7.2 Device status registers

readable in SPI or I2C mode.

7.7.2.1 DEVSTAT - device status register (address 01h)

Table 37. DEVSTAT - device status register (address 01h) bit allocation

7 DSP_ERR The DSP error flag is set if a DSP-specific error is present in the pressure signal DSP:

5 COMM_ERR The communication error flag is set if any bit in DEVSTAT3 is set:

4 MEMTEMP_ERR The memory error flag is set if any bit in DEVSTAT2 is set:

a test mode operation or by a power cycle. Table 38. DEVSTAT - device status register (address 01h) bit description FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

is valid for read through one of the device communication interfaces (tPOR_DataValid). Table 38. DEVSTAT - device status register (address 01h) bit description...continued [1] See Section 7.7.4 bit 3, supply error reporting disable bit (SUP_ERR_DIS). [2] After POR and/or soft reset, see Section 7.5.5 for initialization sequence.

7.7.2.2 DEVSTAT1 - device status register (address 02h)

Table 39. DEVSTAT1 - device status register (address 02h) bit allocation [1] During POR and soft reset ignore DEVSTAT1 error flags, refer to Section 7.5.5. on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in Section 7.7.4. Table 104. See Section 7.1 for details on the VCC undervoltage monitor. regulator voltage falls outside expected limits. voltage falls outside expected limits. voltage falls outside expected limits.

0 CONT_ERR The continuity monitor passes a low current through a connection around the perimeter of

is detected in the connection. Table 40. DEVSTAT1 - device status register (address 02h) bit description FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 40. DEVSTAT1 - device status register (address 02h) bit description...continued [1] During POR and soft reset ignore DEVSTAT1 error flags, refer to Section 7.5.5. on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in Section 7.7.4.

7.7.2.3 DEVSTAT2 - device status register (address 03h)

Table 41. DEVSTAT2 - device status register (address 03h) bit allocation 7 F_OTP_ERR The NXP factory OTP array error bit is set if a fault is detected in the factory OTP array. interface or on a data transmission that includes the error in the status field. data transmission that includes the error in the status field. 4 U_W_ACTIVE The user OTP write in process status bit is set if a user initiated write to OTP is in process. The U_W_ACTIVE bit is automatically cleared once the write to OTP is complete.

2 TEMP0_ERR The temperature error bit is set if an overtemperature or undertemperature condition

Table 42. DEVSTAT2 - device status register (address 03h) bit description FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

7.7.2.4 DEVSTAT3 - device status register (address 04h)

Table 43. DEVSTAT3 - device status register (address 04h) bit allocation

7 MISO_ERR In SPI mode, the MISO data mismatch flag is set when a MISO Data mismatch fault

Table 44. DEVSTAT3 - device status register (address 04h) bit description

7.7.3 TEMPERATURE - temperature register (address 0Eh)

value is specified in the temperature sensor signal chain section of Table 104. Table 45. TEMPERATURE - temperature register (address 0Eh) bit allocation

7.7.4 DEVLOCK_WR - lock register writes register (address 10h)

The lock register writes register is a read/write register that contains the ENDINIT bit and reset control bits. Table 46. DEVLOCK_WR - lock register writes register (address 10h) bit allocation FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

7 ENDINIT The ENDINIT bit is a control bit used to indicate that the user has completed all device and

An error detection is enabled for all user writable registers. The error detection code is continuously calculated on the user writable registers and verified against a previously calculated error detection code.
Self-test is disabled and inhibited.
Register writes are inhibited except for the RESET[1:0] bits in the DEVLOCK_WR register. 3 SUP_ERR_DIS The supply error disable bit allows the user to disable reporting of the supply errors in the SPI status fields. In SPI Mode:
0: No Response until the supply monitor timer expires. The Sensor Data Field Error Code is transmitted for one response after the supply monitor timer expires. All supply errors are cleared by a read of the DEVSTAT1 register through any communication interface or on a data transmission that includes the error in the status field if and only if the timer has reached zero.
1: No Responses occur if the timer is non-zero. The error is cleared when the timer reaches zero and normal transmissions resume. In I2C Mode (0 or 1):
No response until the supply monitor timer expires.
All supply errors are cleared by a read of the DEVSTAT1 register. 1 to 0 RESET[1:0] To reset the device, three consecutive register write operations must be performed in the order shown in Table 48, or the device will not reset.[1]

Table 47. DEVLOCK_WR - lock register writes register (address 10h) bit description [1] After POR and/or soft reset, see Section 7.5.5 for initialization sequence. Table 48. Device reset command sequence

7.7.5 WRITE_OTP_EN – write OTP enable register (address 11h)

the user read/write array error detection. This register is readable and writable in SPI and I2C modes. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 49. WRITE_OTP_EN – write OTP enable register – (address 11h) bit allocation OTP is written to as shown in Table 50. Table 50. Writes for OTP registers register write commands, but no new values can be written to the OTP.

Read the appropriate CRC_UFx register and confirm the LOCK_Uxx bit is not set.
Write the desired values to the user array registers for only the region to be written using the procedures in

Section 7.7.6 "UF_REGION_W, UF_REGION_R - UF region selection registers (address 14h, 15h)" . register block remains in the shared registers and is written to OTP if the Write OTP sequence is completed.

Execute a write to the WRITE_OTP_EN register with the appropriate bits set for the desired region to

UOTP_WR_INIT bit remains set.

Delay 10 ms to allow the device to complete the writes to OTP.
Verify that the OTP write has successfully completed by reading back all of the OTP registers using register

registers (address 14h, 15h)".

Repeat steps 1 through 4 for all regions to be programmed.
Read the CRC_UF2 register and confirm the LOCK_UF2 bit is not set.
Write the desired values to the user array registers.

Execute a write to the WRITE_OTP_EN register with region 2 selected and the EX_COMMTYPE and

EX_PADDR bits set as shown in Table 50. UOTP_WR_INIT bit remains set.

Delay 10 ms to allow the device to complete the writes to OTP.
Verify that the OTP write successfully completed by reading back all of the OTP registers using register read

7.7.6 UF_REGION_W, UF_REGION_R - UF region selection registers (address 14h, 15h)

active register is a read-only register that contains the status bits for the UF0 and UF1 regions to be accessed. This register is included in the user read/write array error detection. readable in SPI mode or I2C mode. Table 51. UF_REGION_W - UF region selection register (address 14h) bit allocation Table 52. UF_REGION_R - UF region selection register (address 15h) bit allocation registers. Below is the necessary procedure to ensure proper reading of the UF0, UF1, and F registers.

Write the desired address range to be read to the REGION_LOAD[3:0] bits in the UF_REGION_W register.

Add a delay of minimum 50 µs.
Optional: Execute a register read of the UF_REGION_R register and confirm the REGION_ACTIVE[3:0] bits

match the values written to the REGION_LOAD[3:0] bits in the UF_REGION_W register. Table 54. REGION_ACTIVE Bit Definitions

Execute a Register Read of the desired registers from the UF0, UF1 or F register section. Complete all

desired Register Reads of the selected UF Region.

Repeat steps 1 through 4 for the next desired UF region to read.

The user must take care to ensure that the desired registers are addressed. For example, if the REGION_LOAD bits are set to Ah and the user executes a read of address C2h, the contents of registers A2h is transmitted. No error detection is included other than a read of the REGION_ACTIVE bits.
In SPI and I2C modes, once the ENDINIT bit is set, writes to registers other than the RESET[1:0] bits are inhibited. For this reason, reads of the UF0, UF1, and F registers are only possible for the region selected by the REGION_ACTIVE bits at the time ENDINIT is set.

7.7.7 SOURCEID_x - source identification registers (address 1Ah, 1Bh)

identification information used in SPI Mode. These registers are included in the read/write array error detection. Table 55. SOURCEID_0 - source identification register (address 1Ah) bit allocation Table 56. SOURCEID_1 - source identification register (address 1Bh) bit allocation FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

7.7.7.1 Data source enable bits (SIDx_EN)

the SOURCEID_x channels. SPI error responses are detailed in Section 7.5.4 "Error checking".

0 SPI error responseSOURCEID_0

1 SNSDATA0

0 SPI error responseSOURCEID_1

1 SNSDATA1

Table 57. Source ID enable Table 11, for details regarding the effect of the SIDx_EN bits.

7.7.8 SPI Configuration Control Register (SPI_CFG, Address 3Dh)

Table 58. SPI_CFG Register (address 3Dh) bit allocation

7.7.8.1 SPI Data Field Size (DATASIZE)

The SPI data field size bit controls the size of the SPI data field as shown in Table 59. Table 59. DATASIZE Bit Definition

7.7.8.2 SPI CRC Length and Seed Bits

shown in the table. The new seed value is enabled for both MISO and MOSI on the next SPI Mode command. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 60. SPI CRC Definition

7.7.9 WHO_AM_I - who am I register (address 3Eh)

The WHO_AM_I register is a user programmed read/write register that contains the unique product identifier. This register is included in the read/write array error detection. Table 61. WHO_AM_I - device identification register (address 3Eh) bit allocation command. For all other register values, the actual register value is transmitted in response to a read command. Table 62. WHO_AM_I register values

7.7.10 I2C_ADDRESS - I2C client address register (address 3Fh)

address. The register is readable in all modes. This register is included in the read/write array error detection. Table 63. I2C_ADDRESS - I2C client address register (address 3Fh) bit allocation

7.7.11 DSP Configuration Registers (DSP_CFG_Ux)

The DSP Configuration registers (DSP_CFG_Ux) are a series of registers that affect the DSP data path. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

7.7.11.1 Self-test control bits

included in the read/write array error detection.

7.7.11.2 DSP_CFG_U1 - DSP user configuration #1 register (address 40h)

configuration information. This register is included in the read/write array error detection. sensor data requests should be prevented during this time. Table 64. DSP_CFG_U1 - DSP user configuration #1 register (address 40h) bit allocation Table 65. Low-pass filter selection bits (LPF[3:0]) [2] In case of POR, filter reverts to the default. Note: Using values other than those listed in Table 65 causes an error in the DEVSTAT.

7.7.11.3 DSP_CFG_U3 - DSP user configuration #3 register (address 42h)

configuration information. This register is included in the read/write array error detection. be prevented during this time. This register is readable and writeable in SPI mode, and I2C mode. Table 66. DSP_CFG_U3 - DSP user configuration #3 register (address 42h) bit allocation FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

7.7.11.3.1 DSP data type 0 selection bits (DATATYPE0)

Table 67. DATATYPE0[1:0]

7.7.11.3.2 DSP data type 1 selection bits (DATATYPE1)

Table 68. DATATYPE1[1:0]

7.7.11.4 DSP_CFG_U4 - DSP user configuration #4 register (address 43h)

configuration information. This register is included in the read/write array error detection. Table 69. DSP_CFG_U4 - DSP user configuration #4 register (address 43h) bit allocation 2 INT_OUT The interrupt pin configuration bit selects the mode of operation for the interrupt pin. Table 70. DSP_CFG_U4 - DSP user configuration #4 register (address 43h) bit description

7.7.11.5 DSP_CFG_U5 - DSP user configuration #5 register (address 44h)

information. This register is included in the read/write array error detection. Table 71. DSP_CFG_U5 - DSP user configuration #5 register (address 44h) bit allocation FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 73. The self-test control bits are not included in the read/write array error detection. 3 to 0 reserved These bits are reserved. Table 72. DSP_CFG_U5 - DSP user configuration #5 register (address 44h) bit description Table 73. Self-test control bits (ST_CTRL[3:0])

7.7.12 INT_CFG - interrupt configuration register (address 45h)

lock register writes register (address 10h)"). The register is included in the read/write array error detection. Table 74. INT_CFG - interrupt configuration register (address 45h) bit allocation FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

from the internal oscillator, so the tolerance on this oscillator applies. exist after the most recent evaluated sample. timer is zero, the interrupt pin is deasserted. The pulse stretch counter continuously decrements until it reaches zero. the most recent evaluated sample. programmed for activation either within or outside a window. Table 75. INT_CFG - interrupt configuration register (address 45h) bit description

7.7.13 P_INT_HI, P_INT_LO - interrupt window comparator threshold registers (address 46h to

10h)"). The register is included in the read/write array error detection. Table 76. P_INT_HI, P_INT_LO - interrupt window comparator threshold registers (address 46h to 49h) bit If either the high or low threshold is programmed to 0000h, comparisons are disabled for that threshold only. programmed to 0000h, the interrupt output is disabled.

7.7.14 P_CAL_ZERO - pressure calibration registers (address 4Ch, 4Dh)

SNSDATA_x registers and sensor data requests should be prevented during this time. Table 77. P_CAL_ZERO - pressure calibration registers (address 4Ch, 4Dh) bit allocation output range or a railed output.

7.7.15 DSP_STAT - DSP specific status register (address 60h)

The DSP status register is a read-only register that contains sensor data-specific status information. Table 78. DSP_STAT - DSP-specific status register (address 60h) bit allocation 0 — An analog or digital self-test has been activated since the last reset. 1 — No analog or digital self-test has been activated since the last reset. interface or on a data transmission that includes the error in the status field. Table 79. DSP_STAT - DSP-specific status register (address 60h) bit description

7.7.16 DEVSTAT_COPY - device status copy register (address 61h)

as a read of the DEVSTAT register. Table 80. DEVSTAT_COPY - device status copy register (address 61h) bit allocation For bit descriptions, see Table 38.

7.7.17 SNSDATA0_L, SNSDATA0_H - sensor data #0 registers (address 62h, 63h)

"Absolute pressure output data scaling equation" for details regarding the 16-bit sensor data. sequence, SNSDATA0_L register first, followed by the SNSDATA0_H register. Table 81. SNSDATA0_L, SNSDATA0_H - sensor data #0 registers (addresses 62h, 63h) bit allocation

7.7.18 SNSDATA1_L, SNSDATA1_H - sensor data #1 registers (address 64h, 65h)

temperature can be selected to be put into this register. See Table 9 and Table 67. sequence, SNSDATA1_L register first, followed by the SNSDATA1_H register. Table 82. SNSDATA1_L, SNSDATA1_H - sensor data #1 registers (address 64h, 65h) bit allocation

7.7.19 SNSDATA0_TIMEx - timestamp registers (address 66h to 6Bh)

The sensor data 0 timestamp registers are read-only registers that contain a 48-bit timestamp. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

register value transmission for a register read of the SNSDATA0_L register. data register read wrap-around mode as documented in Table 9. The sensor data 0 timestamp registers are read-only registers that contain a 48-bit timestamp. sensor data 0 data is latched for transmission via SPI. Table 83. SNSDATA0_TIMEx - timestamp register (address 66h to 6Bh) bit allocation

7.7.20 P_MAX, P_MIN - maximum and minimum absolute pressure value registers (address

0000h on a write to a DSP_CFG_U1 register that changes the value of the LPF[2:0] or ST_CTRL[3:0]. as the instantaneous pressure value obtained from the SNSDATA_x registers. always required to read the registers in sequence, P_xxx_L register first, followed by the P_xxx_H register. Table 84. P_Max and P_Min registers (address 6Ch to 6Fh) bit allocation

7.7.21 FRT - free running timer registers (addresses 78h to 7Dh)

timer is clocked by the main oscillator frequency and increments every 100 ns. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 85. FRT - free running timer registers (addresses 78h to 7Dh) bit allocation

7.7.22 IC type register (Address C0h)

or I2C mode when ENDINIT is not set. Table 86. IC TYPE REGISTER (ICTYPEID address C0h) bit allocation

7.7.23 IC manufacturer revision register (Address C1h)

The IC manufacturer revision register is a factory programmable OTP register that contains the IC revision. mode when ENDINIT is not set. Table 87. IC MANUFACTURER REVISION REGISTER (ICREVID address C1h) bit allocation

7.7.24 IC manufacturer identification register (address C2h)

readable in SPI mode or I2C mode when ENDINIT is not set. Table 88. IC MANUFACTURER IDENTIFICATION REGISTER (ICMFGID address C2h) bit allocation FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

7.7.25 Part number register (address C4h, C5h)

are readable in SPI mode or I2C mode when ENDINIT is not set. Table 89. PN0 Register (address C4h) bit allocation Table 90. PN1 Register (address C5h) bit allocation

7.7.26 Device serial number registers

might not be assigned. These registers are included in the factory programmed OTP array error detection. These registers are readable in SPI mode or I2C mode when ENDINIT is not set. Table 91. SN0 Register (address C6h) bit allocation Table 92. SN1 Register (address C7h) bit allocation Table 93. SN2 Register (address C8h) bit allocation FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 94. SN3 Register (address C9h) bit allocation Table 95. SN4 Register (address CAh) bit allocation

7.7.27 ASIC wafer ID registers

Table 96. ASICWFR# Register (address CBh) bit allocation Table 97. ASICWFR_X Register (address CCh) bit allocation Table 98. ASICWFR_Y Register (address CDh) bit allocation Table 99. ASICWLOT_L Register (address D0h) bit allocation FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 100. ASICWLOT_H Register (address D1h) bit allocation

7.7.28 USERDATA_0 to USERDATA_E - user data registers

writable in SPI mode or I2C mode when ENDINIT is not set.

7.7.29 USERDATA_10 to USERDATA_1E - user data registers

writable in SPI mode or I2C mode when ENDINIT is not set.

7.7.30 Lock and CRC Registers

when the corresponding data array is programmed to OTP using the Write OTP Enable register. Table 101. Lock and CRC Register bit definitions

7.7.31 Reserved registers

data for reserved bits may be '0' or '1'. normal device operation and performance. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

7.7.32 Invalid register addresses

data array" results in a valid response. The data for the registers are '00h'. data array" is not executable, but results in a valid response. The data for the registers are '00h'. the registers is the current content of the registers.

7.8 Read/write register array CRC verification

polynomial of g(x) = X4 + X3 + 1, with a seed value = '0000'.

8 Maximum ratings

it. Absolute maximum ratings are stress ratings only; functional operation at these ratings is not guaranteed. Exposure to absolute maximum ratings conditions for extended periods might affect device reliability. voltages to this high-impedance circuit. Table 102. Maximum ratings [1] Parameter verified by parametric and functional validation. [2] Parameter verified by qualification testing (Per AEC-Q100 Rev H or per NXP specification). [3] Functionality verified by modeling, simulation and/or design verification. [5] CDM tested at ±750 V for corner pins and ±500 V for all other pins. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

This device is sensitive to mechanical shock. Improper handling can cause permanent damage to the part. This is an ESD sensitive device. Improper handling can cause permanent damage to the part.

9 Operating range

VCC_min ≤ (VCC - VSS) ≤ VCC_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified. TA VCC = 5.0 V, unless otherwise stated. Table 103. Electrical characteristics — supply and I/O [1] Parameter tested at final test. [2] Parameter verified by parametric and functional validation.

10 Static characteristics

VCC_min ≤ (VCC - VSS) ≤ VCC_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified. Table 104. Static characteristics FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

VCC_min ≤ (VCC - VSS) ≤ VCC_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified. Table 104. Static characteristics...continued [1] Parameter verified by pass/fail testing at final test. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

[2] Functionality verified by modeling, simulation and/or design verification. [3] Parameter verified by functional validation. [4] Parameter verified by characterization. [5] Parameter tested at final test. [6] See Section 13 for accuracy over temperature and life, including nonlinearity, full scale = PABS range. [7] Parameter does not include lifetime drift. For complete pressure drift over temperature and life, review Section 13.

11 Dynamic characteristics

VCC_min ≤ (VCC – VSS) ≤ VCC_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified. Table 105. Dynamic characteristics FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

VCC_min ≤ (VCC – VSS) ≤ VCC_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified. Table 105. Dynamic characteristics...continued FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

VCC_min ≤ (VCC – VSS) ≤ VCC_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified. [1] Parameter verified by characterization. [2] Parameter verified by functional evaluation. [4] Functionality verified by modeling, simulation and/or design verification.

12 Media compatibility—pressure sensors only

For more information regarding media compatibility information, contact your local sales representative.

13 Pressure sensor accuracy (drift over temperature and life)

The absolute pressure accuracy is specified in Figure 23 and Figure 24. drift over temperature is guaranteed by production testing. Figure 24 have been obtained by qualification testing to conform to the AEC-Q100[2] (Rev-H) standards. for lifetime performance is (1 kPa × multiplying factor) = 2 kPa. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Figure 23. Absolute pressure accuracy as a function of temperature Figure 24. Absolute pressure accuracy multiplier over life Figure 26 show the modes and their respective biasing and bypass components. molecules may collect, form bubbles and possibly result in delamination of the gel from the material it protects. listed in the data sheet. In rare cases, the bubble may bend the bond wires and result in a permanent shift. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

16 Soldering

Figure 31. SOT1573-1 PCB design guidelines - I/O pads and solderable area FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

17 Mounting recommendations

A plugged port exhibits no change in pressure and can be cross checked in the user software. Refer to NXP application note AN1902[1] for proper printed circuit board attributes and recommendations.

18 References

Modifications: • This document has been reformatted to conform to NXP style guidelines.

Section 7.7.9, Table 61, Factory default (read value): revised bit 5 from "1" to "0".
Section 10, Table 104, revised as follows: – PSENS, revised typ value from "46.64" to "46.67". – PABS_DRng: removed row with the condition "Digitial, 12 bit". – POFF_D12: Inserted POFF_D16; added "12-bit (SPI)" and "16-bit (i2C, SPI)" to the paramter field; and added "29270" to the typ field. FXPS7115D4S v.1 20220809 Objective data sheet — —

NXP Semiconductors FXPS7115D4S Digital absolute pressure sensor, 40 kPa to 115 kPa

20 Legal information

20.1 Data sheet status

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

20.2 Definitions

Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

20.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Objective data sheet Rev. 1.1 — 7 June 2023

NXP Semiconductors FXPS7115D4S Digital absolute pressure sensor, 40 kPa to 115 kPa Suitability for use in automotive applications — This NXP product has been qualified for use in automotive applications. If this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as “Critical Applications”), then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer. Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to customer’s incorporation of any product in a Critical Application. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products.

20.4 Trademarks

Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Objective data sheet Rev. 1.1 — 7 June 2023

NXP Semiconductors FXPS7115D4S Digital absolute pressure sensor, 40 kPa to 115 kPa Tables Tab. 5. Self-test control bits for sense data fixed Tab. 9. Sensor data register read wrap-around Tab. 14. Register read command message bit field Tab. 16. Register read response message bit field Tab. 18. Register write command message bit field Tab. 20. Register write response message bit field Tab. 21. Sensor data request command message Tab. 22. Sensor data request command message Tab. 23. Sensor data request response message Tab. 24. Sensor data request response message bit Tab. 26. Reserved command message bit field Tab. 27. Reserved command response message Tab. 28. Reserved command response message bit Tab. 31. Expected initial responses after tPOR_ Tab. 32. Expected initial responses after tPOR_ Tab. 33. Basic status field for responses to register Tab. 35. User-accessible data — sensor specific Tab. 36. COUNT - rolling counter register (address Tab. 37. DEVSTAT - device status register (address Tab. 38. DEVSTAT - device status register (address Tab. 39. DEVSTAT1 - device status register Tab. 40. DEVSTAT1 - device status register Tab. 41. DEVSTAT2 - device status register Tab. 42. DEVSTAT2 - device status register Tab. 43. DEVSTAT3 - device status register Tab. 44. DEVSTAT3 - device status register Tab. 45. TEMPERATURE - temperature register Tab. 46. DEVLOCK_WR - lock register writes Tab. 47. DEVLOCK_WR - lock register writes Tab. 49. WRITE_OTP_EN – write OTP enable Tab. 51. UF_REGION_W - UF region selection Tab. 52. UF_REGION_R - UF region selection Tab. 55. SOURCEID_0 - source identification Tab. 56. SOURCEID_1 - source identification Tab. 58. SPI_CFG Register (address 3Dh) bit Tab. 61. WHO_AM_I - device identification register Tab. 63. I2C_ADDRESS - I2C client address Tab. 64. DSP_CFG_U1 - DSP user configuration #1 Tab. 66. DSP_CFG_U3 - DSP user configuration #3 Tab. 69. DSP_CFG_U4 - DSP user configuration #4 Tab. 70. DSP_CFG_U4 - DSP user configuration #4 FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Objective data sheet Rev. 1.1 — 7 June 2023

NXP Semiconductors FXPS7115D4S Digital absolute pressure sensor, 40 kPa to 115 kPa Tab. 71. DSP_CFG_U5 - DSP user configuration #5 Tab. 72. DSP_CFG_U5 - DSP user configuration #5 Tab. 74. INT_CFG - interrupt configuration register Tab. 75. INT_CFG - interrupt configuration register Tab. 76. P_INT_HI, P_INT_LO - interrupt window comparator threshold registers (address Tab. 77. P_CAL_ZERO - pressure calibration Tab. 78. DSP_STAT - DSP-specific status register Tab. 79. DSP_STAT - DSP-specific status register Tab. 80. DEVSTAT_COPY - device status copy Tab. 81. SNSDATA0_L, SNSDATA0_H - sensor data #0 registers (addresses 62h, 63h) bit Tab. 82. SNSDATA1_L, SNSDATA1_H - sensor data #1 registers (address 64h, 65h) bit Tab. 83. SNSDATA0_TIMEx - timestamp register Tab. 84. P_Max and P_Min registers (address 6Ch Tab. 85. FRT - free running timer registers Tab. 86. IC TYPE REGISTER (ICTYPEID address Tab. 87. IC MANUFACTURER REVISION REGISTER (ICREVID address C1h) bit Tab. 88. IC MANUFACTURER IDENTIFICATION REGISTER (ICMFGID address C2h) bit Tab. 96. ASICWFR# Register (address CBh) bit Tab. 97. ASICWFR_X Register (address CCh) bit Tab. 98. ASICWFR_Y Register (address CDh) bit Tab. 99. ASICWLOT_L Register (address D0h) bit Tab. 100. ASICWLOT_H Register (address D1h) bit Tab. 106. External component recommendations for Tab. 107. External component recommendations for Figures Fig. 4. User-controlled PABS common mode self- Fig. 12. Temperature sensor signal chain block Fig. 13. Common mode error detection signal chain Fig. 17. I2C acknowledge and not acknowledge Fig. 20. Standard 32 Bit SPI protocol timing Fig. 23. Absolute pressure accuracy as a function Fig. 24. Absolute pressure accuracy multiplier over Fig. 30. SOT1573-1 PCB design guidelines - Solder Fig. 31. SOT1573-1 PCB design guidelines - I/O Fig. 32. SOT1573-1 PCB design guidelines - Solder FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Objective data sheet Rev. 1.1 — 7 June 2023

NXP Semiconductors FXPS7115D4S Digital absolute pressure sensor, 40 kPa to 115 kPa

7.7.14 P_CAL_ZERO - pressure calibration

7.7.15 DSP_STAT - DSP specific status register

7.7.16 DEVSTAT_COPY - device status copy

7.7.17 SNSDATA0_L, SNSDATA0_H - sensor data

7.7.18 SNSDATA1_L, SNSDATA1_H - sensor data

7.7.19 SNSDATA0_TIMEx - timestamp registers

7.7.20 P_MAX, P_MIN - maximum and minimum

absolute pressure value registers (address

7.7.21 FRT - free running timer registers

7.7.23 IC manufacturer revision register (Address

7.7.24 IC manufacturer identification register

7.7.28 USERDATA_0 to USERDATA_E - user data

7.7.29 USERDATA_10 to USERDATA_1E - user

12 Media compatibility—pressure sensors

13 Pressure sensor accuracy (drift over

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2023 NXP B.V. All rights reserved. For more information, please visit: http://www.nxp.com Date of release: 7 June 2023 Document identifier: FXPS7115D4S

Product Information

FXPS7115D4S specifications and overview.

Summary

Digital absolute pressure sensor, 40 kPa to 115 kPa Rev. 1.1 - 7 June 2023

Description

Digital absolute pressure sensor, 40 kPa to 115 kPa Rev. 1.1 - 7 June 2023

Source title FXPS7115D4S_V01 Datasheet(PDF) - NXP Semiconductors

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