FXOS8700CQR1

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Technical content

1. General description FXOS8700CQ is a small, low-power, 3-axis, linear accelerometer and 3-axis, magnetometer combined into a single package. The device features a selectable I2C or point-to-point SPI serial interface with 14-bit accelerometer and 16-bit magnetometer ADC resolution along with smart-embedded functions. FXOS8700CQ has dynamically selectable acceleration full-scale ranges of ±2 g/±4 g/±8 g and a fixed magnetic measurement range of ±1200 μT. Output data rates (ODR) from 1.563 Hz to 800 Hz are selectable by the user for each sensor. Interleaved magnetic and acceleration data is available at ODR rates of up to 400 Hz. FXOS8700CQ is available in a plastic QFN package and it is guaranteed to operate over the extended temperature range of –40 °C to +85 °C. 2. Features and benefits  Complete 6-axis, e-compass hardware solution  1.95 V to 3.6 V VDD supply voltage, 1.62 V to 3.6 V VDDIO voltage  ±2 g/±4 g/±8 g dynamically selectable acceleration full-scale range  ±1200 µT magnetic sensor full-scale range  Output data rates (ODR) from 1.563 Hz to 800 Hz for each sensor, and up to 400 Hz when operated in hybrid mode with both sensors active  Low noise: < 126 μg/√Hz acceleration noise density at 200-Hz bandwidth, < 100 nT/√Hz magnetic noise density at 100-Hz bandwidth  14-bit ADC resolution for acceleration measurements  16-bit ADC resolution for magnetic measurements  Low power: 240 μA current consumption at 100 Hz, and 80 μA at 25 Hz with both sensors active  Embedded programmable acceleration event functions  Freefall and motion detection  Transient detection  Vector-magnitude change detection  Pulse and tap detection (single and double)  Orientation detection (portrait/landscape)  Embedded programmable magnetic event functions  Threshold detection  Vector-magnitude change detection  Autonomous magnetic min/max detection  Autonomous hard-iron calibration FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer Rev. 7.0 - 22 March 2016 Data sheet: Technical data

unmanned aerial vehicles (UAVs) with electronic compass (e-compass) function. Table 1. Ordering information

Product data sheet Rev. 7.0 — 22 March 2016 3 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer 5. Block diagram Fig 1. Block diagram

Product data sheet Rev. 7.0 — 22 March 2016 4 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer 6. Pinning information

6.1 Pinning

Fig 2. Pin configuration

6.2 Pin description

[1] Refer to Section 10.2.1 regarding point-to-point SPI operation. [3] Refer to Table 11 for I2C address options selectable using the SA0 and SA1 pins. ceramic capacitor placed as close as possible to pin 1 of the device. Table 2. Pin description

Product data sheet Rev. 7.0 — 22 March 2016 6 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer (1) Pullup resistors on SCL/SCLK and SDA/MOSI are not r equired if the device is operated in SPI Interface mode. (2) Pullup resistors on INT1 and INT2 are not required if these pins are configured for push-pull (default) operation. Fig 3. Electrical connection

Product data sheet Rev. 7.0 — 22 March 2016 7 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer

7.1 Orientation

1. Terminology

8.1 Sensitivity

Sensitivity is represented in mg/LSB for the accelerometer and μT/LSB for the magnetometer. The magnetometer sensitivity is fixed at 0.1 μT/LSB. The accelerometer sensitivity changes with the full-scale range selected by the user. Accelerometer sensitivity is 0.244 mg/LSB in 2 g mode, 0.488 mg/LSB in 4 g mode, and 0.976 mg/LSB in 8 g mode.

8.2 Zero- g and zero-flux offset

For the accelerometer, zero-g offset describes the deviation of the output values from the ideal values when the sensor is stationary. With an accelerometer stationary on a level horizontal surface, the ideal output is 0 g for the X and Y axes, and 1 g for the Z-axis. The Fig 4. Product orientation and axis orientation Top view Pin 1 Side view TOP BOTTOM +Ax, +Mx +Ay, +My +Az, +Mz Top view Xout @ 0 g Magnetic Field Earth Gravity Maximum My Minimum MxMaximum Mx Minimum My Maximum Mz Minimum Mz Yout @ –1 g Zout @ 0 g Xout @ 1 g Yout @ 0 g Zout @ 0 g Xout @ –1 g Yout @ 0 g Zout @ 0 g Xout @ 0 g Yout @ 1 g Zout @ 0 g Xout @ 0 g Yout @ 0 g Zout @ 1 g Xout @ 0 g Yout @ 0 g Zout @ –1 g

8.3 Self-test

sensor and by the electrostatic self-test force.

9.1 Accelerometer mechanical characteristics

Table 3. Accelerometer mechanical ch aracteristics @ VDD = 2.5 V, VDDIO = 1.8 V T = 25 °C unless otherwise

[1] Dynamic range is limited to ±4 g when in the low-noise mode. [3] Post-board mount offset specificati ons are based on a 2-layer PCB design. AN4399 for more information. [6] Self-test is only exercised along one direction for each sensitive axis.

9.2 Magnetometer magnetic characteristics

[1] After m-cell has been factory trimmed. figure, expressed in % of the full-scale range (FSMAG). [3] Tested over a ±1000 μT measurement range. Table 4. Magnetometer magnetic characteristics @ VDD = 2.5 V, VDDIO = 1.8 V T = 25 °C unless otherwise noted.

9.3 Hybrid characteristics

9.4 Electrical characteristics

Table 5. Hybrid characteristics @ VDD = 2.5 V, V DDIO = 1.8 V T = 25 °C unless otherwise noted. Table 6. Electrical characteristi cs @ VDD = 2.5 V, VDDIO = 1.8 V T = 25 °C unless otherwise noted.

[1] Time from VDDIO on and VDD > VDD min until I 2C/SPI interface ready for operation. [2] Time to obtain valid data from power-down mode to active mode. [3] Time to obtain valid data from standby mode to active mode. Table 7. IDD (µA) table versus operating modes (VDD + VDDIO), VDD = VDDIO = 2.4 V[1] OS7 = Magnetometer OSR set to 7 (M_CTRL_REG1[m_os] = 0b111).

9.5 Absolute maximum ratings

extended periods may affect device reliability. only handle the device with non-magnetic tools and fixtures. uniform magnetic field on the order of 100 Gauss or greater, along the X-axis. Table 7. IDD (µA) table versus operating modes (VDD + VDDIO), VDD = VDDIO = 2.4 V[1] - ¶continued OS7 = Magnetometer OSR set to 7 (M_CTRL_REG1[m_os] = 0b111). Table 8. Maximum ratings Table 9. ESD and latchup protection characteristics

10.1 I 2C interface characteristics

[2] This device does not stretch the low period (t LOW) of the SCL signal. [3] t VD;DAT = time for data signal from SCL low to SDA output. [5] C b = total capacitance of one bus line in pF. Table 9. ESD and latchup protection characteristics - ¶continued cause the part to otherwise fail. This device is sensitive to ESD, improper handling can cause permanent damage to the part. Table 10. I 2C slave timing values[1]

Product data sheet Rev. 7.0 — 22 March 2016 14 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer

10.1.1 General I 2C operation

There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. External pullup resistors connected to VDDIO are required for SDA and SCL. When the bus is free both the lines are high. The I2C interface is compliant with fast mode (400 kHz), and normal mode (100 kHz) I2C standards. Operation at frequencies higher than 400 kHz is possible, but depends on several factors including the pullup resistor values, and total bus capacitance (trace + device capacitance). See Table 11 for more information. A transaction on the bus is started through a start condition (ST) signal, which is defined as a high-to-low transition on the data line while the SCL line is held high. After the ST signal has been transmitted by the master, the bus is considered busy. The next byte of data transmitted contains the slave address in the first seven bits, and the eighth bit, the read/write bit, indicates whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after the ST condition with its own address. If they match, the device considers itself addressed by the master. The ninth clock pulse, following the slave address byte (and each subsequent byte) is the acknowledge (ACK). The transmitter must release the SDA line during the ACK period. The receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock period. The number of bytes per transfer is unlimited. If a receiver can't receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL low to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. This delay action is called clock stretching. Not all receiver devices support clock stretching. Not all master devices recognize clock stretching. This part does not use clock stretching. A low to high transition on the SDA line while the SCL line is high is defined as a stop condition (SP) signal. A write or burst write is always terminated by the master issuing the SP signal. A master should properly terminate a read by not acknowledging a byte at the appropriate time in the protocol. A master may also issue a repeated start signal (SR) during a transfer The slave addresses that may be assigned to the FXOS8700CQ part are 0x1C, 0x1D, 0x1E, or 0x1F. The selection is made through the logic level of the SA1 and SA0 inputs. Fig 5. I 2C slave timing diagram handbook, full pagewidth MSC610 S Sr tSU;STOtSU;STAtHD;STA tHIGH tLOW tSU;DAT tHD;DAT tf SDA SCL P S tBUFtr tftr tSPtHD;STA

10.1.2 I 2C read/write operations

the transmitted data, but transmits a stop condition to end the data transfer. transfer. The data sent to the FXOS8700CQ is now stored in the appropriate register. acknowledgment (ACK) is received. Table 11. I 2C slave address

10.2 SPI interface characteristics

considered as the slave and thus is never initiating the communication. Table 12 and Figure 7 describe the timing requirements for the SPI system. Table 12. SPI timing

10.2.1 General SPI operation

multiple slave devices are present on the bus. master toggles the SPI clock (SCLK) and transmits data on the MOSI pin. Byte 2: DATA[7],DATA[6],DATA[5],DATA[4],DATA[3],DATA[2],DATA[1],DATA[0].

• Polarity: rising/falling
• Phase: sample/setup
• Order: MSB first Data is sampled during the rising edge of SCLK and set up during the falling edge of SCLK.

10.2.2 SPI read/write operations

are ignored by the part. The read data is deserialized from the MISO pin. starting from the indicated register address in ADDR[7:0]. ended by deasserting the CS_B pin (low-to-high transition). VDD can be powered off and the communications pins will be in a high impedance state. This will allow communications to continue on the bus with other devices. transmitted by the master using the MOSI pin. That is, a transaction is always initiated by master. Table 13. Serial interf ace pin descriptions

10.2.3 I 2C/SPI auto detection

10.2.4 Power supply sequencing and I 2C/SPI mode auto-detection

period. If the INT1 pin was already low prior to the reset event, it will only go high. Table 14. I 2C/SPI auto detection Table 15. Mode of operation description blocks are shutdown. I2C bus inhibited. Only digital blocks are enabled. All blocks are enabled (digital and analog).

Product data sheet Rev. 7.0 — 22 March 2016 20 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer All register contents are preserved when transitioning from active-to-standby mode, but some registers are reset when transitioning from standby-to-active. These registers are noted in Table16. The sleep and wake modes are active modes. For more information on how to use the sleep and wake modes and configuring the device to transition between them, please refer to Section 12 or NXP application note AN4074. 12. Embedded functionality FXOS8700CQ is a low-power, digital output, 6-axis sensor with both I2C and SPI interfaces. Extensive embedded functionality is provided to detect inertial and magnetic events at low power, with the ability to notify the host processor of an event using either of the two programmable interrupt pins. The embedded functionality includes:

• 8-bit or 14-bit accelerometer data which includes high-pass filtered data, and 8-bit or 16-bit magnetometer data
• Four different oversampling options for the accelerometer output data, and eight for the magnetometer. The oversampling settings allow the end user to optimize the resolution versus power trade-off in a given application.
• A low-noise accelerometer mode that functions independently of the oversampling modes for even higher resolution
• Low-power, auto-wake/sleep function for conserving power in portable battery powered applications
• Accelerometer pulse-detection circuit which can be used to detect directional single and double taps
• Accelerometer directional motion- and freefall-event detection with programmable threshold and debounce time
• Acceleration transient detection with programmable threshold and debounce time. Transient detection can employ either a high-pass filter or use the difference between reference and current sample values.
• Orientation detection with programmable hysteresis for smooth transitions between portrait/landscape orientations
• Accelerometer vector-magnitude change event detection with programmable reference, threshold, and debounce time values
• Magnetic threshold event detection with programmable reference, threshold, and debounce time
• Magnetometer vector-magnitude change event detection with programmable reference, threshold and debounce time values
• Magnetic min/max detection circuit which can also be used for autonomous calibration of magnetic hard-iron offset Many different configurations of the above functions are possible to suit the needs of the end application. Separate application notes are available to further explain the different configuration settings and potential use cases.

12.1 Factory calibration

FXOS8700CQ's integrated accelerometer and magnetometer sensors are factory calibrated for sensitivity and offset on each axis. The trim values are stored in non-volatile memory (NVM). On power-up, the trim parameters are read from NVM and applied to the internal compensation circuitry. After mounting the device to the PCB, the user may

Product data sheet Rev. 7.0 — 22 March 2016 21 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer further adjust the accelerometer and magnetometer offsets through the OFF_X/Y/Z and M_OFF_X/Y/Z registers, respectively. For more information on device calibration, refer to NXP application note, AN4399. 12.2 8-bit or 14-bit accelerometer data The measured acceleration data is stored in the OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB registers as 2’s complement 14-bit numbers. The most significant 8-bits of each axis are stored in the OUT_X/Y /Z_MSB registers, so applications needing only 8-bit results simply read these three registers and ignore the OUT_X/Y/Z_LSB registers. To do this, the f_read mode bit in CTRL_REG1 must be set. When the full-scale range is set to 2 g, the measurement range is –2 g to +1.999 g, and each count corresponds to 0.244 mg at ±14-bits resolution. When the full-scale is set to 8 g, the measurement range is –8 g to +7.996 g, and each count corresponds to 0.976 mg. The resolution is reduced by a factor of 64 if only the 8-bit results are used (CTRL_REG1[f_read] = 1). For further information on the different data formats and modes, please refer to NXP application note AN4076.

12.3 Accelerometer low-power mod es versus high-resolution modes

FXOS8700CQ can be optimized for lower power or higher resolution of the accelerometer output data. High resolution is achieved by setting the lnoise bit in register 0x2A. This improves the resolution (by lowering the noise), but be aware that the full-scale range setting is restricted to ±2 g or ±4 g when this bit is set. This will affect all internal embedded functions (scaling of thresholds, etc.) and reduce noise. Another method for improving the resolution of the data is through oversampling. One of the oversampling schemes of the output data can be activated when CTRL_REG2[mods] = 0b10 which will improve the resolution of the output data without affecting the internal embedded functions or fixing the dynamic range. There is a trade-off between low power and high resolution. Low power can be achieved when the oversampling rate is reduced. When CTRL_REG2[ mods] = 0b10, the lowest power is achieved, at the expense of higher noise. In general, the lower the selected ODR and OSR, the lower the power consumption. For more information on how to configure the device in low-power or high-resolution modes and understand the benefits and trade-offs, please refer to NXP application note AN4075.

12.4 Auto-wake/sleep mode

FXOS8700CQ can be configured to transition between sample rates (with their respective current consumptions) based on the status of the embedded interrupt event generators in the device. The advantage of using the auto-wake/sleep is that the system can automatically transition to a higher sample rate (higher current consumption) when needed but spends the majority of the time in the sleep mode (lower current) when the device does not require higher sampling rates. Auto-wake refers to the device being triggered by one of the interrupt event functions to transition to a higher sample rate. This may also interrupt the processor to transition from a sleep mode to a higher power mode.

Product data sheet Rev. 7.0 — 22 March 2016 22 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer Sleep mode occurs when none of the enabled interrupt event functions has detected an interrupt within the user-defined, time-out period. The device will then transition to the specified lower sample rate. It may also alert the processor to go into a lower power mode to save power during this period of inactivity. Refer to AN4074 for more detailed information on configuring the auto-wake/sleep function.

12.5 Hybrid mode

FXOS8700CQ uses a single common analog-to-digital converter (ADC) for both the accelerometer and magnetometer. When operating in hybrid mode (M_CTRL_REG1[m_hms] = 0b11), both the accelerometer and magnetometer sensors are actively measured by the ADC at an ODR equal to one half of the setting made in CTRL_REG1[dr] when operating in accelerometer-only mode (M_CTRL_REG1[m_hms] = 0b00 (default)) or magnetometer-only mode (M_CTRL_REG1[m_hms] = 0b01). While the ODR is common to both sensors when operating in hybrid mode, the OSR settings for each sensor are independent and may be set using the CTRL_REG2[mods] for the accelerometer and M_CTRL_REG1[m_os] for the magnetometer, respectively.

12.6 Accelerometer freefall and motion event detection

FXOS8700CQ integrates a programmable threshold based acceleration detection function capable of detecting either motion or freefall events depending upon the configuration. For further details and examples on using the embedded freefall and motion detection functions, refer to NXP application note AN4070.

12.6.1 Freefall detection

The detection of “Freefall” involves the monitoring of the X, Y, and Z axes for the condition where the acceleration magnitude is below a user-specified threshold for a user-definable amount of time. Typically, the usable threshold ranges are between ±100 mg and ±500 mg.

12.6.2 Motion detection

Motion detection is often used to alert the main processor that the device is currently in use. When the acceleration exceeds a set threshold for a set amount of time, the motion interrupt is asserted. A motion can be a fast moving shake or a slow moving tilt. This will depend on the threshold and timing values configured for the event. The motion detection function can analyze static acceleration changes or faster jolts. The timing value is set by a configurable debounce counter. The debounce counter acts like a filter to indicate whether the condition exists for longer than a set amount of time (that is, 100 ms or longer). There is also directional data available in the source register to detect the direction of the motion that generated the interrupt. This is useful for applications such as directional shake or flick detection, and can also assist gesture detection algorithms by indicating that a motion gesture has started.

12.7 Transient detection

FXOS8700CQ integrates an acceleration transient detection function that incorporates a high-pass filter. Acceleration data goes through the high-pass filter, eliminating the DC tilt offset and low frequency acceleration changes. The high-pass filter cutoff can be set by the user to four different frequencies which are dependent on the selected output data

Product data sheet Rev. 7.0 — 22 March 2016 23 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer rate (ODR). A higher cutoff frequency ensures that DC and slowly changing acceleration data will be filtered out, allowing only the higher frequencies to pass. The transient detection feature can be used in the same manner as the motion detection by bypassing the high-pass filter. There is an option in the configuration register to do this. This adds more flexibility to cover the various customer use cases. Many applications use the accelerometer’s static acceleration readings (that is, tilt) which measure the change in acceleration due to gravity only. These functions benefit from acceleration data being filtered with a low-pass filter where high-frequency data is considered noise. However, there are many functions where the accelerometer must analyze dynamic acceleration. Functions such as tap, flick, shake and step counting are based on the analysis of the change in the dynamic acceleration. The transient detection function can be routed to either interrupt pin through bit 5 in CTRL_REG5 register (0x2E). Registers 0x1D – 0x20 are used for configuring the transient detection function. The source register contains directional data to determine the direction of the transient acceleration, either positive or negative. For further information of the embedded transient detection function along with specific application examples and recommended configuration settings, refer to NXP application note AN4461.

12.8 Pulse detection

FXOS8700CQ has embedded single/double and directional pulse detection. This function employs several timers for programming the pulse width time and the latency between pulses. The detection thresholds are independently programmable for each axis. The acceleration data input to the pulse detection circuit can be put through both high and low-pass filters, allowing for greater flexibility in discriminating between pulse and tap events. The PULSE_SRC register provides information on the axis, direction (polarity), and single/double event status for the detected pulse or tap. For more information on how to configure the device for pulse detection, please refer to NXP application note AN4072.

12.9 Orientation detection

FXOS8700CQ has an embedded orientation detection algorithm with the ability to detect all six orientations. The transition angles and hysteresis are programmable, allowing for a smooth transition between portrait and landscape orientations. The angle at which the device no longer detects the orientation change is referred to as the “Z-lockout angle”. The device operates down to 29° from the flat position. All angles are accurate to ±2°. For further information on the orientation detection function refer to NXP application note, AN4068.

12.10 Acceleration vecto r-magnitude detection

FXOS8700CQ incorporates an acceleration vector-magnitude change detection block that can be configured to generate an interrupt when the acceleration magnitude exceeds a preset threshold for a programmed debounce time. The function can be configured to operate in absolute or relative modes, and can also act as a wake-to-sleep/sleep-to-wake source. This function is useful for detecting acceleration transients when operated in absolute mode, or for detecting changes in orientation when operated in relative mode, refer to NXP application note AN4692.

Product data sheet Rev. 7.0 — 22 March 2016 24 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer

12.11 Magnetic vector-magnitude detection

FXOS8700CQ incorporates a magnetic vector-magnitude change detection block that can be configured to generate an interrupt when the magnetic field magnitude exceeds a preset threshold for a programmed debounce time. The function can be configured to operate in absolute or relative modes, and can also act as a wake-to-sleep/sleep-to-wake source. For more information, refer to NXP application note AN4458.

12.12 Magnetic threshold detection

FXOS8700CQ incorporates a magnetic threshold event detection block that can be configured to generate an interrupt when the magnetic field on the enabled axes is above or below a programmed threshold. Two logic combinations are possible for the detection: all of the enabled axes below their respective thresholds (AND condition), or any of the enabled axes above their respective thresholds (OR condition). Even detection may be filtered using a dedicated debounce counter to avoid spurious event detection. The thresholds for each axis are individually programmable and the function can also act as a wake-to-sleep/sleep-to-wake source.

12.13 Magnetic min/ma x detection (autonomous calibration)

FXOS8700CQ incorporates a magnetic min/max detection circuit that can be used to automatically track the minimum and maximum field values measured on each of the X, Y, and Z axes. The stored minimum and maximum values may optionally be used to determine the magnetic hard-iron compensation and load the offset registers with the appropriate correction values. For more information, refer to NXP application note AN4459.

Product data sheet Rev. 7.0 — 22 March 2016 25 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer 13. Example FXOS8700CQ driver code

13.1 Introduction

It is very straightforward to configure the FXOS8700CQ and start receiving data from the three accelerometer and three magnetometer channels. Unfortunately, since every hardware platform will be different, it is not possible to provide completely portable software drivers. This section therefore provides real FXOS8700CQ driver code for a Kinetis uC board running under the MQX operating system. The I2C functions s_i2c_read_regs and s_i2c_write_regs are not provided here and should be replaced with the corresponding low level I2C driver code on the development platform.

13.2 FXOS8700CQ addresses

This section lists the I2C address of the FXOS8700CQ. The I2C address depends on the logic level of FXOS8700CQ’s SA0 and SA1 address selection pins, so the actual I2C address may be 0x1C, 0x1D, 0x1E or 0x1F. Please see Table 11, “I2C slave address,” on page 15 for the available I2C addresses and SA1/SA0 settings. Example 1. // FXOS8700CQ I2C address #define FXOS8700CQ_SLAVE_ADDR 0x1E // with pins SA0=0, SA1=0 Some of the key FXOS8700CQ internal register addresses are listed below. Example 2. // FXOS8700CQ internal register addresses #define FXOS8700CQ_STATUS 0x00 #define FXOS8700CQ_WHOAMI 0x0D #define FXOS8700CQ_XYZ_DATA_CFG 0x0E #define FXOS8700CQ_CTRL_REG1 0x2A #define FXOS8700CQ_M_CTRL_REG1 0x5B #define FXOS8700CQ_M_CTRL_REG2 0x5C #define FXOS8700CQ_WHOAMI_VAL 0xC7 The reference driver code shown in this example does a block read of the FXOS8700CQ status byte and three 16-bit accelerometer channels plus three 16-bit magnetometer channels for a total of 13 bytes in a single I 2C read operation. Example 3. // number of bytes to be read from the FXOS8700CQ #define FXOS8700CQ_READ_LEN 13 // status plus 6 channels = 13 bytes

Product data sheet Rev. 7.0 — 22 March 2016 26 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer

13.3 Sensor data structure

The high and low bytes of the three accelerometer and three magnetometer channels are placed into a structure of type SRAWDATA containing three signed short integers. Example 4. typedef struct int16_t x; int16_t y; int16_t z; } SRAWDATA;

13.4 FXOS8700CQ configuration function

This function configures the FXOS8700CQ for 200-Hz hybrid mode meaning that both accelerometer and magnetometer data are provided at the 200-Hz rate. The code is self-explanatory and can be easily customized for different settings. Example 5. // function configures FXOS8700CQ combination accelerometer and magnetometer sensor static _mqx_ints_FXOS8700CQ_start(MQX_FILE_PTR aFP) uint8_t databyte; // read and check the FXOS8700CQ WHOAMI register if (s_i2c_read_regs(aFP, FXOS8700CQ_SLAVE_ADDR, FXOS8700CQ_WHOAMI, &databyte, (uint8_t) 1) != 1) return (I2C_ERROR); if (databyte != FXOS8700CQ_WHOAMI_VAL) return (I2C_ERROR); // write 0000 0000 = 0x00 to accelerometer control register 1 to place FXOS8700CQ into // standby // [0]: active=0 databyte = 0x00; if (s_i2c_write_regs(aFP, FXOS8700CQ_SLAVE_ADDR, FXOS8700CQ_CTRL_REG1, &databyte, (uint8_t) 1) != 1) return (I2C_ERROR); // write 0001 1111 = 0x1F to magnetometer control register 1 // [7]: m_acal=0: auto calibration disabled // [6]: m_rst=0: no one-shot magnetic reset

Product data sheet Rev. 7.0 — 22 March 2016 27 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer // [5]: m_ost=0: no one-shot magnetic measurement // [4-2]: m_os=111=7: 8x oversampling (for 200Hz) to reduce magnetometer noise // [1-0]: m_hms=11=3: select hybrid mode with accel and magnetometer active databyte = 0x1F; if (s_i2c_write_regs(aFP, FXOS8700CQ_SLAVE_ADDR, FXOS8700CQ_M_CTRL_REG1, &databyte, (uint8_t) 1) != 1) return (I2C_ERROR); // write 0010 0000 = 0x20 to magnetometer control register 2 // [7]: reserved // [6]: reserved // [5]: hyb_autoinc_mode=1 to map the magnetometer registers to follow the // accelerometer registers // [4]: m_maxmin_dis=0 to retain default min/max latching even though not used // [3]: m_maxmin_dis_ths=0 // [2]: m_maxmin_rst=0 // [1-0]: m_rst_cnt=00 to enable magnetic reset each cycle databyte = 0x20; if (s_i2c_write_regs(aFP, FXOS8700CQ_SLAVE_ADDR, FXOS8700CQ_M_CTRL_REG2, &databyte, (uint8_t) 1) != 1) return (I2C_ERROR); // write 0000 0001= 0x01 to XYZ_DATA_CFG register // [7]: reserved // [6]: reserved // [5]: reserved // [4]: hpf_out=0 // [3]: reserved // [2]: reserved // [1-0]: fs=01 for accelerometer range of +/-4g range with 0.488mg/LSB databyte = 0x01; if (s_i2c_write_regs(aFP, FXOS8700CQ_SLAVE_ADDR, FXOS8700CQ_XYZ_DATA_CFG, &databyte, (uint8_t) 1) != 1) return (I2C_ERROR); // write 0000 1101 = 0x0D to accelerometer control register 1 // [7-6]: aslp_rate=00 // [5-3]: dr=001 for 200Hz data rate (when in hybrid mode) // [2]: lnoise=1 for low noise mode

Product data sheet Rev. 7.0 — 22 March 2016 28 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer // [1]: f_read=0 for normal 16 bit reads // [0]: active=1 to take the part out of standby and enable sampling databyte = 0x0D; if (s_i2c_write_regs(aFP, FXOS8700CQ_SLAVE_ADDR, FXOS8700CQ_CTRL_REG1, &databyte, (uint8_t) 1) != 1) return (I2C_ERROR); // normal return return (I2C_OK);

13.5 Data read function

This function performs a block read of the status, accelerometer and magnetometer measurement registers and places the bytes read into the structures of type SRAWDATA as signed short integers. Note that this function assumes that the hyb_autoinc_mode bit has been set to enable the reading of all accelerometer and magnetometer data in a single-burst, read operation. Example 6. // read status and the three channels of accelerometer and magnetometer data from // FXOS8700CQ (13 bytes) int16_t ReadAccelMagnData(SRAWDATA *pAccelData, SRAWDATA *pMagnData) MQX_FILE_PTR fp; // I2C file pointer uint8_t Buffer[FXOS8700CQ_READ_LEN]; // read buffer // read FXOS8700CQ_READ_LEN=13 bytes (status byte and the six channels of data) if (s_i2c_read_regs(fp, FXOS8700CQ_SLAVE_ADDR, FXOS8700CQ_STATUS, Buffer, FXOS8700CQ_READ_LEN) == FXOS8700CQ_READ_LEN) // copy the 14 bit accelerometer byte data into 16 bit words pAccelData->x = (int16_t)(((Buffer[1] << 8) | Buffer[2]))>> 2; pAccelData->y = (int16_t)(((Buffer[3] << 8) | Buffer[4]))>> 2; pAccelData->z = (int16_t)(((Buffer[5] << 8) | Buffer[6]))>> 2; // copy the magnetometer byte data into 16 bit words pMagnData->x = (Buffer[7] << 8) | Buffer[8]; pMagnData->y = (Buffer[9] << 8) | Buffer[10];

Product data sheet Rev. 7.0 — 22 March 2016 29 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer pMagnData->z = (Buffer[11] << 8) | Buffer[12]; else // return with error return (I2C_ERROR); // normal return return (I2C_OK);

Table 16. Register address map

Table 16. Register address map - ¶continued

[1] Register contents are preserved when transitioning from active-to-standby mode. [2] Register contents are reset when trans itioning from standby-to-active mode. magnetometer data in one contiguous operation. reset of the corresponding internal system debounce counter. bit fields in XYZ_DATA_CFG register. M_OUT_X/Y/Z registers with the current time-aligned output data. register will result in invalid data.

Table 17. Auto-increment address

Table 17. Auto-increment address - ¶continued

14.1 Device configuration registers

14.1.1 STATUS register (address 0x00)

in both 8- and 14-bit modes.

14.1.2 DR_STATUS register (address 0x00)

and reflects real-time updates to the OUT_X, OUT_Y, and OUT_Z registers. Table 18. STATUS register (address 0x00) bit allocation Table 19. STATUS register (address 0x00) bit description Table 20. DR_STATUS register (address 0x00) bit allocation

Table 21. DR_STATUS register (address 0x00) bit descriptions OUT_Y_MSB, and OUT_Z_MSB) are read. X, Y, and Z-axis data overwrite. zow zow is set to 1 whenever a new Z-axis acquisition is completed before the retrieval of the previous data. When this occurs the previous data is overwritten. zow is cleared anytime OUT_Z_MSB register is read. yow yow is set to 1 whenever a new Y-axis acquisition is completed before the retrieval of the previous data. When this occurs the previous data is overwritten. yow is cleared anytime OUT_Y_MSB register is read. xow xow is set to 1 whenever a new X-axis acquisition is completed before the retrieval of the previous data. When this occurs the previous data is overwritten. xow is cleared anytime OUT_X_MSB register is read. high-bytes of the acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) are read. X, Y, and Z-axis new data ready.

14.1.3 F_STATUS register (address 0x00)

FIFO Status when F_SETUP[f_mode] = 0x00 > 0x00. the current status information of the FIFO subsystem. again when the next data sample enters the FIFO.

14.1.4 TRIG_CFG register (address 0x0A)

NXP application note AN4073. Table 22. F_STATUS register (address 0x00) bit allocation Table 23. FIFO flag event descriptions 0 X No FIFO overflow events detected. 1 X FIFO overflow event detected. X 0 No FIFO watermark event detected. than watermark value has been reached. Table 24. FIFO - sample count (address 0x00) bit description 0b00_0000 indicates that the FIFO is empty. FIFO sample counter. Default value 0b00_0000.

14.1.5 SYSMOD register (address 0x0B)

14.1.6 INT_SOURCE register (address 0x0C)

located in the M_INT_SRC register (0x5E). Table 25. TRIG_CFG register (address 0x0A) bit allocation Table 26. TRIG_CFG register (address 0x0A) bit descriptions trig_trans Transient interrupt FIFO trigger enable. trig_lndprt Landscape/portrait orient ation interrupt FIFO trigger enable. trig_a_vecm Acceleration vector-magnitude FIFO trigger enable. Table 27. SYSMOD register (address 0x0B) bit allocation Table 28. SYSMOD register (a ddress 0x0B) bit descriptions fgerr FIFO gate error. Default value: 0. 0 – No FIFO gate error detected. 1 – FIFO gate error was detected. Emptying the FIFO buffer clears the fgerr bit in the SYSMOD register. See Section 14.1.10 for more information on configuring the FIFO gate function. sysmod[1:0] System mode. Default value: 0b00.

appropriate source register for the function that generated the interrupt. Table 29. INT_SOURCE register (address 0x0C) bit allocation Table 30. INT_SOURCE register (address 0x0C) bit descriptions wake-to-sleep or sleep-to-wake system mode transition interrupt event has occurred. thus causing the system to transition to the user-specified higher ODR setting. Reading the SYSMOD register will clear the src_aslp bit. interrupt event has occurred. This bit is cleared by reading the F_STATUS register. user-specified threshold has occurred. and logic ‘0’ indicates that no transient event has occurred. This bit is cleared by reading the TRANSIENT_SRC register. This bit is cleared by reading the PL_STATUS register. pulse event and logic ‘0’ indicates that no pulse event was detected. This bit is cleared by reading the PULSE_SRC register.

14.1.7 WHO_AM_I register (address 0x0D)

0xC4 for preproduction devices and 0xC7 for production devices.

14.1.8 CTRL_REG1 register (address 0x0A)

mode to change any of the fields within CTRL_REG1 (0x2A). and logic ‘0’ indicates that no freefall or motion event was detected. This bit is cleared by reading the A_FFMT_SRC register. generated. This bit is cleared by reading this register (INT_SOURCE). be read. In hybrid mode, this bit signals that new acceleration and/or magnetic data is available. starting at register 0x01 (OUT_X_MSB). Table 31. WHO_AM_I register (address 0x0D) bit allocation Table 32. CTRL_REG1 register (address 0x0A) bit allocation

in Table 35. For example, with aslp_rate = 0b00 the frequency is 25 Hz. Table 33. CTRL_REG1 register (address 0x0A) bit descriptions aslp_rate[1:0] Configures the auto-wake sample frequency when the device is in sleep mode. See Table 35 for more information. dr[2:0] Output data rate (ODR) selection. See Table 35 for more information. lnoise Reduced noise and full-scale range mode (analog gain times 2). cannot be used in ±8 g mode. Table 34. Sleep mode ODR selection Table 35. System Output Data Rate selection

low-noise mode. In low-noise mode the maximum signal that can be measured is ±4 g. Note: Any thresholds set above 4 g will not be reached. with a single 6-byte burst read starting at the OUT_X_MSB register. The f_read bit can only be changed while F_SETUP[f_mode] = 0.

14.1.9 CTRL_REG2 register (address 0x2B)

Table 36. CTRL_REG2 register (address 0x2B) bit allocation

Table 37. CTRL_REG2 register (address 0x2B) bit descriptions pulsing the external RST pin high. I2C mode. See Section 10.2.3 for further information about the interface mode auto-detection circuit. driver in such a way that it does not look for an ACK following a soft reset command. At the end of the boot process, the rst bit is hardware cleared. setting determines the sleep mode power and noise for acceleration measurements. See Table 38 and Table 39 for more information. and Table 39 for more information. Table 38. CTRL_REG2[(s)mods] oversampling modes

14.1.10 CTRL_REG3 - interrupt control register (address 0x2C)

Table 39. Oversampling Ratio versus oversampling mode Table 40. CTRL_REG3 - interrupt control register (address 0x2C) bit allocation Table 41. CTRL_REG3 - interrupt control register (address 0x2C) bit descriptions mode or from sleep-to-wake mode. and new data samples are ignored until the FIFO is emptied by the host application. the FIFO buffer remains un-emptied. Emptying the FIFO buffer clears the SYS_MOD[fgerr] register. wake_lndprt 0 – Orientation function is disabled sleep mode.

data from different ODR periods.

14.1.11 CTRL_REG4 - interrupt enable register (address 0x2D)

ipol The ipol The bit selects the logic polarity of the interrupt signals output on the INT1 and INT2 pins. Table 41. CTRL_REG3 - interrupt control register (address 0x2C) bit descriptions - ¶continued Table 42. CTRL_REG4 - interrupt enable register (address 0x2D) bit allocation Table 43. CTRL_REG4 - interrupt enable register (address 0x2D) bit descriptions

(MAG_THS_CFG), and 0x69 (M_VECM_CFG), respectively.

14.1.12 CTRL_REG5 - interrupt routing configuration register (address 0x2E)

Table 43. CTRL_REG4 - interrupt enable register (address 0x2D) bit descriptions - ¶continued Table 44. CTRL_REG5 - interrupt routing configur ation register (address 0x2E) bit allocation Table 45. CTRL_REG5 - interrupt routing configuration register (address 0x2E) bit descriptions

source(s) of the interrupt(s). 1 – Interrupt is routed to INT1 pin.

14.2 Auto-sleep trigger register

14.2.1 ASLP_COUNT register (address 0x29)

Table 46. ASLP_COUNT register (address 0x29) bit allocation Table 47. ASLP_COUNT register (address 0x29) bit description Table 48. ASLP_COUNT relationship with ODR

to hybrid mode, the ASLP_COUNT time step becomes 640 ms. sample data until the host application flushes the FIFO buffer. auto-sleep mode (that is, wakes up), except for the data ready function. ODR value specified in CTRL_REG1[aslp_rate]. by the host application before new samples can be acquired. Table 49. Sleep/wake mode gates and triggers

14.3 Temperature register

14.3.1 TEMP register (address 0x51)

Eight-bit 2’s complement sensor temperature value with 0.96 °C/LSB sensitivity.

14.4 Accelerometer output data registers

14.4.1 OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB,

expressed as 2's complement numbers. Table 50. TEMP register (address 0x51) bit allocation

CTRL_REG1[f_read] register setting. return a value of zero when read directly. Table 51. OUT_X_MSB register (address 0x01) bit allocation Table 52. OUT_X_LSB register (address 0x02) bit allocation Table 53. OUT_Y_MSB register (address 0x03) bit allocation Table 54. OUT_Y_LSB register (address 0x04) bit allocation

14.5 Accelerometer FIFO register

14.5.1 F_SETUP register (address 0x09)

[1] This bit field can be written in active mode. [2] This bit field can be written in standby mode. [3] The FIFO mode (f_mode) cannot be switched between operational modes (0b01, 0b10 and 0b11). Table 55. OUT_Z_MSB register (address 0x05) bit allocation Table 56. OUT_Z_LSB register (address 0x06) bit allocation Table 57. F_SETUP register (address 0x09) bit allocation Table 58. F_SETUP register (address 0x09) bit descriptions discarded to be replaced by new sample. 0b10 – FIFO stops accepting new samples when overflowed. (auto-sleep/wake), or on a transition from standby mode to active mode. F_STATUS[f_cnt] status flags to zero. A FIFO overflow event (that is, F_STATUS[f_cnt] = 32) will assert the F_STATUS[f_ovf] flag. [2] FIFO sample count watermark. or greater than the f_ wmrk watermark. Setting the f_wmrk to 0b00_0000 will disable the FIFO watermark event flag generation. This field is also used to set the number of pre-trigger samples in trigger mode (f_mode = 0b11).

CTRL_REG1[aslp_rate] bit fields. FIFO operating modes, please refer to NXP application note AN4073.

14.6 Accelerometer sensor data configuration register

14.6.1 XYZ_DATA_CFG register (address 0x0E)

range, and also to select whether the output data is passed through the high-pass filter. Table 59. XYZ_DATA_CFG register (address 0x0E) bit allocation Table 60. XYZ_DATA_CFG register (address 0x0E) bit descriptions 0 – High-pass filter is disabled. fs[1:0] Accelerometer full-scale range selection. See Table 61. Table 61. Full-scale range selection

14.7 Accelerometer high-p ass filter register

14.7.1 HP_FILTER_CUTOFF register (address 0x0F)

High-pass filter cutoff frequency setting register. Table 62. HP_FILTER_CUTOFF register (address 0x0F) bit allocation Table 63. HP_FILTER_CUTOFF register (address 0x0F) bit descriptions Table 64. HP_FILTER_CUTOFF

Product data sheet Rev. 7.0 — 22 March 2016 58 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer Please note that when the part is operated in hybrid mode, the ODR is reduced by a factor of two, which also affects the filter cutoff frequency. For example, an ODR setting of

400 Hz in accelerometer only mode with HP_FILTER_CUTOFF[sel] = 0b10 sets the cutoff

frequency at 4 Hz. If the part is operated in Hybrid mode, the effective ODR becomes

200 Hz and the cutoff frequency is now 2 Hz for the same ODR and

HP_FILTER_CUTOFF[sel] settings.

14.8 Portrait/landscape detection registers

The FXOS8700CQ is capable of detecting six orientations: landscape left, landscape right, portrait up, and portrait down with Z-lockout feature as well as face up and face down orientation as shown in Figure 13 , 14, and 15. For more details on the meaning of the different user-configurable settings and for example code, please refer to NXP application note AN4068. Fig 13. Z-tilt angle lockout transition Fig 14. Landscape to portrait transition NORMAL 90° Z-LOCK = 32.142° DETECTION LOCKOUT REGION Portrait Landscape to Portrait 90° Trip Angle = 60° 0° Landscape

14.8.1 PL_STATUS register (address 0x10)

[1] The default powerup state is bafro(Undefined), lapo( Undefined), and no lockout for orientation function. Table 65. PL_STATUS register (address 0x10) bit allocation Table 66. PL_STATUS register (address 0x10) bit descriptions newlp Landscape/portrait status change flag. bafro Back or front orientation.

experienced on any of the three axes is greater than 1.25 g.

14.8.2 PL_CFG register (address 0x11)

14.8.3 PL_COUNT register (address 0x12)

200 Hz, and the effective debounce time step is 5 ms instead of 2.5 ms. Table 67. PL_CFG register (address 0x11) bit allocation Table 68. PL_CFG register (address 0x11) bit descriptions dbcntm Debounce counter mode selection. 0 – Decrements debounce whenever condition of interest is no longer valid. pl_en Portrait/landscape detection enable. 0 – Portrait/landscape detection is disabled. Table 69. PL_COUNT register (address 0x12) bit allocation

14.8.4 PL_BF_ZCOMP register (address 0x13)

Back/front and Z-tilt angle compensation register. Table 70. PL_Count Relationship with the ODR Table 71. PL_BF_ZCOMP register (address 0x13) bit allocation Table 72. PL_BF_ZCOMP register (address 0x13) bit descriptions bkfr[1:0] Back/front trip angle threshold. See Table 74 for more information. Default: 0b10 → ±70°. Step size is 5°. Table 73. Z-lockout angle definitions

14.8.5 PL_THS_REG register (address 0x14)

Portrait to landscape trip threshold registers. Table 74. Back/front orientation definitions Table 75. PL_THS_REG register (address 0x14) bit allocation Table 76. Threshold angle lookup table Table 77. Trip angles versus hysteresis settings

14.9 Freefall and motion detection registers

(motion) events utilizing the A_FFMT_CFG[a_ffmt_oae] bit. on all enabled axes (ex. X, Y and Z) for the A_FFMT_SRC[a_ffmt_ea] bit to be affected. A_FFMT_SRC[a_ffmt_ea] flag can only be cleared by reading the A_FFMT_SRC register. A_FFMT_SRC[a_ffmt_ea] bit reflects the real-time status of the event detection. value stored in register 0x17 is used as a common 7-bit threshold for the X, Y, and Z axes. threshold (stored in the A_FFMT_X/Y/Z MSB and LSB registers).

14.9.1 A_FFMT_CFG register (address 0x15)

Freefall/motion configuration register. Table 78. Portrait/landscape ideal orientation definitions Table 79. A_FFMT_CFG register (address 0x15) bit allocation

14.9.2 A_FFMT_SRC register (address 0x16)

Freefall/motion source register. Read-only register. generate the freefall/motion interrupts. Table 80. A_FFMT_CFG register (a ddress 0x15) bit descriptions flags) and freefall (logical AND combination of low-g X, Y, and Z-axis event flags) detection. Motion detect/freefall detect logic selection. A_FFMT_CFG register, new event flags are blocked from updating the A_FFMT_SRC register. 1 – Raise event flag on measured Z-axis acceleration above/below threshold. A_FFMT_CFG register, new event flags are blocked from updating the A_FFMT_SRC register. 1 – Raise event flag on measured Y-axis acceleration above/below threshold. A_FFMT_CFG register, new event flags are blocked from updating the A_FFMT_SRC register. 1 – Raise event flag on measured X-axis acceleration above/below threshold. Table 81. A_FFMT_SRC register (address 0x16) bit allocation

14.9.3 A_FFMT_THS register (address 0x17)

Freefall/motion detection threshold registers. Table 82. A_FFMT_SRC register (a ddress 0x16) bit descriptions a_ffmt_ea Event active flag. A_FFMT_CFG[a_ffmt_oae] bit to determine the effect of the 3-axis event flags on the a_ffmt_ea bit. a_ffmt_zhe Z-high event flag. a_ffmt_zhp Z-high event polarity flag. a_ffmt_yhe Y-high event flag. a_ffmt_yhp Y-high event polarity flag. a_ffmt_xhe X-high event flag. a_ffmt_xhp X-high event polarity flag. Table 83. A_FFMT_THS register (address 0x17) bit allocation

14.9.4 A_FFMT_ THS_X_MSB, A_FFMT_THS_X_LSB, A_FFMT_THS_Y_MSB,

Table 84. A_FFMT_THS register (address 0x17) bit descriptions of the value of the a_ffmt_ths_xyz_en. interest is momentarily not true. the debounce counter reaches 0 or the inertial event of interest become active. impede the correct detection of inertial events. ths[6:0] Freefall/motion detection threshold: defaul t value: 0b000_0000. Resolution is fixed at 63 mg/LSB. Table 85. A_FFMT_THS_X_MSB register (address 0x73) bit allocation Table 86. A_FFMT_THS_X_MSB register (address 0x73) bit descriptions acceleration threshold has a fixed resolution of 63 mg/LSB, with a range of 0 to 127 counts. A_FFMT_THS_Z_MSB and A_FFMT_THS_Z_LSB for the Z-axis acceleration threshold. a_ffmt_ths_x[12:6] 7-bit MSB of X-axis acceleration threshold. Table 87. A_FFMT_THS_X_LSB register (address 0x74) bit allocation

13-bit threshold (stored in the A_FFMT_X/Y/Z MSB and LSB registers). Table 88. A_FFMT_THS_Y_MSB register (address 0x75) bit allocation Table 89. A_FFMT_THS_Y_LSB register (address 0x76) bit allocation Table 90. A_FFMT_THS_Y_MSB register (address 0x77) bit allocation Table 91. A_FFMT_THS_Z_LSB register (address 0x78) bit allocation

14.9.5 A_FFMT_COUNT register (address 0x18)

before the interrupt is triggered. the time-step values shown in Table 94. effective debounce response time will be 300 ms for the same settings. Table 92. A_FFMT_COUNT register (address 0x18) bit allocation Table 93. A_FFMT_COUNT register (address 0x18) bit description condition of interest is momentarily not true. Table 94. A_FFMT_COUNT relationship with the ODR

Product data sheet Rev. 7.0 — 22 March 2016 69 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer

14.10 Accelerometer vector-ma gnitude function register

The accelerometer vector-magnitude function is an inertial event detection function available to assist host software algorithms in detecting motion events. If > A_VECM_THS for a time period greater than the value stored in A_VECM_CNT, the vector-magnitude change event flag is triggered. a_x_out, a_y_out, and a_z_out are the current accelerometer output values, and a_x_ref, a_y_ref, and a_z_ref are the reference values stored internally in the ASIC for each axis or in A_VECM_INIT_X/Y/Z registers if A_VECM_CFG[a_vecm_initm] is set. Please note that the x_ref, y_ref, and z_ref values are not directly visible to the host application through the register interface. Please refer to NXP application note AN4458. Fig 17. Behavior of the A_FFMT debounce counte r in relation to the a_ffmt_dbcntm setting Low-g Event on Count Threshold EA all 3-axis FF Counter Low-g Event on Count Threshold (a) all 3-axis Debounce Counter Low-g Event on Count Threshold EA all 3-axis a_ffmt_dbcntm = 1 (b) EA a_ffmt_dbcntm = 0 (c)Debounce Counter

14.10.1 A_VECM_CFG register (address 0x5F)

14.10.2 A_VECM_THS_MSB (address 0x60) register

Table 95. A_VECM _CFG register (address 0x5F) bit allocation Table 96. A_VECM_CFG register (address 0x5F) bit descriptions flag is controlled by the A_VECM_CNT register’s programmed debounce time. a_vecm_initm Control bit a_vecm_initm defines how the initia l reference values (x_ref, y_ref, and z_ref) are chosen. when the vector-magnitude function is enabled. function has been triggered. accelerometer output data values. Note: The vector-magnitude function will only perform correctly up to a maximum ODR of 400 Hz. Table 97. A_VECM_THS_MSB register (address 0x60) bit allocation

14.10.3 A_VECM_THS_LSB register (address 0x61)

14.10.4 A_VECM_CNT register (address 0x62)

40 ms. Note that ODR is halved when in hybrid mode.

14.10.5 A_VECM_INITX_MSB register (address 0x63)

Table 98. A_VECM_THS_MSB register (address 0x60) bit descriptions the interrupt is no longer true. result is below the programmed threshold value. below the programmed threshold value. Table 99. A_VECM_THS_LSB register (address 0x61) bit allocation Table 100. A_VECM_CNT register (address 0x62) bit allocation Table 101. A_VECM_CNT register (address 0x62) bit description a_vecm_cnt[7:0] Vector-magnitude function debounce count value. Table 102. A_VECM_INITX_MSB regist er (address 0x63) bit allocation Table 103. A_VECM_INITX_MSB regist er (address 0x63) bit description XYZ_DATA_CFG[fs], and is equal to the accelerometer resolution.

14.10.6 A_VECM_INITX_LSB register (address 0x64)

14.10.7 A_VECM_INITY_MSB register (address 0x65)

14.10.8 A_VECM_INITY_LSB register (address 0x66)

14.10.9 A_VECM_INITZ_MSB register (address 0x67)

Table 104. A_VECM_INITX_LSB register (address 0x64) Table 105. A_VECM_INITX_LSB regist er (address 0x64) bit description Table 106. A_VECM_INITY_MSB regist er (address 0x65) bit allocation Table 107. A_VECM_INITY_MSB regist er (address 0x65) bit description XYZ_DATA_CFG[fs], and is equal to the accelerometer resolution. Table 108. A_VECM_INITY_LSB regist er (address 0x66) bit allocation Table 109. A_VECM_INITY_LSB regist er (address 0x66) bit description a_vecm_inity[7:0] LSB of the signed 14-bit initial Y-axis value to be used as ref_y when A_VECM_CFG[a_vecm_initm] = 1. Table 110. A_VECM_INITZ_MSB register (address 0x67) bit allocation

14.10.10 A_VECM_INITZ_LSB register (address 0x68)

14.11 Transient (AC) accelerat ion detection registers

transient detection function to work in a similar manner to the motion detection function. detection function, refer to NXP application note AN4461. Table 111. A_VECM_INITZ_MSB register (address 0x67) bit description XYZ_DATA_CFG[fs], and is equal to the accelerometer resolution. Table 112. A_VECM_INITZ_LSB register (address 0x68) bit allocation Table 113. A_VECM_INITZ_LSB register (address 0x68) bit description

14.11.1 TRANSIENT_CFG register (address 0x1D)

14.11.2 TRANSIENT_SRC register (address 0x1E)

axes and polarity (directional) information. Table 114. TRANSIENT_ CF G register (address 0x1D) bit allocation Table 115. TRANSIENT_ CF G register (address 0x1D) bit descriptions tran_ele Transient event flag latch enable. 0 – Event flag latch disabled: the transient interrupt flag reflects the real-time status of the function. TRANSIENT_SRC register is required to clear the event flag. tran_zefe Z-axis transient event flag enable. 1 – Z-axis event detection enabled. Raise event flag on Z-axis acceleration value greater than threshold. tran_yefe Y-axis transient event flag enable. 1 – Y-axis event detection enabled. Raise event flag on Y-axis acceleration value greater than threshold. tran_xefe X-axis transient event flag enable. 1 – X-axis event detection enabled. Raise event flag on X-axis acceleration value greater than threshold. tran_hpf_byp Transient function high-pass filter bypass. 0 – High-pass filter is applied to accelerometer data input to the transient function. 1 – High-pass filter is not applied to accelerometer data input to the transient function. Table 116. TRANSIENT_SRC register (address 0x1E) bit allocation

be cleared by reading the TRANSIENT_SRC register.

14.11.3 TRANSIENT_THS register (address 0x1F)

Table 117. TRANSIENT_SRC register (address 0x1E) bit descriptions tran_ea Transient event active flag. 0 – No transient event active flag has been asserted. 1 – One or more transient event active flags has been asserted. tran_zef Z-axis transient event active flag. 0 – Z-axis event flag is not active. debounce time specified in TRANS_COUNT. tran_zpol Z-axis event flag polarity. 0 – Z-axis event was above positive threshold value. 1 – Z-axis event was below negative threshold value. tran_yef Y-axis transient event active flag. 0 – Y-axis event flag is not active. debounce time specified in TRANS_COUNT. tran_ypol Y-axis event flag polarity. 0 – Y-axis event was above positive threshold value. 1 – Y-axis event was below negative threshold value. tran_xef X-axis transient event active flag. 0 – X-axis event flag is not active. debounce time specified in TRANS_COUNT. tran_xpol X-axis event flag polarity. 0 – X-axis event was above positive threshold value. 1 – X-axis event was below negative threshold value.

measurement range is fixed at ±4 g, regardless of the settings made in XYZ_DATA_CFG.

14.11.4 TRANSIENT_COUNT register (address 0x20)

the threshold set in TRANSIENT_THS for any of the enabled axes. doubles the time-step values shown in Table 122. Table 118. TRANSIENT_THS register (address 0x1F) bit allocation Table 119. TRANSIENT_THS regist er (address 0x1F) descriptions tr_dbcntm Debounce counter mode selection. 1 – Clears debounce counter when the transient event condition is not true during the current ODR period. Table 120. TRANSIENT_COUNT regist er (address 0x20) bit allocation Table 121. TRANSIENT_COUNT register (address 0x20) bit description tr_count[7:0) Transient function debounce count value. Table 122. TRANSIENT_COUNT relationship with the ODR

effective debounce time of 300 ms.

14.12 Pulse detection registers

14.12.1 PULSE_CFG register (address 0x21)

This register configures the pulse event detection function. Table 122. TRANSIENT_COUNT relationship with the ODR - ¶continued Table 123. PULSE_CFG register (address 0x21) bit allocation Table 124. PULSE_CFG register (address 0x21) bit descriptions specified by the PULSE_LTCY register. end of the time period specified by the PULSE_LTCY register. pls_zdpefe Event flag enable on double-pulse event on Z-axis. pls_zspefe Event flag enable on single-pulse event on Z-axis. pls_ydpefe Event flag enable on double-pulse event on Y-axis.

14.12.2 PULSE_SRC register (address 0x22)

This register indicates the status bits for the pulse detection function. pls_yspefe Event flag enable on single-pulse event on Y-axis. 1 – Raise event flag on detection of single-pulse event on Z-axis. pls_xdpefe Event flag enable on double-pulse event on X-axis. 1 – Raise event flag on detection of double-pulse event on X-axis. pls_xspefe Event flag enable on single-pulse event on X-axis. 1 – Raise event flag on detection of single-pulse event on X-axis. Table 124. PULSE_CFG register (address 0x21) bit descriptions - ¶continued Table 125. PULSE_SRC register (address 0x22) bit allocation Table 126. PULSE_SRC register (address 0x22) bit descriptions pls_src_ea Event active flag. pls_src_axz Z-axis event flag. pls_src_axy Y-axis event flag. pls_src_axx X-axis event flag. 1 – X-axis event has occurred. pls_src_dpe Double pulse on first event.

14.12.3 PULSE_THSX register (address 0x23)

for the pulse detection function, regardless of the settings made in XYZ_DATA_CFG[fs].

14.12.4 PULSE_THSY register (address 0x24)

pls_src_polz Pulse polarity of Z-axis event. 0 – Pulse event that triggered interrupt was positive. 1 – Pulse event that triggered interrupt was negative. pls_src_poly Pulse polarity of Y-axis event. 0 – Pulse event that triggered interrupt was positive. 1 – Pulse event that triggered interrupt was negative. pls_src_polx Pulse polarity of X-axis event. 0 – Pulse event that triggered interrupt was positive. 1 – Pulse event that triggered interrupt was negative. Table 126. PULSE_SRC register (address 0x22) bit descriptions - ¶continued Table 127. PULSE_THSX register (address 0x23) bit allocation Table 128. PULSE_THSX register (address 0x23) bit description pls_thsx[6:0] Pulse threshold for X-axis. Table 129. PULSE_THSY register (address 0x24) bit allocation Table 130. PULSE_THSY register (address 0x24) bit description pls_thsy[6:0] Pulse threshold for Y-axis.

14.12.5 PULSE_THSZ register (address 0x25)

14.12.6 PULSE_TMLT register (address 0x26)

Minimum time step for the pulse-time limit is defined in Table 135 and Table 136. Maximum time for a given ODR is “Minimum time step x 255”. Table 131. PULSE_THSZ register (address 0x25) bit allocation Table 132. PULSE_THSZ register (address 0x24) bit description pls_thsz[6:0] Pulse threshold for Z-axis. Table 133. PULSE_TMLT register (address 0x26) bit allocation Table 134. PULSE_TMLT register (address 0x26) bit description back below the specified threshold. Table 135. Time step for PULSE_TMLT with HP_FILTER_CUTOFF[pls_hpf_en] = 1

CTRL_REG2, would result in a maximum pulse-time limit of (0.625 ms * 255) = 159 ms.

14.12.7 PULSE_LTCY register (address 0x27)

time is (time step @ ODR and power mode) x 255. Table 136. Time step for PULSE_TMLT with HP_FILTER_CUTOFF[pls_hpf_en] = 0 Table 137. PULSE_LTCY register (address 0x27) bit allocation Table 138. PULSE_LTCY register (address 0x27) bit description function ignores the start of a new pulse. Table 139. Time step for PULSE_LTCY with HP_FILTER_CUTOFF[pls_hpf_en] = 1

14.12.8 PULSE_WIND register (address 0x28)

double the time-step value from what is shown in Table 143 and Table 144. Table 140. Time step for PULSE_LTCY with HP_FILTER_CUTOFF[pls_hpf_en] = 0 Table 141. PULSE_WIND register (address 0x28) bit allocation Table 142. PULSE_WIND register (address 0x28) bit description specified by the PULSE_WIND register. Table 143. Time step for PULSE_WIND with HP_FILTER_CUTOFF[pls_hpf_en] = 1

14.13 Accelerometer offset correction registers

14.13.1 OFF_X register (address 0x2F)

Table 144. Time step for PULSE_WIND with HP_FILTER_CUTOFF[pls_hpf_en] = 0 Table 145. OFF_X register (address 0x2F) bit allocation Table 146. OFF_X register (address 0x2F) bit description off_x[7:0] X-axis offset correction value ex pressed as an 8-bit 2's complement number.

14.13.2 OFF_Y register (address 0x30)

14.13.3 OFF_Z register (address 0x31)

14.14 Magnetometer data registers

14.14.1 M_DR_STATUS register (address 0x32)

Magnetic data-ready status register. Table 147. OFF_Y register (address 0x30) bit allocation Table 148. OFF_Y register (address 0x30) bit description off_y[7:0] Y-axis offset correction value expressed as an 8-bit 2's complement number. Table 149. OFF_Z register (a ddress 0x31) bit allocation Table 150. OFF_Z register (a ddress 0x31) bit description off_z[7:0] Z-axis offset correction value expr essed as an 8-bit 2's complement number. Table 151. M_DR_STATUS register (address 0x32) bit allocation

Table 152. M_DR_STATUS register (address 0x32) bit descriptions magnetometer data (M_OUT_X_MSB, M_OUT_Y_MSB, and M_OUT_Z_MSB) are read. zow zow is set to 1 whenever a new Z-axis acquisition is completed before the retrieval of the previous data. yow yow is set to 1 whenever a new Y-axis acquisition is completed before the retrieval of the previous data. When this occurs the previous data is overwritten. yow is cleared anytime M_OUT_Y_MSB register is read. xow xow is set to 1 whenever a new X-axis acquisition is completed before the retrieval of the previous data. 0 – No new X-axis magnetic data is available.

numbers, with a resolution of 0.1 μT/LSB. Table 153. M_OUT_X_MSB register (address 0x33) bit allocation Table 154. M_OUT_X_LSB register (address 0x34) bit allocation Table 155. M_OUT_Y_MSB register (address 0x35) bit allocation Table 156. M_OUT_Y_LSB register (address 0x36) bit allocation Table 157. M_OUT_Z_MSB register (address 0x37) bit allocation Table 158. M_OUT_Z_LSB register (address 0x38) bit allocation

14.14.3 CMP_X_MSB (address 0x39), CMP_X_LSB, CMP_Y_MSB, CMP_Y_LSB,

Table 159. CMP_X_MSB register (address 0x39) bit allocation Table 160. CMP_X_LSB register (address 0x3A) bit allocation Table 161. CMP_Y_MSB register (address 0x3B) bit allocation Table 162. CMP_Y_LSB register (address 0x3C) bit allocation Table 163. CMP_Z_MSB register (address 0x3D) bit allocation Table 164. CMP_Z_LSB register (address 0x3E) bit allocation

14.14.4 MAX_X_MSB, MAX_X_LSB, MA X_Y_MSB, MAX_Y_LSB, MAX_Z_MSB

(MAX_X/Y/Z + MIN_X/Y/Z) /2 when M_CTRL_REG2[maxmin_dis] = 0 (default). loaded with the hex value 0x8000 (negative full scale). at the end of the next measurement cycle (ODR period). Table 165. MAX_X_MSB register (address 0x45) bit allocation Table 166. MAX_X_LSB register (address 0x46) bit allocation Table 167. MAX_Y_MSB register (address 0x47) bit allocation Table 168. MAX_Y_LSB register (address 0x48) bit allocation Table 169. MAX_Z_MSB register (address 0x49) bit allocation

14.14.5 MIN_X_MSB, MIN_X_LSB, MIN_Y_MSB, MIN_Y_LSB, MIN_Z_MSB

(MAX_X/Y/Z + MIN_X/Y/Z) /2 when M_CTRL_REG2[maxmin_dis] = 0 (default). Table 170. MAX_Z_LSB register (address 0x4A) bit allocation Table 171. MIN_X_MSB register (address 0x4B) bit allocation Table 172. MIN_X_LSB register (address 0x4C) bit allocation Table 173. MIN_Y_MSB register (address 0x4D) bit allocation Table 174. MIN_Y_LSB register (address 0x4E) bit allocation

14.15 Magnetometer offset correction registers

14.15.1 M_OFF_X_MSB (address 0x3F), M_OFF_X_LSB, M_OFF_Y_MSB,

any effect on the magnetic output data. and with an effective offset adjustment range of –1638.4 μT to +1638.3 μT. following a left-shift for proper alignment (0x0258<<1 = 0x04b0). Table 175. MIN_Z_MSB register (address 0x4F) bit allocation Table 176. MIN_Z_LSB register (address 0x50) bit allocation Table 177. M_OFF_X_MSB register (address 0x3F) bit allocation Table 178. M_OFF_X_LSB register (address 0x40) bit allocation

14.16 Magnetometer thresh old function registers

in MAG_THS_COUNT before the event flag is triggered.

14.16.1 M_THS_CFG register (address 0x52)

Magnetic-field threshold detection configuration register. Table 179. M_OFF_Y_MSB register (address 0x41) bit allocation Table 180. M_OFF_Y_LSB register (address 0x42) bit allocation Table 181. M_OFF_Z_MSB register (address 0x43) bit allocation Table 182. M_OFF_Z_LSB register (address 0x44) bit allocation Table 183. M_THS_CFG register (address 0x52) bit allocation

enabled axes are below or equal to their respective threshold values (AND condition). is above or equal to their respective threshold value (OR condition). the application software running on the MCU. Table 184. M_THS_CFG register (address 0x52) bit descriptions m_ths_ele Magnetic-threshold event latch enable. state with the real-time status of the event detection logic. cleared by reading the M_THS_SRC register. m_ths_oae Magnetic-threshold event logic selection. 0 – Logical “AND” of enabled axes X, Y, and Z below threshold flags is used to detect the event. 1 – Logical “OR” of enabled axes X, Y, and Z above threshold flags is used to detect the event. m_ths_zefe Event-flag enable on Z-axis. m_ths_yefe Event-flag enable on Y-axis. m_ths_xefe Event-flag enable on X-axis. 1 – The system includes the magnetic-threshold event flag when evaluating the auto-sleep/wake function. m_ths_int_en 0 – Magnetic-threshold interrupt is disabled. 1 – Magnetic-threshold interrupt is enabled.

14.16.2 M_THS_SRC register (address 0x53)

Magnetic-threshold interrupt source register. magnetic-event flags specified in M_THS_CFG is true.

0 Field

Table 185. M_THS_SRC register (address 0x53) bit allocation Table 186. M_THS_SRC register (address 0x53) bit descriptions 1 – One or more event flag(s) has been asserted. m_ths_zhe Z-high event flag. m_ths_zhp Z-high event polarity flag.

m_ths_yhe Y-high event flag. m_ths_yhp Y-high event polarity flag. m_ths_xhe X-high event flag. m_ths_xhp X-high event polarity flag. 1 – X event detected was negative polarity. Table 187. M_THS_X_MSB register (address 0x54) bit allocation Table 188. M_THS_X_MSB register (address 0x54) bit descriptions event of interest is momentarily not true. m_ths_x[14:8] Upper 7 bits of the 15-bit unsigned X-axis magnetic threshold.

14.16.4 M_THS_COUNT register (address 0x5A)

Table 189. M_THS_X_LSB register (address 0x55) bit allocation Table 190. M_THS_Y_MSB register (address 0x56) bit allocation Table 191. M_THS_Y_LSB register (address 0x57) bit allocation Table 192. M_THS_Z_MSB register (address 0x58) bit allocation Table 193. M_THS_Z_LSB register (address 0x59) bit allocation Table 194. M_THS_COUNT register (address 0x5A) bit allocation Table 195. M_THS_COUNT register (address 0x5A) bit description m_ths_cnt[7:0] Magnetic thre shold debounce count value.

value. The time step used for the debounce sample count depends on the chosen ODR. debounce response time of 300 ms. Table 196. M_THS_COUNT relationship with the ODR

800 N/A N/A

14.17 Magnetometer control registers

14.17.1 M_CTRL_REG1 register (address 0x5B)

Table 197. M_CTRL_REG1 register (address 0x5B) bit allocation

CTRL_REG1[dr] and CTRL_REG1[aslp_rate] bit fields. determines the magnetic output data update rate. CMP_Y_LSB (0x3C), CMP_Z_MSB (0x3D), and CMP_Z_LSB (0x3E).

• Configure the device into standby mode.
• Continously poll the SYSMOD (0x0B) register to check whether the device has gone to standby mode.

14.17.2 M_CTRL_REG2 register (address 0x5C)

Table 198. M_CTRL_REG1 register (address 0x5B) bit descriptions (MAX_X/Y/Z + MIN_X/Y/Z)/2 for each axis at the end of every ODR cycle. 1 – One-shot magnetic reset is enabled, hardware cleared when complete. 0 – No action taken, or one-shot measurement complete. magnetic measurements, clear this bit, and return to standby mode. Table 199. M_CTRL_REG2 register (address 0x5C) bit allocation

14.17.3 M_CTRL_REG3 register (address 0x5D)

Table 200. M_CTRL_REG2 register (address 0x5C) bit descriptions the register map auto-increment address column for further information. 0 – Magnetic min/max detection function is enabled (default). 1 – Magnetic min/max detection function is disabled. hardware based hard-iron offset compensation function. 0b00 – Automatic magnetic reset at the beginning of each ODR cycle (default). 0b01 – Automatic magnetic reset every 16 ODR cycles. 0b10 – Automatic magnetic reset every 512 ODR cycles. Table 201. M_CTRL_REG3 register (address 0x5D) bit allocation

14.17.4 M_INT_SRC register (address 0x5E)

Table 202. M_CTRL_REG3 register (address 0x5D) bit descriptions must be cleared in order for the automatic hard-iron compensation function to have any effect. hard-iron compensation function does not have any effect on the output data. m_aslp_os[2:0] Defines magnetometer OSR in auto-sleep mode. See Table 203. detection function triggers. 1 – Only the reference value for the axis that triggered the detection event is updated. Table 203. M-cell OSR versus ODR Table 204. M_INT_SRC register (address 0x5E) bit allocation Table 205. M_INT_SRC register (address 0x5E) bit description 0 – Magnetic threshold event has not been detected. 1 – Magnetic threshold event has been detected. 0 – Magnetic vector-magnitude change event has not been detected. 1 – Magnetic vector-magnitude change event has been detected. 0 – No new magnetic data is available. 1 – New magnetic data is available.

14.18 Magnetometer vector-magni tude function registers

magnetic vectors greater than the preset threshold (with reference values non-zero). through the register interface. Refer to NXP application note AN4458.

14.18.1 M_VECM_CFG register (address 0x69)

Table 206. M_VECM_CFG register (address 0x69) bit allocation Table 207. M_VECM_CFG register (a ddress 0x69) bit descriptions time and may be cleared by the ASIC prior to the user reading the flag. at the time the m_vecm_en bit is set. 1 – The function does not update the reference values when the event is triggered. values using the M_VECM_INIT_X/Y/Z registers in real time when the function is enabled.

14.18.2 M_VECM_THS_MSB register (address 0x6A)

14.18.3 M_VECM_THS_LSB register (address 0x6B)

0 – The system excludes the src_m_vecm event flag when evaluating the auto-sleep function. 1 – The system includes the src_m_vecm event flag when evaluating the auto-sleep function. 0 – Magnetic vector-magnitude interrupt is disabled. 1 – Magnetic vector-magnitude interrupt is enabled. 0 – Magnetic vector-magnitude interrupt is output on INT2 pin. 1 – Magnetic vector-magnitude interrupt is output on INT1 pin. Table 207. M_VECM_CFG register (a ddress 0x69) bit descriptions - ¶continued Table 208. M_VECM_THS_MSB register (address 0x6A) bit allocation Table 209. M_VECM_THS_MSB register (address 0x6A) bit descriptions below the threshold set in M_VECM_THS. threshold set in M_VECM_THS. Table 210. M_VECM_THS_LSB register (address 0x6B) bit allocation

14.18.4 M_VECM_CNT register (address 0x6C)

40 ms. Note that ODR is halved when in hybrid mode.

14.18.5 M_VECM_INITX_MSB register (address 0x6D)

14.18.6 M_VECM_INITX_LSB register (address 0x6E)

Table 211. M_VECM_CNT register (address 0x6C) bit allocation Table 212. M_VECM_CNT register (address 0x6C) bit description m_vecm_cnt[7:0] Vector-magnitude debounce count value. Table 213. M_VECM_INITX_MSB register (address 0x6D) bit allocation Table 214. M_VECM_INITX_MSB register (address 0x6D) bit description M_VECM_CFG[m_vecm_initm] = 1. Table 215. M_VECM_INITX_LSB register (address 0x6E) bit allocation Table 216. M_VECM_INITX_LSB register (address 0x6E) bit description M_VECM_CFG[m_vecm_initm] = 1.

14.18.7 M_VECM_INITY_MSB register (address 0x6F)

14.18.8 M_VECM_INITY_LSB register (address 0x70)

14.18.9 M_VECM_INITZ_MSB register (address 0x71)

14.18.10 M_VECM_INITZ_LSB register (address 0x72)

Table 217. M_VECM_INITY_MSB register (address 0x6F) bit allocation Table 218. M_VECM_INITY_MSB register (address 0x6F) bit description M_VECM_CFG[m_vecm_initm] = 1. Table 219. M_VECM_INITY_LSB register (address 0x70) bit allocation Table 220. M_VECM_INITY_LSB register (address 0x70) bit description M_VECM_CFG[m_vecm_initm] = 1. Table 221. M_VECM_INITZ_MSB register (address 0x71) bit allocation Table 222. M_VECM_INITZ_MSB register (address 0x71) bit description M_VECM_CFG[m_vecm_initm] = 1. Table 223. M_VECM_INITZ_LSB register (address 0x72) bit allocation Table 224. M_VECM_INITZ_LSB register (address 0x72) bit description M_VECM_CFG[m_vecm_initm] = 1.

Product data sheet Rev. 7.0 — 22 March 2016 105 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer 15. Package outline This drawing is located at http://cache.nxp.com/files/shared/doc/package_info/98ASA00318D.pdf. Fig 20. Package outline 16-lead QFN, 3 mm x 3 mm x 1.2 mm

Product data sheet Rev. 7.0 — 22 March 2016 106 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer Fig 21. Package outline 16-lead QFN, 3 mm x 3 mm x 1.2 mm

Product data sheet Rev. 7.0 — 22 March 2016 107 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer Fig 22. Package outline 16-lead QFN, 3 mm x 3 mm x 1.2 mm

Product data sheet Rev. 7.0 — 22 March 2016 108 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer 16. Packing information 17. Mounting guidelines for the quad flat no-lead (QFN) package

17.1 Soldering information

The QFN package is compliant with the RoHS standards. Refer to NXP application note AN4077 for more information. Printed circuit board (PCB) layout is a critical portion of the total design. The footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the PCB and the package. With the correct footprint, the packages will self-align when subjected to a solder reflow process. These guidelines are for soldering and mounting the quad flat no-lead (QFN) package inertial sensors to PCBs. The purpose is to minimize the stress on the package after board mounting. The FXOS8700CQ uses the QFN package platform. This section describes suggested methods of soldering these devices to the PCB for consumer applications. Refer to NXP application note AN4247,”Layout Recommendation for PCBs Using a Magnetometer Sensor” for a technical discussion on hard and soft-iron magnetic interference and general guidelines on layout and component selection applicable to any PCB using a magnetometer sensor. NXP application note AN1902, “Quad Flat Pack No-Lead (QFN) Micro Dual Flat Pack No-Lead (DFN)” discusses the QFN package used by the FXOS8700CQ, PCB design guidelines for using QFN packages and temperature profiles for reflow soldering.

17.2 Overview of soldering considerations

Information provided here is based on experiments executed on QFN devices. As they cannot represent exact conditions present at a customer site, the information provided herein should be used for guidance only and further process and design optimizations are Fig 23. Tape and reel

Product data sheet Rev. 7.0 — 22 March 2016 109 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer recommended to develop an application specific solution. It should be noted that with the proper PCB footprint and solder stencil designs, the package will self-align during the solder reflow process. The QFN package is compliant with the RoHS standards. Please refer to NXP application note AN4077 for more information.

17.3 Halogen content

This package is designed to be Halogen free, exceeding most industry and customer standards. Halogen free means that no homogeneous material within the assembled package will contain chlorine (Cl) in excess of 700 ppm or 0.07% weight/weight or bromine (Br) in excess of 900 ppm or 0.09% weight/weight.

17.4 PCB mounting recommendations

• The PCB land should be designed with non-solder mask defined (NSMD) as shown in Figure 24 and Figure 25.
• No additional via pattern underneath package.
• PCB land pad is 0.8 mm by 0.3 mm as shown in Figure 24 and Figure 25.
• Solder mask opening = PCB land pad edge + 0.113 mm larger all around.
• Stencil opening = PCB land pad –0.015 mm smaller all around = 0.77 mm by 0.27 mm.
• Stencil thickness is 100 or 125 μm.
• Do not place any components or vias at a distance less than 2 mm from the package land area. This may cause additional package stress if it is too close to the package land area.
• Signal traces connected to pads should be as symmetric as possible. Put dummy traces on the NC pads in order to have same length of exposed trace for all pads.
• Use a standard pick and place process and equipment. Do not use a hand soldering process.
• Do not use a screw down or stacking to fix the PCB into an enclosure as this could bend the PCB, putting stress on the package.
• The PCB should be rated for the multiple lead-free reflow condition with max 260 °C temperature.
• No copper traces on top layer of PCB under the package. This will cause planarity issues with board mount. NXP QFN sensors are compliant with Restrictions on Hazardous Substances (RoHS), having halide-free molding compound (green) and lead-free terminations. These terminations are compatible with tin-lead (Sn-Pb) as well as tin-silver-copper (Sn-Ag-Cu) solder paste soldering processes. Reflow profiles applicable to those processes can be used successfully for soldering the devices.

Product data sheet Rev. 7.0 — 22 March 2016 110 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer Fig 24. Recommended PCB land pattern, solder mask, and stencil opening near package footprint Package footprint0.467mm x 0.25mm Package Footprint P C BL a n dP a t t e r n&S t e n c i l Stencil opening = PCB land pad -0.015mm smaller all around = 0.77mm x 0.27mm Solder mask opening = PCB land pad edge + 0.113mm larger all around PCB land pad = 0.8mm x 0.3mm 0.567 mm x 0.25 mm No copper in this area Fig 25. Detailed dimensions

1. Package thermal characteristics

on the board, and board thermal resistance. [2] Per JEDEC JESD51-2 with the si ngle-layer board (JESD51-3) horizontal. [3] Per JEDEC JESD51-6 with t he board (JESD51-7) horizontal. is measured on the top surface of the board near the package. characterization parameter is written as Psi-JT. Table 225. Thermal resistance data

Table 226. Revision history

• Updated bullets in Section 2, features and benefits and Section 3, applications.
• Section 9.5: Table 8, updated value on maximum exposed magnetic field without perming row; was 10,000 to 3000.
• Section 14: Table 16, added and deleted footnote references.
• Section 14.1.5: Table 28, corrected description for sysmod[1:0] was “0b01: Sleep mode” to “0b10: Sleep mode”.
• Section 14.1.9: Table 37, updated description for rst, changing parts of paragraphs to a “Note”.
• Section 14.9.4: Table 86, corrected description for a_ffmt_ths_xyz_en
• Section 14.17.1: Updated NOTE following Table 198.
• Added Section 16, Packing information. FXOS8700CQ v.6.0 20150918 Product data sheet - FXOS8700CQ v.5.0 FXOS8700CQ v.5.0 20150527 Product data sheet - FXOS8700CQ v.4.1 FXOS8700CQ v.4.1 20150113 Product data sheet - FXOS8700CQ v.4.0 FXOS8700CQ v.4.0 20140305 Product data sheet - FXOS8700CQ v.3 FXOS8700CQ v.3 20130719 Product data sheet - FXOS8700CQ v.2 FXOS8700CQ v.2 20130511 Product data sheet - FXOS8700CQ v.1 FXOS8700CQ v.1 20120616 Advance information - -

Product data sheet Rev. 7.0 — 22 March 2016 113 of 113 NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer 20. Legal information

20.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Document status[1] Product status[2] Definition Product preview Development This document contains certain information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Advance information Qualification This document contains informati on on a new product. Specifications and information herein are subject to change without notice. Technical data Production NXP Semic onductors reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

Product data sheet Rev. 7.0 — 21 March 2016 114 of 116 continued >> NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer 21. Contents 10.1 I 10.2.3 I

10.2.4 Power supply sequencing and I 2C/SPI mode

12.3 Accelerometer lo w-power modes versus

12.13 Magnetic min/max detection (autonomous

14.1.10 CTRL_REG3 - interrupt control register (address

14.1.11 CTRL_REG4 - interrupt enable register (address

14.1.12 CTRL_REG5 - interrupt routing configuration

14.4.1 OUT_X_MSB, OU T_X_LSB, OUT_Y_MSB,

OUT_Y_LSB, OUT_Z_MSB, OUT_Z_LSB

14.7.1 HP_FILTER_CUTOFF register (address 0x0F) 57

Product data sheet Rev. 7.0 — 21 March 2016 115 of 116 continued >> NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer

14.9.4 A_FFMT_ THS_X_M SB, A_FFMT_THS_X_LSB,

14.10.2 A_VECM_THS_MSB (address 0x60) register 70

14.10.3 A_VECM_THS_LSB register (address 0x61). 71

14.10.5 A_VECM_INITX_MSB register (address 0x63) 71

14.10.6 A_VECM_INITX_LSB register (address 0x64) 72

14.10.7 A_VECM_INITY_MSB register (address 0x65) 72

14.10.8 A_VECM_INITY_LSB register (address 0x66) 72

14.10.9 A_VECM_INITZ_MSB register (address 0x67) 72

14.10.10 A_VECM_INITZ_LSB register (address 0x68) 73

14.11 Transient (AC) acceleration detection registers

14.11.1 TRANSIENT_CFG register (address 0x1D) . 74 14.11.2 TRANSIENT_SRC register (address 0x1E) . . 74 14.11.3 TRANSIENT_THS register (address 0x1F) . . 75

14.11.4 TRANSIENT_COUNT register (address 0x20) 76

14.14.2 M_OUT_X_M SB, M_OUT_X_LSB,

M_OUT_Z_MSB, M_OUT_Z_LSB registers

14.14.3 CMP_X_MSB (addre ss 0x39), CMP_X_LSB,

CMP_Y_MSB, CMP_Y_LSB, CMP_Z_MSB, CMP_Z_LSB (addresses 0x3A to 0x3E) registers

14.14.4 MAX_X_MSB, M AX_X_LSB, MAX_Y_MSB,

MAX_Y_LSB, MAX_Z_MSB (addresses 0x45 to 0x49), MAX_Z_LSB (address 0x4A) registers 88

14.14.5 MIN_X_MSB, MIN_X_LSB, MIN_Y_MSB,

MIN_Y_LSB, MIN_Z_MSB (addresses 0x4B to 0x4F), MIN_Z_LSB (address 0x50) registers 89

14.15.1 M_OFF_X_MSB (address 0x3F),

M_OFF_Z_LSB (addresses 0x40 to 0x44) 14.16 Magnetometer threshold function registers . . 91

14.16.3 M_THS_X_M SB, M_THS_X_LSB,

M_THS_Z_MSB, M_THS_Z_LSB (addresses

14.18 Magnetometer vector-magnitude function

14.18.3 M_VECM_THS_LSB register (address 0x6B) 102

NXP Semiconductors FXOS8700CQ 6-axis sensor with integrated linear accelerometer and magnetometer © NXP B.V. 2016. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 21 March 2016 Document identifier: FXOS8700CQ Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

17 Mounting guidelines for the quad flat no-lead

Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support NXP , the NXP logo, Freescale, and the Freescale logo, are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © 2016 NXP B.V. Document Number: FXOS8700CQ Rev. 7.0