FXOS8700CQ FREESCALE | Alldatasheet
Document overview
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- PDF pages: 86
Technical content
Datasheet sections
- 1 Block Diagram
- 2 Pin Description
- 2.1 Soldering information
- 2.2 Orientation
- 3 Terminology
- 3.1 Sensitivity
- 3.2 Zero-g and Zero-Flux offset
- 3.3 Self-Test
- 4 Device Characteristics
- 4.1 Mechanical characteristics (accelerometer)
- 4.2 Magnetic characteristics (magnetometer)
- 4.3 Hybrid characteristics
- 4.4 Electrical characteristics
- 4.5 Absolute maximum ratings
- 5 Digital Interfaces
- 5.1 I 2C interface characteristics
- 5.2 SPI Interface characteristics
- 6 Modes of Operation
- 7 Embedded Functionality
- 7.1 Factory calibration
- 7.3 Accelerometer low-power modes versus high-resolution modes
- 7.4 Auto-Wake/Sleep mode
- 7.5 Hybrid mode
- 7.6 Accelerometer Freefall and Motion event detection
- 7.7 Transient detection
- 7.8 Pulse detection
- 7.9 Orientation detection
- 7.10 Acceleration Vector Magnitude detection
- 7.11 Magnetic Vector Magnitude detection
- 7.12 Magnetic Threshold detection
- 7.13 Magnetic Min/Max detection (autonomous calibration)
- 8 Register Map
- 9 Registers by Functional Blocks
- 9.1 Device configuration
- 9.2 Auto-Sleep trigger
- 9.3 Temperature
- 9.4 Accelerometer output data registers
- 9.5 Accelerometer FIFO
- 9.6 Accelerometer sensor data configuration
- 9.7 Accelerometer High-Pass filter
- 9.8 Portrait/Landscape Detection
- 9.9 Freefall and Motion detection
- 9.10 Accelerometer vector magnitude function
- 9.11 Transient (AC) acceleration detection
- 9.12 Pulse detection
- 9.13 Accelerometer offset correction
- 9.14 Magnetometer data registers
- 9.15 Magnetometer offset correction
- 9.16 Magnetometer threshold function
- 9.17 Magnetometer control registers
- 10 Mounting Guidelines for the Quad Flat No Lead (QFN) Package
- 10.1 Overview of soldering considerations
- 10.2 Halogen content
- 10.3 PCB mounting recommendations
- 11 Package
Features
- 1.95V to 3.6V VDD supply volt age, 1.62V to 3.6 VDDIO voltage
- ±2g/±4g/±8g dynamically selectable acceleration full-scale range
- ±1200 µT magnetic sensor full-scale range
- Output Data Rates (ODR) from 1.563 Hz to 800 Hz for each sensor, and up to
400 Hz when operated in hybrid mode with both sensors active
- Low noise: < 150 μg/√Hz acceleration, < 1 μT rms magnetic
- 14-bit resolution for acceleration measurements
- 16-bit resolution for magnetic measurements
- Footprint compatible with Xtrinsic MMA8451, 2, 3
- Embedded programmable acceleration event functions: — Freefall and Motion Detection — Transient Detection — Vector-Magnitude Change Detection — Pulse and Tap Detection (Single and Double) — Orientation Detection (Portrait/Landscape)
- Embedded programmable magnetic event functions: — Threshold Detection — Vector-Magnitude Change Detection — Autonomous Magnetic Min/Max Detection — Autonomous Hard -Iron Calibration
- Programmable automatic ODR change using Auto-Wake and return to Sleep functions to save power. This function works with both magnetic and acceleration event interrupt sources.
- 32-sample FIFO for acceleration data only
- Integrated accelerometer and magnetometer self-test functions Target Markets
- Smart phones, tablets, personal navigation devices, roboti cs, UAVs, and wrist watches with embedded electronic compass (eCompass) function.
- Medical applications: patient monitoring, fall detection, and rehabilitation 1VDDIO 16 15 14 BYP Reserved SCL/SCLK GND Reserved GND INT1 SA1/CS_B INT2 SDA/MOSI SA0/MISO Crst RST N/C VDD
16 LEAD QFN
3 mm by 3 mm by 1.2 mm FXOS8700CQ Top View Pin Connections FXOS8700CQ
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Applications
- eCompass in mo bile devices
- User interface (menu scrolling by orientation change, tap detection for button replacement)
- Orientation detection (portrait/landscape: up/down, left/right, back/fron t position identification)
- Augmented Reality (AR), gaming, and real-tim e activity analysis (pedometry, freefall and drop detection for hard disk drives and other devices)
- Power management for mobile devices us ing inertial and magnetic event detection
- Shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging) Related Documentation The FXOS8700CQdevice features and operations are described in a variety of reference manuals, user guides, and application notes. To find the most-current versions of these documents: 1. Go to the Freescale homepage at: http://www.freescale.com/ 2. In the Keyword search box at the top of the page, enter the device number FXOS8700CQ. In the Refine Your Result pane on the left, click on the Documentation link.
ORDERING INFORMATION
Part Number Temperature Range Package Description Shipping FXOS8700CQR1 -40°C to +85°C QFN Tape and Reel
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1 Block Diagram
Figure 1. Block diagram
2 Pin Description
Figure 2. Pinout diagram 100 nF ceramic capacitor placed as close as possible to pin 1 of the device. removed, these pins will clamp any logic signals through their internal ESD protection diodes. Table 1. Pin Description
1 VDDIO Interface power supply
2 BYP Internal regulator output bypass capacitor connection
3 Reserved Test reserved, connect to GND
5 GND Ground
7 SA0/MISO I 2C address selection bit 0(1)/SPI Master In, Slave Out
- See Table 9 for I2C address options selectable using the SA0 and SA1 pins.
8 Crst Magnetic reset cap
9 INT2 Interrupt 2
10 SA1/CS_B I 2C address selection bit 1(1)/SPI Chip Select (active low)
11 INT1 Interrupt 1
12 GND Ground
13 Reserved Test reserved, connect to GND
14 VDD Power supply
15 N/C Internally not connected
16 Lead QFN-COL
6 Freescale Semiconductor, Inc. and SCL I2C connections are open drain and therefore require a pullup resistor as shown in the application diagram in Figure 3. Figure 3. Electrical connection
2.1 Soldering information
pins are configured for push/pull (default) operation. required if the device is operated in SPI Interface mode.
2.2 Orientation
Figure 4. Product orientation and axis orientation
8 Freescale Semiconductor, Inc. 3T e r m i n o l o g y
3.1 Sensitivity
Sensitivity is represented in mg/LSB for the accelerometer and μT/LSB for the magnetometer. The magnetometer sensitivity is fixed at 0.1 μT/LSB. The accelerometer sensitivity changes with the full-scale range selected by the user. Accelerometer sensitivity is 0.244 mg/LSB in 2g mode, 0.488 mg/LSB in 4g mode, and 0.976 mg/LSB in 8g mode.
3.2 Zero-g and Zero-Flux offset
For the accelerometer, zero-g offset (TyOff) describes the deviation of the output values from the ideal values when the sensor is stationary. With an accelerometer stationary on a level horizontal surface, the ideal output is 0g for the X and Y axes, and 1g for the Z-axis. The deviation of each axes output from the ideal value is called zero-g offset. Offset is to some extent a result of stress on the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. For the magnetometer, zero-flux offset describes the deviation of the output signal from zero when the device is shielded from external magnetic field sources (i.e. inside a zero-gauss chamber).
3.3 Self-Test
Self-Test can be used to verify the accelerometer and magnetometer transducer functionality without the need for an external acceleration or magnetic field stimulus. When the accelerometer self-test is activated, an electrostatic actuation force is applied to the sensor, simulating a small acceleration. In this case the sensor X, Y, Z outputs will exhibit a change in DC levels related to the selected full-scale range (sensitivity). When self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic self-test force. When self-test is activated for the magnetometer, an internal magnetic field is generated along the X, Y and Z axes. The sensor response will be the sum of the ambient magnetic field and the self-test induced field.
4 Device Characteristics
4.1 Mechanical characteristics (accelerometer)
Table 2. Mechanical characteristics @ VDD = 2.5V, VDDIO = 1.8V T = 25°C unless otherwise noted.
- Dynamic range is limited to ±4g when in the low-noise mode.
4096 LSB/g
2048 LSB/g
1024 LSB/g
- Sensitivity remains in spec as stated, but changing the oversampling mode to low power causes a 3% sensitivity shift. This behavior is also
seen when changing from 800 Hz ODR to any other ODR in the normal, low-noise + low-power, or high-resolution modes.
- Post-board mount offset specifications are based on an 8-layer PCB.
- Self-test is only exer cised along one direction for each sensitive axis.
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4.2 Magnetic character istics (magnetometer)
Table 3. Magnetic characteristics @ VDD = 2.5V, VDDIO = 1.8V T = 25°C unless otherwise noted.
- After m-cell has been trimmed .
- Hysteresis is measured by sweepi ng the applied magnetic field from -1500 μT to 1500 μT and then back to -1500 μT. The difference in the
two readings at -1500 μT divided by the swept field range is the hysteresis figure, expressed in % of the full-scale range (FS).
- Over a ±300 μT sliding window within the full-scale range.
- Verified by characterization.
4.3 Hybrid characteristics
4.4 Electrical characteristics
Table 4. Hybrid characteristics @ VDD = 2.5V, VDDIO = 1.8V T = 25°C unless otherwise noted. Table 5. Electrical characteristics @ VDD = 2.5V, VDDIO = 1.8V T = 25°C unless otherwise noted.
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4.5 Absolute maximum ratings
extended periods may affect device reliability.
- Time from VDDIO on and VDD > VDD min until I 2C ready for operation.
- Time to obtain valid data from Standby mode to Active mode.
- Time to obtain valid data from power-down condition.
Table 6. Maximum ratings Table 7. ESD and latchup protection characteristics This device is sensitive to ESD, improper handling can cause permanent damage to the part.
5 Digital Interfaces
5.1 I 2C interface characteristics
Figure 5. I2C slave timing diagram Table 8. I2C slave timing values(1)
- All values referred to VIH (min) and VIL (max) levels.
- This device does not stretch the LOW period (t LOW) of the SCL signal.
- t VD;DAT = time for Data signal from SCL LOW to SDA output.
- t VD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
- C b = total capacitance of one bus line in pF.
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5.1.1 General I 2C operation
data line while the SCL line is held HIGH. After the ST signal has been transmitted by the master, the bus is considered busy. remains stable low during the high period of the acknowledge clock period. support clock stretching. Not all master devices recognize clock stretching. This part does not use clock stretching. the logic level of the SA1 and SA0 inputs. Consult the factory for alternate address programming options.
5.1.2 I 2C Read/Write operations
data, but transmits a stop condition to end the data transfer. master followed by a stop condition (SP) signaling an end of transmission. is now stored in the appropriate register. Table 9. I
- Preproduction parts have the I 2C address of 0x1C, 0x1D, 0x1E and 0x1F respectively.
FXOS8700CQ acknowledgment (ACK) is received. Figure 6. I2C timing diagram
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5.2 SPI Interface characteristics
initiating the communication. Table 10 and Figure 7 describe the timing requirements for the SPI system. Figure 7. SPI Timing Diagram
5.2.1 General SPI operation
transaction is complete. During a transaction the master toggles the SPI clock (SCLK) and transmits data on the MOSI pin. DATA[7],DATA[6],DATA[5],DATA[4],DATA[3],DATA[2],DATA[1],DATA[0].
- Polarity: rising/falling
- Phase: sample/setup
- Order: MSB first
Table 10. SPI timing
5.2.2 SPI READ/WRITE operations
first and second serialized bytes. Subsequent bits are ignored by the part. The read data is deserialized from the MISO pin. bytes can be transmitted into consecutive registers, starting from the indicated register address in ADDR[7:0]. transaction is always initiated by master. Figure 8. SPI single-burst READ/WRITE transaction diagram
5.2.3 I 2C/SPI auto detection
exiting reset. Once set for I2C or SPI operation the device will remain in I2C or SPI mode until the device is reset.
5.2.4 Power supply sequencing and I 2C/SPI mode auto detection
for further options if necessary. Table 11. Serial interface pin descriptions Table 12. I2C/SPI auto detection
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6 Modes of Operation
Figure 9. FXOS8700CQ power mode transition diagram please refer to Section 7, “Embedded Functionality” or Freescale application note AN4074. Table 13. Mode of operation description are shutdown. I2C bus inhibited. Only digital blocks are enabled. Analog subsystem is disabled. Internal clocks disabled. All blocks are enabled (digital and analog).
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7 Embedded Functionality
FXOS8700CQ is a low-power, digital output 6-axis sensor with both I2C and SPI interfaces. Extensive embedded functionality is provided to detect inertial and magnetic events at low-power, with the ability to notify the host processor of an event via either of the two programmable interrupt pins. The embedded functionality includes:
- 8-bit or 14-bit accelerometer data which includes high-pa ss filtered data, and 8 or 16-bit magnetometer data
- Four different oversampling options for the accelerometer ou tput data, and eight for the magnetometer. The oversampling settings allow the end user to optimize the resolution versus power trade-off in a given application.
- A low-noise accelerometer mode that functions independent ly of the oversampling modes for even higher resolution
- Low-power auto-wake/sleep function for conser ving power in portable battery powered applications
- Accelerometer pulse detection circuit which can be used to detect directional single and double taps
- Accelerometer directional motion and freefall event detection with programmable threshold and debounce time
- Acceleration transient detection with programmable threshold and debounce time. Transient detection can employ either a high-pass filter or use the difference between reference and current sample values.
- Orientation detection with programmable hysteresis for smooth transitions between portrait/landscape orientations
- Accelerometer vector magnitude change event detection with programmable reference, threshold, and debounce time values
- Magnetic threshold event detection with progra mmable reference, threshold, and debounce time
- Magnetometer vector magnitude change ev ent detection with programmable reference, threshold and debounce time values
- Magnetic min/max detection circuit which can also be used for autonomous calibration of magnetic hard-iron offset Many different configurations of the above functions are possible to suit the needs of the end application. Separate application notes are available to further explain the different configuration settings and potential use cases.
7.1 Factory calibration
FXOS8700CQ's integrated accelerometer and magnetometer sensors are factory calibrated for sensitivity and offset on each axis. The trim values are stored in Non-Volatile Memory (NVM). On power-up, the trim parameters are read from NVM and applied to the internal compensation circuitry. After mounting the device to the PCB, the user may further adjust the accelerometer and magnetometer offsets through the OFF_X/Y/Z and M_OFF_X/Y/Z registers, respectively. For more information on device calibration, refer to Freescale application note, AN4069. 7.2 8-bit or 14-bit accelerometer data The measured acceleration data is stored in the OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB registers as 2’s complement 14-bit numbers. The most significant 8-bits of each axis are stored in the OUT_X, Y, Z_MSB registers, so applications needing only 8-bit results simply read these three registers and ignore the OUT_X,Y, Z_LSB registers. To do this, the f_read mode bit in CTRL_REG1 must be set. When the full-scale range is set to 2g, the measurement range is -2g to +1.999g, and each count corresponds to 0.244 mg at ±14-bits resolution. When the full-scale is set to 8g, the measurement range is -8g to +7.996g, and each count corresponds to 0.976 mg. The resolution is reduced by a factor of 64 if only the 8-bit results are used ([f_read] = 1). For further information on the different data formats and modes, please refer to Freescale application note AN4076.
7.3 Accelerometer low-power mod es versus high-resolution modes
FXOS8700CQ can be optimized for lower power or for higher resolution of the accelerometer output data. High resolution is achieved by setting the lnoise bit in register 0x2A. This improves the resolution (by lowering the noise), but be aware that the dynamic range becomes limited to ±4g when this bit is set. This will affect all internal embedded functions (scaling of thresholds, etc.) and reduce noise. Another method for improving the resolution of the data is through oversampling. One of the oversampling schemes of the output data can activated when CTRL_REG2[mods] = 0b10 which will improve the resolution of the output data without affecting other internal embedded functions or limiting the dynamic range. There is a trade-off between low power and high resolution. Low power can be achieved when the oversampling rate is reduced. When CTRL_REG2[mods] = 0b10, the lowest power is achieved, at the expense of higher noise. In general, the lower the selected ODR and OSR, the lower the power consumption. For more information on how to configure the device in low-power or high-resolution modes and understand the benefits and trade-offs, please refer to Freescale application note AN4075.
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7.4 Auto-Wake/Sleep mode
FXOS8700CQ can be configured to transition between sample rates (with their respective current consumptions) based on the status of the embedded interrupt event generators in the device. The advantage of using the Auto-Wake/Sleep is that the system can automatically transition to a higher sample rate (higher current consumption) when needed but spends the majority of the time in the Sleep mode (lower current) when the device does not require higher sampling rates. Auto-Wake refers to the device being triggered by one of the interrupt event functions to transition to a higher sample rate. This may also interrupt the processor to transition from a sleep mode to a higher power mode. Sleep mode occurs when none of the enabled interrupt event functions has detected an interrupt within the user defined time- out period. The device will then transition to the specified lower sample rate. It may also alert the processor to go into a lower power mode to save power during this period of inactivity . Please refer to AN4074 for more detailed information on configuring the Auto- Wake/Sleep function.
7.5 Hybrid mode
FXOS8700CQ uses a single common Analog-to-Digital Converter (ADC) for both the accelerometer and magnetometer. When operating in hybrid mode (M_CTRL_REG1[m_hms] = 2’b11), both the accelerometer and magnetometer sensors are actively measured by the ADC at an ODR equal to one half of the setting made in CTRL_REG1[dr] when operating in accelerometer-only mode (M_CTRL_REG1[m_hms] = 2’b00 (default)) or magnetometer-only mode (M_CTRL_REG1[m_hms] = 2’b01). While the ODR is common to both sensors when operating in hybrid mode, the OSR settings for each sensor are independent and may be set via CTRL_REG2[mods] for the accelerometer and M_CTRL_REG1[m_os] for the magnetometer, respectively.
7.6 Accelerometer Freefall a nd Motion event detection
FXOS8700CQ integrates a programmable threshold based acceleration detection function capable of detecting either motion or freefall events depending upon the configuration. For further details and examples on using the embedded freefall and motion detection functions, please refer to Freescale application note AN4070.
7.6.1 Freefall detection
The detection of “Freefall” involves the monitoring of the X, Y, and Z axes for the condition where the acceleration magnitude is below a user specified threshold for a user definable amount of time. Typically, the usable threshold ranges are between ±100 mg and ±500 mg.
7.6.2 Motion detection
Motion detection is often used to alert the main processor that the device is currently in use. When the acceleration exceeds a set threshold for a set amount of time, the motion interrupt is asserted. A motion can be a fast moving shake or a slow moving tilt. This will depend on the threshold and timing values configured for the event. The motion detection function can analyze static acceleration changes or faster jolts. The timing value is set by a configurable debounce counter. The debounce counter acts like a filter to indicate whether the condition exists for longer than a set amount of time (i.e., 100 ms or longer). There is also directional data available in the source register to detect the direction of the motion that generated the interrupt. This is useful for applications such as directional shake or flick detection, and can also assist gesture detection algorithms by indicating that a motion gesture has started.
7.7 Transient detection
FXOS8700CQ integrates an acceleration transient detection function that incorporates a high-pass filter. Acceleration data goes through the high-pass filter, eliminating the DC tilt offset and low frequency acceleration changes. The high-pass filter cutoff can be set by the user to four different frequencies which are dependent on the selected Output Data Rate (ODR). A higher cutoff frequency ensures that DC and slowly changing acceleration data will be filtered out, allowing only the higher frequencies to pass. The transient detection feature can be used in the same manner as the motion detection by bypassing the high-pass filter. There is an option in the configuration register to do this. This adds more flexibility to cover the various customer use cases. Many applications use the accelerometer’s static acceleration readings (i.e., tilt) which measure the change in acceleration due to gravity only. These functions benefit from acceleration data being filtered with a low-pass filter where high-frequency data is considered noise. However, there are many functions where the accelerometer must analyze dynamic acceleration. Functions such as tap, flick, shake and step counting are based on the analysis of the change in the dynamic acceleration. The transient detection function can be routed to either interrupt pin through bit 5 in CTRL_REG5 register (0x2E). Registers 0x1D – 0x20 and 0x79 – 0x7C are the dedicated transient detection configuration registers. The source register contains directional data to determine the direction of the transient acceleration, either positive or negative. For further information of the embedded transient detection function along with specific application examples and recommended configuration settings, please refer to Freescale application note AN4071.
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7.8 Pulse detection
FXOS8700CQ has embedded single/double and directional pulse detection. This function employs several timers for programming the pulse width time and the latency between pulses. The detection thresholds are independently programmable for each axis. The acceleration data input to the pulse detection circuit can be put through both high and low-pass filters, allowing for greater flexibility in discriminating between pulse and tap events. The PULSE_SRC register provides information on the axis, direction (polarity), and single/double event status for the detected pulse or tap. For more information on how to configure the device for pulse detection, please refer to Freescale application note AN4072.
7.9 Orientation detection
FXOS8700CQ has an embedded orientation detection algorithm with the ability to detect all six orientations. The transition angles and hysteresis are programmable, allowing for a smooth transition between portrait and landscape orientations. The angle at which the device no longer detects the orientation change is referred to as the “Z-lockout angle”. The device operates down to 29° from the flat position. All angles are accurate to ±2°. For further information on the orientation detection function refer to Freescale application note, AN4068.
7.10 Acceleration Vector Magnitude detection
FXOS8700CQ incorporates an acceleration vector magnitude change detection block that can be configured to generate an interrupt when the acceleration magnitude exceeds a pre-set threshold for a programmed debounce time. The function can be configured to operate in absolute or relative modes, and can also act as a wake to sleep/sleep to wake source. This function is useful for detecting acceleration transients when operated in absolute mode, or for detecting changes in orientation when operated in relative mode.
7.11 Magnetic Vector Magnitude detection
FXOS8700CQ incorporates a magnetic vector magnitude change detection block that can be configured to generate an interrupt when the magnetic field magnitude exceeds a pre-set threshold for a programmed debounce time. The function can be configured to operate in absolute or relative modes, and can also act as a wake to sleep/sleep to wake source.
7.12 Magnetic Threshold detection
FXOS8700CQ incorporates a magnetic threshold event detection block that can be configured to generate an interrupt when the magnetic field on the enabled axes is above or below a programmed threshold. Two logic combinations are possible for the detection: all of the enabled axes below their respective thresholds (AND condition), or any of the enabled axes above their respective thresholds (OR condition). Even detection may be filtered using a dedicated debounce counter to avoid spurious event detection. The thresholds for each axis are individually programmable and the function can also act as a wake to sleep/sleep to wake source.
7.13 Magnetic Min/Max detection (autonomous calibration)
FXOS8700CQ incorporates a magnetic min/max detection circuit that can be used to automatically track the minimum and maximum field values measured on each of the X, Y, and Z axes. The stored minimum and maximum values may optionally be used to determine the magnetic hard-iron compensation and load the offset registers with the appropriate correction values.
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8 Register Map
Table 14. Register Address Map
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26 Freescale Semiconductor, Inc. condition is detected. In SPI mode there is no stop condition and the address is not cleared.
- Register contents are preserved when transitioning from Active to Standby mode.
- Register contents are reset when trans itioning from Standby to Active mode.
- Register contents can be modified anytime in Standby or Active mode. A write to this register will cause a reset of the corresponding internal
- Modification of this register’s contents can only occur when device is in Standby mode, except the FS[1:0] bit fields in CTRL_REG1 register. Hybrid
current accelerometer and magnetometer data in one contiguous operation.
- To ensure that valid data is read from these registers, the us er must first read the M_OUT_X_MSB register in either burst or single-read mode.
Reading of the M_OUT_X_MSB register triggers the update of the M_OUT_X/Y/Z registers with the current time-aligned output data.
- To ensure that valid data is read from these registers, the user must first read the MSB register of each register pair in either burst or single-read
mode. Reading of the LSB register without first reading the MSB register will result in invalid data.
9 Registers by Functional Blocks
9.1 Device configuration
9.1.1 STATUS (0x00) register
the auto incrementing mechanism in both 8 and 14-bit modes.
9.1.2 DR_STATUS (0x00) register
OUTX, OUTY, and OUTZ registers. time status information of the X, Y, and Z sample data. Figure 10. STATUS register Table 15. STATUS Description Figure 11. DR_STATUS register Table 16. DR_STATUS description when the high-bytes of the acceleration data (OUTX_MSB, OUTY_MSB, and OUTZ_MSB) are read. X, Y , Z-axis data overwrite. previous data is overwritten. zow is cleared anytime OUTZ_MSB register is read. previous data is overwritten. yow is cleared anytime OUTY_MSB register is read.
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9.1.3 F_STATUS (0x00) register
FIFO Status when STATUS > 0x00. INT_SOURCE[src_fifo] bit will be set again when the next data sample enters the FIFO. while the f_cnt value is equal to or greater than then f_wmrk value. previous data is overwritten. xow is cleared anytime OUTX_MSB register is read. acceleration data (OUTX_MSB, OUTY_MSB, OUTZ_MSB) are read. X, Y , Z-axis new data ready. zdr is set to 1 whenever a new Z-axis data acquisition is completed. zdr is cleared anytime the OUTZ_MSB register is read. ydr is set to 1 whenever a new Y-axis data acquisition is completed. ydr is cleared anytime the OUTY_MSB register is read. xdr is set to 1 whenever a new X-axis data acquisition is completed. xdr is cleared anytime the OUTX_MSB register is read. Figure 12. F_STATUS register Table 17. FIFO flag event descriptions 0 X No FIFO overflow events detected. 1 X FIFO overflow event detected. X 0 No FIFO watermark event detected.
9.1.4 TRIG_CFG (0x0A) register
FIFO and the various trigger events, please see AN4073 available on the Freescale website.
9.1.5 SYSMOD (0x0B) register
also indicates the status of the FIFO gate error flag and the time elapsed since the FIFO gate error flag was asserted. Table 18. FIFO sample count bit description FIFO sample counter. Default value 0b000000. Figure 13. TRIG_CFG register Table 19. TRIG_CFG bit descriptions trig_trans Transient interrupt FIFO trigger enable. trig_lndprt Landscape/Portrait orientation interrupt FIFO trigger enable. trig_a_vecm Acceleration vector magnitude FIFO trigger enable. Figure 14. SYSMOD register Table 20. SYSMOD bit description FIFO gate error. Default value: 0. 0: No FIFO gate error detected. 1: FIFO gate error was detected. Emptying the FIFO buffer clears the fgerr bit in the SYSMOD register. See CTRL_REG3 [Interrupt CTRL register] (0x2C) for more information on configuring the FIFO Gate function. System mode. Default value: 0.
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9.1.6 INT_SOURCE (0x0C) register
are located in the M_INT_SRC register (0x5E). interrupt flag bits are reset by reading the appropriate interrupt source register for the function that generated the interrupt. Figure 15. INT_SOURCE register Table 21. INT_SOURCE bit descriptions transition interrupt event has occurred. (ASLP_COUNT) has been detected, thus causing the system to transition to a user specified low ODR setting. system to transition to the user specified higher ODR setting. Reading the SYSMOD register will clear the src_aslp bit. = F_STATUS[f_wmrk]) event has occurred and logic ‘0’ indicates that no FIFO interrupt event has occurred. This bit is cleared by reading the F_STATUS register. has occurred. and logic ‘0’ indicates that no transient event has occurred. This bit is asserted whenever TRANSIENT_SRC[ea] is asserted and the functional block interrupt has been enabled. This bit is cleared by reading the TRANSIENT_SRC register. device orientation status and logic ‘0’ indicates that no change in orientation status was detected. This bit is asserted whenever PL_STATUS[newlp] is asserted and the functional block interrupt has been enabled. This bit is cleared by reading the PL_STATUS register. logic ‘0’ indicates that no pulse event was detected. This bit is asserted whenever PULSE_SRC[ea] is asserted and the functional block interrupt has been enabled. This bit is cleared by reading the PULSE_SRC register. indicates that no freefall or motion event was detected. This bit is asserted whenever PULSE_SRC[ea] is asserted and the functional block interrupt has been enabled. This bit is cleared by reading the A_FFMT_SRC register. Data-ready interrupt status bit. In acceleration only mode this bit indicates that new accelerometer data is available to read. signals that new acceleration and/or magnetic data is available. all of the sensor data can be read out in a 12 byte burst read starting at register 0x01 (OUT_X_MSB).
9.1.7 WHO_AM_I (0x0D) register
9.1.8 CTRL_REG1 (0x2A) register
what is shown in Table 22. For example, with aslp_rate = 0b00 the frequency is 25 Hz. reduced by a factor of two when the device is operated in hybrid mode. Figure 16. WHO_AM_I register Figure 17. CTRL_REG1 register Table 22. CTRL_REG1 bit descriptions aslp_rate[1:0] Configures the auto-wake sample frequency when the device is in Sleep mode. See Table 22 for more information. dr[2:0] Output Data Rate (ODR) selection. See Table 23 for more information. Reduced noise and full-scale range mode (analog gain times 2). 1: Reduced noise mode; Note that the FSR setting is restricted to a ±4g in this mode (lnoise = 1). pointer will skip over the LSB addresses for each axes sample data when performing a burst read operation. Table 23. Sleep mode poll rate description
32 Freescale Semiconductor, Inc. The active bit selects between Standby mode and Active mode. The default value is 0 (Standby mode) on reset. maximum signal that can be measured is ±4g. Note: Any thresholds set above 4g will not be reached.
9.1.9 CTRL_REG2 (0x2B) register
Table 24. System Output Data Rate selection Figure 18. CTRL_REG2 register Table 25. CTRL_REG2 bit descriptions thus allowing the host application to check the functionality of the entire measurement signal chain. reset can also be initiated by pulsing the external RST pin high. device over the I2C or SPI interfaces. At the end of the boot process the rst bit is deasserted to 0. Reading this bit will always return a value of 0. smods[1:0] Sleep mode power scheme selection. See Table 25 for more information.
- When SLPE = 1, a transition between Sleep mode and Wake mode result s in a FIFO flush and a reset of internal functional block counters.
description (FIFO_GATE bit). for acceleration measurements. See Table 25 for more information.
9.1.10 CTRL_REG3 [Interrupt Control Register] (0x2C) register
Table 26. CTRL_REG2[mods] oversampling modes
00 N ormal
Table 27. Current Consumption versus Oversampling Figure 19. CTRL_REG3 register Table 28. CTRL_REG3 bit descriptions FIFO buffer are preserved, new data samples are ignored until the FIFO is emptied by the host application. Emptying the FIFO buffer clears the SYS_MOD[fgerr] register. wake_lndprt 0: Orientation function is disabled Sleep mode.
34 Freescale Semiconductor, Inc.
9.1.11 CTRL_REG4 [Interrupt Enable Register] (0x2D) register
interrupts are located in registers 0x52 (MAG_THS_CFG), and 0x69 (M_VECM_CFG), respectively. The ipol The bit selects the logic polarity of the interrupt signals output on the INT1 and INT2 pins. multiple interrupt signals on the same interrupt line but will require an external pullup resistor to function correctly.
- The FIFO contents are flushed whenever the system ODR changes in order to prevent the mixing of FIFO data from different time domains.
(MAG_THS_CFG) and 0x69 (M_VECM_CFG), respectively. Figure 20. CTRL_REG4 register Table 29. Interrupt Enable Register bit descriptions
9.1.12 CTRL_REG5 [Interrupt Routing Configuration Register] (0x2E) register
Figure 21. CTRL_REG5 register Table 30. Interrupt Routing Configuration bit descriptions 1: Interrupt is routed to INT1 pin. 1: Interrupt is routed to INT1 pin.
36 Freescale Semiconductor, Inc. Figure 22. Interrupt controller block diagram Figure 23. INT1/INT2 PIN Control Logic
9.2 Auto-Sleep trigger
9.2.1 ASLP_COUNT (0x29) register
provided that CTRL_REG2[slpe] = 1. See Table 32 for functional blocks that may be monitored for inactivity in order to trigger the return-to-sleep event.
Please note that when the device is operated in hybrid mode, the effective ODR is half of what is selected in CTRL_REG1[dr]. For example, with ODR = 800 Hz and the device set to hybrid mode, the ASLP_COUNT time step becomes 640 ms. instead it prevents the FIFO buffer from accepting new sample data until the host application flushes the FIFO buffer. from Auto-Sleep mode (i.e. wakes up), except for the data ready function. system will transition to the Sleep mode and use the ODR value specified in CTRL_REG1[aslp_rate]. Figure 24. ASLP_COUNT register Table 31. ASLP_COUNT bit description Table 32. ASLP_COUNT relationship with ODR Table 33. Sleep/Wake mode gates and triggers
38 Freescale Semiconductor, Inc. enabled in register CTRL_REG3. If the Auto-Sleep interrupt is enabled, a transition from Active mode to Sleep mode and vice-versa will generate an interrupt. Figure 25. Auto-Sleep state transition diagram
9.3 Temperature
9.3.1 TEMP (0x51) register
9.4 Accelerometer output data registers
9.4.1 OUT_X_MSB (0x01), OUT_X_LSB (0x02), OUT_Y_MSB (0x03), OUT_Y_LSB (0x04),
These registers contain the X-axis, Y-axis, and Z-axis 14-bit left-justified sample data expressed as 2's complement numbers. 32 X, Y, and Z data samples. CTRL_REG1[f_read] register setting. Figure 26. TEMP register
while registers 0x02, 0x03, 0x04, 0x05, 0x06 return a value of zero when read directly. executing a burst read of 12 bytes starting at register OUT_X_MSB.
9.5 Accelerometer FIFO
9.5.1 F_SETUP (0x09) register
Figure 27. OUT_X_MSB register Figure 28. OUT_X_LSB register Figure 29. OUT_Y_MSB register Figure 30. OUT_Y_LSB register Figure 31. OUT_Z_MSB register Figure 32. OUT_Z_LSB register Figure 33. F_SETUP register
40 Freescale Semiconductor, Inc. A FIFO sample count exceeding the watermark event does not stop the FIFO from accepting new data. Auto-Sleep is active, the ODR is set by CTRL_REG1[aslp_rate] bit fields. the X-axis data, it will be lost. In Trigger mode, the FIFO is operated as a circular buffer and will contain up to the 32 most recent acceleration data samples. information on using the FIFO buffer and the various FIFO operating modes, please refer to Freescale application note AN4073.
9.6 Accelerometer sensor data configuration
9.6.1 XYZ_DATA_CFG (0x0E) register
data is passed through the high-pass filter. Table 34. F_SETUP bit descriptions
- This bit field can be written in Active mode.
- This bit field can be written in Standby mode.
- The FIFO mode ( f_mode) cannot be switched between operational modes (01, 10 and 11).
10: FIFO stops accepting new samples when overflowed. transition from Standby mode to Active mode. A FIFO overflow event (i.e. F_STATUS[f_cnt] = 32) will assert the F_STATUS[f_ovf] flag. FIFO sample count watermark. Setting the f_wmrk to 0b000000 will disable the FIFO watermark event flag generation. This field is also used to set the number of pre-trigger samples in trigger mode (f_mode = 0b11). Figure 34. XYZ_DATA_CFG register Table 35. XYZ_DATA_CFG bit descriptions 0: High-pass filter is disabled.
9.7 Accelerometer High-Pass filter
9.7.1 HP_FILTER_CUTOFF (0x0F) register
High-pass filter cutoff frequency setting register.
11 R eserved
Figure 35. HP_FILTER_CUTOFF register Table 37. HP_FILTER_CUTOFF bit descriptions Table 38. HP_FILTER_CUTOFF
42 Freescale Semiconductor, Inc. frequency is now 2 Hz for the same ODR and HP_FILTER_CUTOFF[sel] settings.
9.8 Portrait/Landscape Detection
meaning of the different user configurable settings and for example code, please refer to Freescale application note AN4068. Figure 36. Illustration of Z-tilt angle lockout transition Figure 37. Illustration of landscape to portrait transition
Figure 38. Illustration of portrait to landscape transition
9.8.1 PL_STATUS (0x10) register
Back and Front orientations please refer to Figure 38. The interrupt is cleared when reading the PL_STATUS register. Figure 39. PL_STATUS register Table 39. PL_STATUS bit descriptions Landscape/Portrait status change flag. 0: Lockout condition has not been detected. 1: Z-tilt lockout trip angle has been exceeded. Lockout condition has been detected. 0: Front: equipment is in the front facing orientation. 1: Back: equipment is in the back facing orientation.
- The default power up state is bafro(Undefined), lapo( Undefined), and no lockout for orientation function.
Landscape/Portrait orientation. 11: Landscape left: equipment is in landscape mode to the left.
44 Freescale Semiconductor, Inc.
9.8.2 PL_CFG (0x11) register
This register enables the Portrait/Landscape function and sets the behavior of the debounce counter.
9.8.3 PL_COUNT (0x12) register
9.8.4 PL_BF_ZCOMP (0x13) register
Figure 40. PL_CFG register Table 40. PL_CFG bit descriptions Debounce counter mode selection. 0: Decrements debounce whenever condition of interest is no longer valid. 1: Clears counter whenever condition of interest is no longer valid. Portrait/Landscape detection enable. 0: Portrait/Landscape detection is disabled. 1: Portrait/Landscape detection is enabled. Figure 41. PL_COUNT register Table 41. PL_Count Relationship with the ODR Figure 42. PL_BF_ZCOMP register
9.8.5 PL_THS_REG (0x14) register
Portrait to landscape trip threshold registers. Table 42. PL_BF_ZCOMP bit descriptions Z-lock angle threshold. range is from 13° to 44°. Step size is approximately 4°. See Table 42 for more information. Back/front trip angle threshold. See Table 43 for more information. Default: 10 ≥ ±75°. Step size is 5°. Table 43. Z-Lockout Angle definitions Table 44. Back/Front Orientation definitions
00 Z < 80° or Z > 280° Z > 100° and Z < 260°
01 Z < 75° or Z > 285° Z > 105° and Z < 255°
10 Z < 70° or Z > 290° Z > 110° and Z < 250°
11 Z < 65° or Z > 295° Z > 115° and Z < 245°
Figure 43. PL_THS_REG register Table 45. Threshold angle lookup table
46 Freescale Semiconductor, Inc.
9.9 Freefall and Motion detection
condition occurring in any of the enabled axes (ex. X, Y or Z) will suffice to affect the A_FFMT_SRC [a_ffmt_ea] bit. (A_FFMT_THS_X/Y/Z) for individual axis threshold operation. freefall or motion events are not latched, and the A_FFMT_SRC[a_ffmt_ea] bit reflects the real-time status of the event detection. A_FFMT_SRC[a_ffmt_ea] bit. See Figure 55 for details. A_FFMT_CFG[a_ffmt_xefe], A_FFMT_CFG[a_ffmt_yefe], and A_FFMT_CFG[a_ffmt_zefe]. axis may be programmed with an individual 13-bit threshold (stored in the A_FFMT_X/Y/Z MSB and LSB registers).
9.9.1 A_FFMT_CFG (0x15) register
Freefall/motion configuration register. Table 46. Trip angles versus hysteresis settings Table 47. Portrait/Landscape orientation definitions Figure 44. A_FFMT_CFG register
9.9.2 A_FFMT_SRC (0x16) register
Freefall/motion source register. Read-only register. CTRL_REG5[int_cfg_ffmt] register bits to generate the freefall/motion interrupts. Table 48. A_FFMT_CFG bit descriptions when the a_ffmt_ea bit gets set, and are cleared by reading the A_FFMT_SRC source register. (logical AND combination of low-g X, Y, Z-axis event flags) detection. Motion detect/freefall detect logic selection. flags are blocked from updating the A_FFMT_SRC register. 1: Raise event flag on measured Z-axis acceleration above/below threshold. flags are blocked from updating the A_FFMT_SRC register. 1: Raise event flag on measured Y-axis acceleration above/below threshold. flags are blocked from updating the A_FFMT_SRC register. 1: Raise event flag on measured X-axis acceleration above/below threshold. Figure 45. A_FFMT_SRC register Table 49. A_FFMT_SRC bit descriptions effect of the 3-axis event flags on the a_ffmt_ea bit.
48 Freescale Semiconductor, Inc.
9.9.3 A_FFMT_THS (0x17), A_FFMT_ THS_X_MSB (0x73), A_FFMT_THS_X_LSB (0x74),
Freefall/motion detection threshold registers. Figure 46. A_FFMT_THS (0x17) register Table 50. A_FFMT_THS (0x17) bit descriptions (part c, Figure 55) until the debounce counter reaches 0 or the inertial event of interest become active. detection of inertial events. ths[6:0] Freefall/motion detection threshold: default value: 0b0000000. Resolution is fixed at 63 mg/LSB. Figure 47. A_FFMT_THS_X_MSB (0x73) register
50 Freescale Semiconductor, Inc. Figure 53. A_FFMT_THS high and low-g level
9.9.4 A_FFMT_COUNT (0x18) register
either a freefall or motion detection event required before the interrupt is triggered. CTRL_REG1. This has the effect of doubling the time-step values shown in Table 53. Figure 52. A_FFMT_THS_Z_LSB (0x78) register Figure 54. A_FFMT_COUNT register Table 53. A_FFMT_COUNT bit description
150 ms. If the device is operated in hybrid mode, the effective debounce response time will be 300 ms for the same settings. Figure 55. Behavior of the A_FFMT debounce counter in relation to the a_ffmt_dbcntm setting Table 54. A_FFMT_COUNT relationship with the ODR
52 Freescale Semiconductor, Inc.
9.10 Accelerometer vector magnitude function
value stored in A_VECM_CNT, the vector magnitude change event flag is triggered. values stored internally in the ASIC for each axis or in A_VECM_INIT_X/Y/Z registers if A_VECM_CFG[a_vecm_initm] is set. Please note that the x_ref, y_ref, and z_ref values are not directly visible to the host application through the register interface. Please refer to Freescale application note 4458.
9.10.1 A_VECM_CFG (0x5F) register
9.10.2 A_VECM_THS_MSB (0x60) register
Figure 56. A_VECM_CFG register Table 55. A_VECM_CFG bit descriptions Control bit a_vecm_initm defines how the initial reference values (x_ref, y_ref, and z_ref) are chosen. magnitude function is enabled. For a_vecm_initm = 1 the function uses the data from A_VECM_INIT_X/Y/Z registers as the initial reference values. writing to the A_VECM_INITX,Y,Z registers. A_VECM_INIT_X/Y/Z registers, depending on the state of the a_vecm_initm bit. Note: The vector magnitude function will only perform correctly up to a maximum ODR of 400 Hz. Figure 57. A_VECM_THS_MSB register
9.10.3 A_VECM_THS_LSB (0x61) register
9.10.4 A_VECM_CNT (0x62) register
is reduced by a factor of two, making the debounce time 300 ms for this example. Table 56. A_VECM_THS_MSB bit descriptions Figure 58. A_VECM_THS_LSB register Figure 59. A_VECM_CNT register Table 57. A_VECM_CNT bit description a_vecm_cnt[7:0] Vector magnitude function debounce count value. Table 58. A_VECM_CNT relationship with selected ODR and power mode
54 Freescale Semiconductor, Inc.
9.10.5 A_VECM_INITX_MSB (0x63) register
9.10.6 A_VECM_INITX_LSB (0x64) register
9.10.7 A_VECM_INITY_MSB (0x65) register
9.10.8 A_VECM_INITY_LSB (0x66) register
Figure 60. A_VECM_INITX_MSB register Table 59. A_VECM_INITX_MSB bit description Figure 61. A_VECM_INITX_LSB register Table 60. A_VECM_INITX_LSB bit description resolution is determined by the settings made in XYZ_DATA_CFG[fs], and is equal to the accelerometer resolution. Figure 62. A_VECM_INITY_MSB register Table 61. A_VECM_INITY_MSB bit description Figure 63. A_VECM_INITY_LSB register Table 62. A_VECM_INITY_LSB bit description is determined by the settings made in XYZ_DATA_CFG[fs], and is equal to the accelerometer resolution.
9.10.9 A_VECM_INITZ_MSB (0x67) register
9.10.10 A_VECM_INITZ_LSB (0x68) register
9.11 Transient (AC) a cceleration detection
transient detection function to work in a similar manner to the motion detection function. Freescale application note AN4461.
9.11.1 TRANSIENT_CFG (0x1D) register
Figure 64. A_VECM_INITZ_MSB register Table 63. A_VECM_INITZ_MSB bit description Figure 65. A_VECM_INITZ_LSB register Table 64. A_VECM_INITZ_LSB bit description resolution is determined by the settings made in XYZ_DATA_CFG[fs], and is equal to the accelerometer resolution. Figure 66. TRANSIENT_ CFG register
56 Freescale Semiconductor, Inc.
9.11.2 TRANSIENT_SRC (0x1E) register
Table 65. TRANSIENT_ CFG bit descriptions 0: Event flag latch disabled: the transient interrupt flag reflects the real-time status of the function. required to clear the event flag. 1: Z-axis event detection enabled. Raise event flag on Z-axis acceleration value greater than threshold. 1: Y-axis event detection enabled. Raise event flag on Y-axis acceleration value greater than threshold. 1: X-axis event detection enabled. Raise event flag on X-axis acceleration value greater than threshold. 0: High-pass filter is applied to accelerometer data input to the transient function. 1: High-pass filter is not applied to accelerometer data input to the transient function. Figure 67. TRANSIENT_ CFG register Table 66. TRANSIENT_SRC bit descriptions 0: No transient event active flag has been asserted. 1: One or more transient event active flags has been asserted. 0: Z-axis event flag is not active. 0: Z-axis event was above positive threshold value. 1: Z-axis event was below negative threshold value. 0: Y-axis event flag is not active. 0: Y-axis event was above positive threshold value. 1: Y-axis event was below negative threshold value. 0: X-axis event flag is not active. 0: X-axis event was above positive threshold value. 1: X-axis event was below negative threshold value.
polarity bits, but once set, the flags can only be cleared by reading the TRANSIENT_SRC register.
9.11.3 TRANSIENT_THS (0x1F) register
axes via a_ffmt_trans_ths_en bit in A_FFMT_THS_Y_MSB register. Please see Section 9.9.3 for more details. the measurement range is fixed at ±4g, regardless of the settings made in XYZ_DATA_CFG.
9.11.4 TRANSIENT_COUNT (0x20) register
flag when the measured acceleration value exceeds the threshold set in TRANSIENT_THS for any of the enabled axes. Table 68. When the device is operated in hybrid mode, the effective ODR is half of what is selected in CTRL_REG1, which also doubles the time-step values shown in Table 68. Figure 68. TRANSIENT_THS register Table 67. TRANSIENT_THS bit descriptions Debounce counter mode selection. 0: Decrements debounce counter when the transient event condition is not true during the current ODR period. 1: Clears debounce counter when the transient event condition is not true during the current ODR period. XYZ_DATA_CFG[fs]. If CTRL_REG1[lnoise] = 1, the maximum acceleration measurement range is ±4g. Figure 69. TRANSIENT_COUNT register Table 68. TRANSIENT_COUNT bit description tr_count[7:0) Transient function debounce count value.
58 Freescale Semiconductor, Inc. the device is operated in hybrid mode, these settings would result in an effective debounce time of 300 ms.
9.12 Pulse detection
9.12.1 PULSE_CFG (0x21) register
This register configures the pulse event detection function. Table 69. TRANSIENT_COUNT relationship with the ODR Figure 70. PULSE_CFG register Table 70. PULSE_CFG bit descriptions Pulse event flag latch enable. When enabled, a read of the PULSE_SRC register is needed to clear the event flag. Event flag enable on double pulse event on Z-axis. Event flag enable on single pulse event on Z-axis. Event flag enable on double pulse event on Y-axis. Event flag enable on single pulse event on Y-axis. 1: Raise event flag on detection of single pulse event on Z-axis. Event flag enable on double pulse event on X-axis. 1: Raise event flag on detection of double pulse event on X-axis.
9.12.2 PULSE_SRC (0x22) register
This register indicates the status bit for the pulse detection function.
9.12.3 PULSE_THSX (0x23) register
Event flag enable on single pulse event on X-axis. 1: Raise event flag on detection of single pulse event on X-axis. Figure 71. PULSE_SRC register Table 71. PULSE_SRC bit descriptions 1: X-axis event has occurred. Double pulse on first event. 0: Single pulse event triggered interrupt. 1: Double pulse event triggered interrupt. Pulse polarity of Z-axis event. 0: Pulse event that triggered interrupt was positive. 1: Pulse event that triggered interrupt was negative. Pulse polarity of Y-axis event. 0: Pulse event that triggered interrupt was positive. 1: Pulse event that triggered interrupt was negative. Pulse polarity of X-axis event. 0: Pulse event that triggered interrupt was positive. 1: Pulse event that triggered interrupt was negative. Figure 72. PULSE_THSX register Table 72. PULSE_THSX bit description pls_thsx[6:0] Pulse threshold for X-axis.
60 Freescale Semiconductor, Inc. of the settings made in XYZ_DATA_CFG[fs].
9.12.4 PULSE_THSY (0x24) register
9.12.5 PULSE_THSZ (0x25) register
9.12.6 PULSE_TMLT (0x26) register
Figure 73. PULSE_THSY register Table 73. PULSE_THSY bit description pls_thsy[6:0] Pulse threshold for Y-axis. Figure 74. PULSE_THSZ register Table 74. PULSE_THSZ bit description pls_thsz[6:0] Pulse threshold for Z-axis. Figure 75. PULSE_TMLT register Table 75. PULSE_TMLT bit description Table 76. Time step for pulse time limit LPF_EN = 1
9.12.7 PULSE_LTCY (0x27) register
Table 77. Time step for PULSE time limit LPF_EN = 0 Figure 76. PULSE_LTCY register Table 78. PULSE_LTCY bit description Table 79. Time step for PULSE latency @ ODR and power mode LPF_EN = 1
62 Freescale Semiconductor, Inc.
9.12.8 PULSE_WIND (0x28) register
shown in Table 81 and Table 82. Table 80. Time step for PULSE Latency @ ODR and power mode LPE_EN = 0 Figure 77. PULSE_WIND register Table 81. PULSE_WIND bit description specified by the PULSE_WIND register. Table 82. Time step for PULSE detection window @ ODR and power mode LPF_EN = 1
9.13 Accelerometer offset correction
For more information on how to calibrate the 0g offset, please refer to Freescale application note AN4069.
9.13.1 OFF_X (0x2F) register
9.13.2 OFF_Y (0x30) register
9.13.3 OFF_Z (0x31) register
Table 83. Time step for PULSE detection window @ ODR and power mode LPF_EN = 1 Figure 78. OFF_X register Table 84. OFF_X bit description off_x[7:0] X-axis offset correction value ex pressed as an 8-bit 2's complement number. Figure 79. OFF_Y register Table 85. OFF_Y bit description off_y[7:0] Y-axis offset correction value expressed as an 8-bit 2's complement number. Figure 80. OFF_Z register
64 Freescale Semiconductor, Inc.
9.14 Magnetometer data registers
9.14.1 M_DR_STATUS (0x32) register
Magnetic data ready status register. This register indicates the real-time status information of the X, Y, and Z magnetic sample data. Table 86. OFF_Z bit description off_z[7:0] Z-axis offset correction value ex pressed as an 8-bit 2's complement number. Figure 81. M_DR_STATUS register Table 87. M_DR_STATUS bit descriptions event occurs when the content of at least one magnetometer output data register (i.e. M_OUT_X/Y/Z) has been overwritten. the previous data is overwritten. zow is cleared anytime the M_OUT_Z_MSB register is read. the previous data is overwritten. yow is cleared anytime M_OUT_Y_MSB register is read. the previous data is overwritten. xow is cleared anytime the M_OUT_X_MSB register is read. significant bytes of the magnetometer data (M_OUT_X_MSB, M_OUT_Y_MSB, and M_OUT_Z_MSB) are read.
9.14.2 M_OUT_X_MSB (0x33), M_OUT_X_LSB (0x34), M_OUT_Y_MSB (0x35), M_OUT_Y_LSB
X-axis, Y-axis, and Z-axis 16-bit magnetic output data expressed as 2's complement numbers, with a resolution of 0.1 μT/LSB.
9.14.3 CMP_X_MSB (0x39), CMP_X_LSB (0x3A), CMP_Y_MSB (0x3B), CMP_Y_LSB (0x3C),
OUT_X/Y/Z registers located at addresses x1-x6, the data in the CMP_X/Y/Z registers is right justified. 0: No new X-axis magnetic data is available. Figure 82. M_OUT_X_MSB (0x33) register Figure 83. M_OUT_X_LSB (0x34) register Figure 84. M_OUT_Y_MSB (0x35) register Figure 85. M_OUT_Y_LSB (0x36) register Figure 86. M_OUT_Z_MSB (0x37) register Figure 87. M_OUT_Z_LSB (0x38) register Figure 88. CMP_X_MSB (0x39) register Figure 89. CMP_X_LSB (0x3A) register
66 Freescale Semiconductor, Inc.
9.14.4 MAX_X_MSB (0x45), MAX_X_LSB (0x46), MAX_Y_MSB (0x47), MAX_Y_LSB (0x48),
(MAX_X/Y/Z + MIN_X/Y/Z) /2 when M_CTRL_REG2[maxmin_dis] = 0 (default). offset values at the end of every measurement cycle (ODR period). registers at the end of the next measurement cycle (ODR period). Figure 90. CMP_Y_MSB (0x3B) register Figure 91. CMP_Y_LSB (0x3C) register Figure 92. CMP_Z_MSB (0x3D) register Figure 93. CMP_Z_LSB (0x3E) register Figure 94. MAX_X_MSB register Figure 95. MAX_X_LSB register Figure 96. MAX_Y_MSB register Figure 97. MAX_Y_LSB register
9.14.5 MIN_X_MSB (0x4B), MIN_X_LSB (0x4C), MIN_Y_MSB (0x4D), MIN_Y_LSB (0x4E),
Y/Z + MIN_X/Y/Z) /2 when M_CTRL_REG2[maxmin_dis] = 0 (default). offset values at the end of every measurement cycle (ODR period). MIN_X/Y/Z registers at the end of the next measurement cycle (ODR period). Figure 98. MAX_Z_MSB register Figure 99. MAX_Z_LSB register Figure 100. MIN_X_MSB register Figure 101. MIN_X_LSB register Figure 102. MIN_Y_MSB register Figure 103. MIN_Y_LSB register Figure 104. MIN_Z_MSB register
68 Freescale Semiconductor, Inc.
9.15 Magnetometer offset correction
9.15.1 M_OFF_X_MSB (0x3F), M_OFF_X_LS B (0x40),M_OFF_Y_MSB (0x41),M_OFF_Y_LSB
0 (default) for the values in these registers to have any effect on the magnetic output data. Each offset register is 16-bit, 2's complement format with a resolution of 0.1 μT/LSB. Figure 105. MIN_Z_LSB register Figure 106. M_OFF_X_MSB register Figure 107. M_OFF_X_LSB register Figure 108. M_OFF_Y_MSB register Figure 109. M_OFF_Y_LSB register Figure 110. M_OFF_Z_MSB register Figure 111. M_OFF_Z_LSB register
9.16 Magnetometer threshold function
Y/Z registers for the time period specified in MAG_THS_COUNT before the event flag is triggered.
9.16.1 M_THS_CFG (0x52) register
Magnetic field threshold detection configuration register. by the offset values stored in the M_OFF_X/Y/Z registers when M_CTRL_REG3[m_raw] = 0. Figure 112. M_THS_CFG register Table 88. M_THS_CFG bit descriptions Magnetic threshold event latch enable. time status of the event detection logic. Magnetic threshold event logic selection. 0: Logical “AND” of enabled axes X, Y, and Z below threshold flags is used to detect the event. 1: Logical “OR” of enabled axes X, Y , and Z above threshold flags is used to detect the event. m_ths_wake_en 0: The system excludes the magnetic threshold event flag when evaluating the Auto-Sleep/Wake function. 1: The system includes the magnetic threshold event flag when evaluating the Auto-Sleep/Wake function. m_ths_int_en 0: Magnetic threshold interrupt is disabled. 1: Magnetic threshold interrupt is enabled.
70 Freescale Semiconductor, Inc. Figure 113. Illustration of magnetic threshold detection
9.16.2 M_THS_SRC (0x53) register
Magnetic threshold interrupt source register. flags specified in M_THS_CFG is true. Figure 114. M_THS_SRC register Table 89. M_THS_SRC bit descriptions 1: One or more event flag(s) has been asserted.
0 Field
9.16.3 M_THS_X_MSB (0x54), M_THS_X_LSB (0x55), M_THS_Y_MSB (0x56), M_THS_Y_LSB
value stored in the M_OFF_X/Y/Z registers when M_CTRL_REG3[m_raw] = 0. 1: X event detected was negative polarity. Figure 115. M_THS_X_MSB register Table 90. M_THS_X_MSB bit descriptions When m_ths_dbcntm = 1, the debounce counter is cleared to 0 whenever the magnetic event of interest is no longer true. m_ths_x[14:8] Upper 7 bits of the 15-b it unsigned X-axis magnetic threshold. Figure 116. M_THS_X_LSB register Figure 117. M_THS_Y_MSB register Figure 118. M_THS_Y_LSB register Figure 119. M_THS_Z_MSB register
72 Freescale Semiconductor, Inc.
9.16.4 M_THS_COUNT (0x5A) register
of the debounce counter is controlled by M_THS_X_MSB [m_ths_dbcntm]. step by a factor of two from what is shown in Table 91. hybrid mode, the same settings would result in a debounce response time of 300 ms. Figure 120. M_THS_Z_LSB register Figure 121. M_THS_COUNT register Table 91. M_THS_COUNT bit description m_ths_cnt[7:0] Magnetic threshold debounce count value. Table 92. M_THS_COUNT relationship with the ODR This table needs to be re-done for this function. Ask design during review
800 N/A N/A N/A N/A N/A N/A N/A N/A
Figure 122. DBCNTM bit function
9.17 Magnetometer control registers
9.17.1 M_CTRL_REG1 (0x5B) register
Figure 123. M_CTRL_REG1 register Table 93. M_CTRL_REG1 bit descriptions each axis at the end of every ODR cycle. 1: One-shot magnetic reset is enabled, hardware cleared when complete.
74 Freescale Semiconductor, Inc. The m_os[2:0] OSR setting along with the system ODR value set in CTRL_REG1 sets the magnetic output data update rate. CMP_Z_MSB (0x3D), and CMP_Z_LSB (0x3E).
9.17.2 M_CTRL_REG2 (0x5C) register
0: No action taken, or one-shot measurement complete. measurements, clear this bit, and return to Standby mode. m_os[2:0] Oversample ratio (OSR ) for magnetometer data (see Table 95).
- When operating in hybrid mode, the effective ODR for eac h sensor is half of the frequency selected in the CTRL_REG1[dr] and
CTRL_REG1[aslp_rate] bit fields. Figure 124. M_CTRL_REG2 register Table 94. M_CTRL_REG2 bit descriptions read mode. Please refer to the register map auto-increment address column for further information. 0: Magnetic min/max detection function is enabled (default). 1: Magnetic min/max detection function is disabled. registers at the end of each ODR cycle with the maximum and minimum magnetic measurements from each axis. negative full-scale values).This bit is automatically cleared after the reset is completed. 00: Automatic magnetic reset at the beginning of each ODR cycle (default). 01: Automatic magnetic reset every 16 ODR cycles. 10: Automatic magnetic reset every 512 ODR cycles.
9.17.3 M_CTRL_REG3 (0x5D) register
9.17.4 M_INT_SRC (0x5E) register
Figure 125. M_CTRL_REG3 register Table 95. M_CTRL_REG3 bit descriptions in order for the automatic hard-iron compensation function to have any effect. function does not have any effect on the output data. m_aslp_os[2:0] Defines magnetometer OSR in Auto-Sleep mode. See Table 95. X, Y and Z reference values are all updated when the function triggers on any of the X, Y, or Z axes. 1: Only the reference value for the axis that triggered the detection event is updated. m_st_z Enables Z-axis magnetic se lf-test function when set to 1. m_st_xy[1:0] Enables both X and Y axes magnetic self-test function simultaneously when set to a value greater than 2’b00. X and Y magnetic self-test is disabled when this field is set to 2'b00. Table 96. M-cell OSR versus ODR Figure 126. M_INT_SRC register Table 97. M_INT_SRC bit description 0: Magnetic threshold event has not been detected. 1: Magnetic threshold event has been detected. 0: Magnetic vector magnitude change event has not been detected. 1: Magnetic vector magnitude change event has been detected.
76 Freescale Semiconductor, Inc.
9.17.5 Magnetometer Vector Magnitude Function
interface. Please refer to Freescale application note AN4458.
9.17.6 M_VECM_CFG (0x69) register
0: No new magnetic data is available. 1: New magnetic data is available. Figure 127. M_VECM_CFG register Table 98. M_VECM_CFG bit descriptions With event latching enabled, the src_m_vecm interrupt flag may only be cleared by reading the M_INT_SRC register. to the user reading the flag. 0: The ASIC uses the current magnetic output data as the initial reference values at the time the m_vecm_en bit is set. 0: The function updates the reference values with the current X/Y/Z magnetic data when the event is triggered. 1: The function does not update the reference values when the event is triggered. M_VECM_INIT_X/Y/Z registers in real time when the function is enabled. data or the values stored in the M_VECM_INIT_X/Y/Z registers depending on the state of m_vecm_initm. Note: The magnetic vector magnitude function will only function correctly up to a maximum ODR of 400 Hz. 0: The system excludes the src_m_vecm event flag when evaluating the Auto-Sleep function. 1: The system includes the src_m_vecm event flag when evaluating the Auto-Sleep function. 0: Magnetic vector magnitude interrupt is disabled. 1: Magnetic vector magnitude interrupt is enabled. 0: Magnetic vector magnitude interrupt is output on INT2 pin. 1: Magnetic vector magnitude interrupt is output on INT1 pin.
9.17.7 M_VECM_THS_MSB (0x6A) register
9.17.8 M_VECM_THS_LSB (0x6B) register
9.17.9 M_VECM_CNT (0x6C) register
9.17.10 M_VECM_INITX_MSB (0x6D) register
Figure 128. M_VECM_THS_MSB register Table 99. M_VECM_THS_MSB bit descriptions m_vecm_ths[14:8] Seven most significant bits of 15-bit unsigned magnetic vector magnitude threshold. Resolution is 0.1 μT/LSB. Figure 129. M_VECM_THS_LSB register Figure 130. M_VECM_CNT register Table 100. M_VECM_CNT bit description in hybrid mode, the effective ODR is reduced by a factor of two, making the debounce time for this example 300 ms. Figure 131. M_VECM_INITX_MSB register Table 101. M_VECM_INITX_MSB bit description M_VECM_CFG[m_vecm_initm] = 1.
78 Freescale Semiconductor, Inc.
9.17.11 M_VECM_INITX_LSB (0x6E) register
9.17.12 M_VECM_INITY_MSB (0x6F) register
9.17.13 M_VECM_INITY_LSB (0x70) register
9.17.14 M_VECM_INITZ_MSB (0x71) register
Figure 132. M_VECM_INITX_LSB register Table 102. M_VECM_INITX_LSB bit description M_VECM_CFG[m_vecm_initm] = 1. Figure 133. M_VECM_INITY_MSB register Table 103. M_VECM_INITY_MSB bit description M_VECM_CFG[m_vecm_initm] = 1. Figure 134. M_VECM_INITY_LSB register Table 104. M_VECM_INITY_LSB bit description M_VECM_CFG[m_vecm_initm] = 1. Figure 135. M_VECM_INITZ_MSB register Table 105. M_VECM_INITZ_MSB bit description M_VECM_CFG[m_vecm_initm] = 1.
9.17.15 M_VECM_INITZ_LSB (0x72) register
Figure 136. M_VECM_INITZ_LSB register Table 106. M_VECM_INITZ_LSB bit description M_VECM_CFG[m_vecm_initm] = 1.
80 Freescale Semiconductor, Inc.
10 Mounting Guidelines for the Qu ad Flat No Lead (QFN) Package
Printed Circuit Board (PCB) layout is a critical portion of the total design. The footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the PCB and the package. With the correct footprint, the packages will self-align when subjected to a solder reflow process. These guidelines are for soldering and mounting the Quad Flat No-Lead (QFN) package inertial sensors to PCBs. The purpose is to minimize the stress on the package after board mounting. The FXOS8700CQ uses the QFN package platform. This section describes suggested methods of soldering these devices to the PCB for consumer applications.
10.1 Overview of sold ering considerations
Information provided here is based on experiments executed on QFN devices. They do not represent exact conditions present at a customer site. Hence, information herein should be used for guidance only and process and design optimizations are recommended to develop an application specific solution. It should be noted that with the proper PCB footprint and solder stencil designs, the package will self-align during the solder reflow process.
10.2 Halogen content
This package is designed to be Halogen Free, exceeding most industry and customer standards. Halogen Free means that no homogeneous material within the assembly package shall contain chlorine (Cl) in excess of 700 ppm or 0.07% weight/weight or bromine (Br) in excess of 900 ppm or 0.09% weight/weight.
10.3 PCB mounting recommendations
- The PCB land should be designed with Non-Solder Mask Defined (NSMD) as shown in Figure 138 and Figure 139 2. No additional via pattern underneath package. 3. PCB land pad is 0.8 mm by 0.3 mm as shown in Figure 138 and Figure 139. 4. Solder mask opening = PCB land pad edge + 0.113 mm larger all around. 6. Stencil thickness is 100 or 125 μm. 7. Do not place any components or vias at a distance le ss than 2 mm from the package land area. This may cause additional package stress if it is too close to the package land area. 8. Signal traces connected to pads are as symmetric as possi ble. Put dummy traces on NC pads in order to have same length of exposed trace for all pads. 9. Use a standard pick and place process and equipment. Do not use a hand soldering process. 10. Do not use a screw down or stacking to fix the PCB into an enclosure because this could bend the PCB, putting stress on the package. 11. The PCB should be rated for the multiple lead- free reflow condition with max 260°C temperature. 12. No copper traces on top layer of PCB under the package. This will cause planarity issues with board mount. Freescale QFN sensors are compliant with Restrictions on Hazardous Substances (RoHS), having halide-free molding compound (green) and lead-free terminations. These terminations are compatible with tin-lead (Sn-Pb) as well as tin- silver-copper (Sn-Ag-Cu) solder paste soldering processes. Reflow profiles applicable to those processes can be used successfully for soldering the devices.
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Freescale Semiconductor, Inc. 83 CASE 2188-01 ISSUE O
84 Freescale Semiconductor, Inc. CASE 2188-01 ISSUE O
Table 107. Revision history 0.1 05/2012 • Corrected Figure 1 and updated Figure 4 to include acceleration values.
- Added Autonomous sub-bullets to first page.
- Table 2: Changed Cross-axis Max value to ±0.5 and Die-to-package alignment error Max value to ±2.
- Table 13: WHO_AM_I register, Default Hex Value numbers changed from 0xC4/0xC7 to 0xC7 removed Note 4 and 5.
- Section 9.1.7, WHO_AM_I register changed register numbers in Figure 16 from 0xC4/0xC7 to 0xC7 0.3 05/2012
- Table 2: Changed Nonlinearity values to TBD. Added Test Conditions for Noise rows.
- Table 3: Added Min values for Self-test output change for X-axis and Y-axis rows.
- Table 5: Updated ODR values for Low-power acceleration mode, Normal-acceleration mode, Hybrid mode and Magnetic mode. Added max value for IddSTBY, Standby mode; added Typ values for VIH and VIL, all previously TBD. Added Typ value for 25° SCL, SDA pin leakage.
- Added Section 7.5, Hybrid mode.
- Table 13:. Deleted registers 0x79, 0x7A, 0x7B and 0x7C,
- Table 50: Updated a_ffmt_ths_xyz_en description.
- Table 51: Updated a_ffmt_trans_ths_en description.
- Updated descriptive paragraph for Section 9.11.3.
- Updated descriptive paragraph for Section 9.11.4. 1 06/2012
- Changed title of document.
- Table 3: updated Note 2. Tco spec updated, Hysteresis value updated, Updated Noise values for ODR = 6.25 Hz, OS = 256 and ODR = 1.56 Hz, OS = 1024. Updated Vst X-axis Typ value from -1500 to -1320 and Z- axis from TBD to 100.
- Table 4: Removed first 2 rows, X, Y, Z inertial alignment parameters and Typ values.
- Table 8: Added SCL, SDA pin leakage Typ value 4 nA, added SCL, SDA pin capacitance 3 pf.
- Replace Table 8 with updated parameters.
- Updated section 5.2 SPI interface characteristics.
- Table 94: updated m_st_xy[1:0] bit description.
Rev. 1 Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/Freescale/Docs/TermsandConditions.htm. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. All rights reserved. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http:/www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp.