FXO-HC735RGB-125 FOX | Alldatasheet
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Features
Tri-State Enable / Disable Feature Industry Standard Package Gold over Nickel Termination Finish OUTPUT Enable / DisableV GND DD PRESSX FOX ASICs O
for ETHERNET Model: FXO-HC735RGB-125 Page 2 of 2 © 2010 FOX ELECTRONICS | ISO9001:2000 Certified | FOXONLINE HCMOS 7 x 5mm 3.3V 50ppm XO Freq: 125MHz Phase Jitter is integrated from HP3048 Phase Noise Measurement System; measured directly into 50 ohm input; VDD = 3.3V. TIE was measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software; VDD = 3.3V. Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications) Rj and Dj, measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software. Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications) DWG-100717 | Rev. 6/2/2010 Dimensional Drawing & Pad Layout Phase Jitter & Time Interval Error (TIE) (Typical Measurements) Frequency Phase Jitter (12kHz to 20MHz) T I E (Sigma of Jitter Distribution) Units 125 MHz 0.75 2.7 pS RMS Random & Deterministic Jitter Composition (Typical Measurements) Frequency Random (Rj) (pS RMS) Deterministic (Dj) (pS P-P) Total Jitter (Tj) (14 x Rj) + Dj 125 MHz 1.20 8.0 25.2 pS Pin Functional Description Pin # Name Type Function
1 E / D 1 Logic Enable / Disable Control of Output (0 = Disabled)
2 GND Ground Electrical Ground for V DD
3 Output Output HCMOS Oscillator Output
4 VDD
2 Power Power Supply Source Voltage
Points N. C. Hi Z No Connection (Factory Use ONLY) NOTES: 1 Includes pull-up resistor to VDD to provide output when the pin (1) is No Connect. 2 Installation should include a 0.01µF bypass capacitor placed between VDD (Pin 4) and GND (Pin 2) to minimize power supply line noise. GND E/D HCMOS LOAD (15 pF) N C # 4 # 3# 2 # 1 OUT 0.01 F DDV N C