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  • Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 30

Technical content

Features

  • 1.95 V to 3.6 V supply voltage (VDD)
  • 1.62 V to VDD IO voltage (VDDIO)
  • Ultra small 2 mm x 2 mm x 0.85 mm, 0.4 mm pitch, 10-pin package
  • Full-scale range ±1000 T
  • Sensitivity of 0.10 T
  • Noise down to 0.25 T rms
  • Output Data Rates (ODR) up to 80 Hz
  • 400 kHz Fast Mode compatible I 2C interface
  • Low-power, single-shot measurement mode
  • RoHS compliant

Applications

  • Electronic Compass (e-compass)
  • Location-Based Services Ruggedized Target markets
  • Smartphones, personal navigation devices, robotics, UAVs , speed sensing, current sensing and wrist watches with embedded electronic compasses (e-compass) function.

Table 1. Ordering information

2 Freescale Semiconductor, Inc. Related Documentation The MAG3110 device features and operations are described in a variety of reference manuals, user guides, and application notes. To find the most-current versions of these documents: 1. Go to the Freescale homepage at: http://www.freescale.com/ 2. In the Keyword search box at the top of the page, enter the device number MAG3110. 3. In the Refine Your Result pane on the left, click on the Documentation link.

Contents

1 Block diagram and pin description

Figure 1. Block diagram Figure 2. Pin connections and measurement coordinate system Figure 3. Device marking diagram

6 MAG

4 Freescale Semiconductor, Inc.

1.1 Application circuit

supply rail as shown in Figure 4. VDDIO supplies power for the digital I/O pins SCL, SDA, and INT1. signals SCL and SDA will clamp any logic signals through their internal ESD protection diodes. Figure 4. Electrical connection Table 2. Pin descriptions

1 Cap-A Bypass cap for internal regulator

3 NC Do not connect

4 Cap-R Magnetic reset pulse circuit capacitor connection

9 INT1 Interrupt - active high output

10 GND GND

2 Operating and Electrical Specifications

2.1 Operating characteristics

Table 3. Operating characteristics @ VDD = 2.4 V, VDDIO = 1.8 V, T = 25°C unless otherwise noted.

  1. Output data range is the sum of ±10000 LSBs full-scale range, ±10000 LSBs user defined offset (provided that CTRL_REG2[RAW] = 0) and
  2. Hysteresis is measured from 0 T to 1000 T to 0 T and from 0 T to -1000 T to 0 T.
  3. Best-fit straight line over the 0 to ±1000 T full-scale range.
  4. OS = Over Sampling Ratio.

6 Freescale Semiconductor, Inc.

2.2 Absolute maximum ratings

extended periods may affect device reliability. Table 4. Maximum ratings Table 5. ESD and latchup protection characteristics cause the part to otherwise fail. This device is sensitive to ESD, improper handling can cause permanent damage to the part.

2.3 Electrical characteristics

Table 6. Electrical characteristics @ VDD = 2.4 V, VDDIO = 1.8 V, T = 25°C unless otherwise noted

  1. ODR = Output Data Rate; OS = Over Sampling Ratio.
  2. Please see Table 32 for all ODR and OSR setting combinations, as well as corresponding current consumption and noise levels.
  3. Time to obtain valid data from STANDBY mode to ACTIVE Mode.

8 Freescale Semiconductor, Inc.

2.4 I 2C Interface characteristics

Table 7. I2C slave timing values(1)

  1. All values are referred to VIH (min) and VIL (max) levels.
  2. tHD;DAT is the data hold time that is measured from the falling edge of SCL; the hold time applies to data in transmission and the acknowledge.
  3. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH (min) of the SCL signal) to bridge the

undefined region of the falling edge of SCL.

  1. The maximum tHD;DAT could be must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. This device may stretch the LOW

period (tLOW) of the SCL signal.

  1. tVD;DAT = time for Data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
  2. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
  3. A Fast mode I2C device can be used in a Standard mode I2C system, but the requirement tSU;DAT 250 ns must then be met. This will

specification) before the SCL line is released. Also the acknowledge timing must meet this setup time.

  1. Cb = total capacitance of one bus line in pF.
  2. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns.

this when considering bus timing.

Figure 5. I2C slave timing diagram

2.5 I 2C pullup resistor selection

state. The value of the pullup resistors depends on the system I2C clock rate and the total capacitive load on the I2C bus. Lower resistance value pullup resistors consume more power, but enable higher I2C clock operating frequencies. operation, pullup resistor values of 1k (or lower) may be required.

10 Freescale Semiconductor, Inc.

3 Modes of Operation

4 Functionality

magnetic transducer for sensing and an ASIC for control and digital I2C communications.

4.1 Factory calibration

“Register Descriptions,” on page 15).

4.2 Digital interface

compliant with Fast mode (400 kHz), and Normal mode (100 kHz) I2C standards.

4.2.1 General I 2C operation

factors including the pullup resistor values, and total bus capacitance (trace + device capacitance). remains stable low during the high period of the acknowledge clock period. support clock stretching. Not all master devices recognize clock stretching. This part supports clock stretching. Table 8. Modes of operation description STANDBY I 2C communication is possible. Only POR and Digital blocks are enabled, the Analog subsystem is disabled. ACTIVE I 2C communication is possible. All blocks are enabled (POR, Digital, Analog). Table 9. Serial interface pin description

Freescale Semiconductor, Inc. 11 A low to high transition on the SDA line while the SCL line is high is defined as a stop condition (SP) signal. A write or burst write is always terminated by the master issuing the SP signal. A master should properly terminate a read by not acknowledging a byte at the appropriate time in the protocol. A master may also issue a repeated start signal (SR) during a transfer. The 7-bit I2C slave address assigned to MAG3110 is 0x0E (standard); the address assigned to FXMS3110CD is 0x0F (Windows™ 8).

4.2.2 I 2C Read/Write operations

The master (or MCU) transmits a start condition (ST) to the MAG3110, followed by the slave address, with the R/W bit set to “0” for a write, and the MAG3110 sends an acknowledgement. Then the master (or MCU) transmits the address of the register to read and the MAG3110 sends an acknowledgement. The master (or MCU) transmits a repeated start condition (SR), followed by the slave address with the R/W bit set to “1” for a read from the previously selected register. The MAG3110 then acknowledges and transmits the data from the requested register. The master does not acknowledge (NAK) the transmitted data, but transmits a stop condition to end the data transfer. Multiple byte read When performing a multi-byte or “burst” read, the MAG3110 automatically increments the register address read pointer after a read command is received. Therefore, after following the steps of a single byte read, multiple bytes of data can be read from sequential registers after each MAG3110 acknowledgment (AK) is received until a no acknowledge (NAK) occurs from the master followed by a stop condition (SP) signaling the end of transmission. Single byte write T o start a write command, the master transmits a start condition (ST) to the MAG3110, followed by the slave address with the R/W bit set to “0” for a write, and the MAG3110 sends an acknowledgement. Then the master (or MCU) transmits the address of the register to write to, and the MAG3110 sends an acknowledgement. Then the master (or MCU) transmits the 8-bit data to write to the designated register and the MAG3110 sends an acknowledgement that it has received the data. Since this transmission is complete, the master transmits a stop condition (SP) to end the data transfer. The data sent to the MAG3110 is now stored in the appropriate register. Multiple byte write The MAG3110 automatically increments the register address write pointer after a write command is received. Therefore, after following the steps of a single byte write, multiple bytes of data can be written to sequential registers after each MAG3110 acknowledgment (ACK) is received.

12 Freescale Semiconductor, Inc. Figure 6. I2C timing diagram

4.2.3 Fast Read mode

(OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, OUT_Z_LSB).

4.2.4 User offset corrections

board mount. These values may be used to compensate for hard-iron interference and zero-flux offset of the sensor. (CTRL_REG2[RAW] = 0), or can be read out uncorrected for user offset values (CTRL_REG2[RAW] = 1).

Freescale Semiconductor, Inc. 13

4.2.5 INT1

The DR_STATUS register (see section 5.1.1) contains the ZYXDR bit which denotes the presence of new measurement data on one or more axes. Software polling can be used to detect the transition of the ZYXDR bit from 0 to 1 but, since the ZYXDR bit is also logically connected to the INT1 pin, a more efficient approach is to use INT1 to trigger a software interrupt when new measurement data is available as follows: 1. Enable automatic resets by setting AUTO_MRS T_EN bit in CTRL_REG2 (CTRL_REG2 = 0b1XXXXXX). 2. Put MAG3110 in ACTIVE mode (CTRL_REG1 = 0bXXXXXX01). 3. Idle until INT1 goes HIGH and activates an in terrupt service routine in the user software. 4. Read magnetometer data as required from registers 0x01 to 0x06. INT1 is cleared when register 0x01 OUT_X_MSB is read. 5. Return to idle in step 3.

4.2.6 Triggered Measurements

Set the TM bit in CTRL_REG1 when you want the part to acquire only one sample on each axis. See table below for details. The anti-aliasing filter in the A/D converter has a finite delay before the output “settles”. The output data for the first ODR period after getting out of Standby mode is expected to be slightly off. This effect will be more pronounced for the lower over-sampling settings since with higher settings the error of the first acquisition will be averaged over the total number of samples. Therefore, it is not recommended to use TRIGGER MODE (CTRL_REG1[AC] =0, CTRL_REG1[TM] =1) measurements for applications that require high accuracy, especially with low over-sampling settings. Table 10. AC TM Description 0 0 ASIC is in low power standby mode. The ASIC will exit standby mode, perform one measurement cycle based on the programmed ODR and OSR setting, update the I2C data registers and re- enter standby mode.

10 The ASIC will perform continuous measurements based on the current OSR and

ODR settings. The ASIC will continue the current measurement at the fastest applicable ODR for the user programmed OSR. The ASIC will return back to the programmed ODR after completing the triggered measurement.

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4.2.7 MAG3110 Setup Examples

Continuous measurements with ODR = 80 Hz, OSR = 1 1. Enable automatic magnetic sensor re sets by setting bit AUTO_MRST_EN in CTRL_REG2. (CTRL_REG2 = 0x80) 2. Put MAG3110 in active mode 80 Hz ODR with OSR = 1 by writing 0x01 to CTRL_REG1 (CTRL_REG1 = 0x01) 3. At this point it is possible to sync with MAG3110 utilizi ng INT1 pin or using polling of the DR_STATUS register as explained in section 4.2.5. Continuous measurements with ODR = 0.63 Hz, OSR = 2 1. Enable automatic magnetic sensor re sets by setting bit AUTO_MRST_EN in CTRL_REG2. (CTRL_REG2 = 0x80) 2. Put MAG3110 in active mode 0.63 Hz ODR with OSR = 2 by writing 0xC9 to CTRL_REG1 (CTRL_REG1 = 0xC9) 3. At this point, it is possible to sync with MAG3110 utiliz ing INT1 pin or using polling of the DR_STATUS register as explained in section 4.2.5. Triggered measurements with ODR = 10 Hz, OSR = 8 1. Enable automatic magnetic sensor re sets by setting bit AUTO_MRST_EN in CTRL_REG2. (CTRL_REG2 = 0x80) 2. Initiate a triggered measurem ent with OSR = 128 by writing 0b00011010 to CTRL_REG1 (CTRL_REG1 = 0b00011010). 3. MAG3110 will acquire the triggered meas urement and go back into STANDBY mode. It is possible at this point to sync on INT1 or resort to polling of DR_STATUS register to read the acquired data out of MAG3110. 4. Go back to step 2 based on application needs.

5 Register Descriptions

Table 11. Register Address Map

  1. Fast Read mode for quickly reading the Most Significant Bytes (MSB) of the sampled data.
  2. Register contents are preserved when transitioning from “ACTIVE” to “STANDBY” mode.
  3. Modification of this register’s contents can only occur when device is “STANDBY” mode, except the TM and AC bit fields in CTRL_REG1

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5.1 Sensor Status

5.1.1 DR_STATUS (0x00)

to the OUT_X, OUT_Y, and OUT_Z registers. bytes of the data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all active channels are read. previous data is overwritten. ZOW is cleared any time OUT_Z_MSB register is read. previous data is overwritten. YOW is cleared any time OUT_Y_MSB register is read. previous data is overwritten. XOW is cleared any time OUT_X_MSB register is read. data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the enabled channels are read. ZDR is set to 1 whenever new Z-axis data acquisition is completed. ZDR is cleared any time OUT_Z_MSB register is read. YDR is set to 1 whenever new Y-axis data acquisition is completed. YDR is cleared any time OUT_Y_MSB register is read. XDR is set to 1 whenever new X-axis data acquisition is completed. XDR is cleared any time OUT_X_MSB register is read. Table 12. DR_STATUS Register Table 13. DR_STATUS Descriptions X, Y, Z-axis Data Overwrite. Default value: 0. 0: No data overwrite has occurred. 1: Previous X or Y or Z data was overwritten by new X or Y or Z data before it was completely read. Z-axis Data Overwrite. Default value: 0. 0: No data overwrite has occurred. 1: Previous Z-axis data was overwritten by new Z-axis data before it was read. Y-axis Data Overwrite. Default value: 0. 0: No data overwrite has occurred. 1: Previous Y-axis data was overwritten by new Y-axis data before it was read. 0: No data overwrite has occurred. 1: Previous X-axis data was overwritten by new X-axis data before it was read. X or Y or Z-axis new Data Ready. Default value: 0. 0: No new set of data ready. 1: New set of data is ready. Z-axis new Data Available. Default value: 0. 0: No new Z-axis data is ready. 1: New Z-axis data is ready. Z-axis new Data Available. Default value: 0. 0: No new Y-axis data is ready. 1: New Y-axis data is ready. Z-axis new Data Available. Default value: 0. 0: No new X-axis data is ready. 1: New X-axis data is ready.

5.1.2 OUT_X_MSB (0x01), OUT_X_LSB (0x02), OUT_Y_MSB (0x03), OUT_Y_LSB (0x04),

X-axis, Y-axis, and Z-axis 16-bit output sample data of the magnetic field strength expressed as signed 2's complement numbers. 1000 T full scale range and the zero-flux offset ranging up to 1000 T). ranging between -10,000 to 10,000 bit counts are included. in the auto-incrementing address range of 0x00 to 0x06. Data acquisition is a sequential read of 6 bytes. read regardless of FR bit setting. ensure that the latest acquisition data is being read. Table 14. OUT_X_MSB Register Table 15. OUT_X_LSB Register Table 16. OUT_Y_MSB Register Table 17. OUT_Y_LSB Register Table 18. OUT_Z_MSB Register Table 19. OUT_Z_LSB Register

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5.2 Device ID

5.2.1 WHO_AM_I (0x07)

5.2.2 SYSMOD (0x08)

The read-only system mode register indicates the current device operating mode.

5.3 User Offset Correction

5.3.1 OFF_X_MSB (0x09), OFF_X_LSB (0x0A), OFF_Y_MSB (0x0B), OFF_Y_LSB (0x0C),

measurement registers when CTRL_REG2[RAW] = 0 is therefore -30,000 to 30,000 bit counts and is computed without clipping. is forced to be zero irrespective of the value written by the user. likely scenario) then the user offset registers can be ignored and the CTRL_REG2[RAW] bit should be set to 1. always applied to the measured magnetic data irrespective o the setting of CTRL_REG2[RAW]. Table 20. WHO_AM_I Register Table 21. SYSMOD Register

000000 SYSMOD1 SYSMOD0

Table 22. SYSMOD Description System Mode. Default value: 00. 10: ACTIVE mode, non-RAW user-corrected data. Table 23. OFF_X_MSB Register Table 24. OFF_X_LSB Register Table 25. OFF_Y_MSB Register

5.4 Temperature

5.4.1 DIE_TEMP (0x0F)

but the output range is limited to -40°C to 125°C. The temperature data is updated on every measurement cycle.

5.5 Control Registers

5.5.1 CTRL_REG1 (0x10)

Table 26. OFF_Y_LSB Register Table 27. OFF_Z_MSB Register Table 28. OFF_Z_LSB Register Table 29. TEMP Register Table 30. CTRL_REG1 Register Table 31. CTRL_REG1 Description DR[2:0] Output data rate selection. Default value: 000. See Table 32 for more information. and active modes of operation. See Table 32 for more information. Fast Read selection. Default value: 0. 0: The full 16-bit values are read. 1: Fast Read, 8-bit values read from the MSB registers (Auto-increment skips over the LSB register in burst-read mode). 0: Normal operation based on AC condition. If part is in ACTIVE mode, any measurement in progress will continue with the highest ODR possible for the selected OSR.

20 Freescale Semiconductor, Inc. Table 32. Over-Sampling Ratio and Data Rate Description

5.5.2 CTRL_REG2 (0x11)

Table 33. CTRL_REG2 Register Table 34. CTRL_REG2 Description Automatic Magnetic Sensor Reset. Default value: 0. 0: Automatic magnetic sensor resets disabled. 1: Automatic magnetic sensor resets enabled. Similar to Mag_RST, however, the resets occur automatically before each data acquisition. Data output correction. Default value: 0. 0: Normal mode: data values are corrected by the user offset register values. 1: Raw mode: data values are not corrected by the user offset register values. Magnetic Sensor Reset (One-Shot). Default value: 0. 1: Reset cycle initiate or Reset cycle busy/active. When the cycle is finished, value returns to 0.

22 Freescale Semiconductor, Inc.

6 Geomagnetic Field Maps

The magnitude of the geomagnetic field varies from 25 T in South America to about 60 T over Northern China. The horizontal component of the field varies from zero at the magnetic poles to 40 T. These web sites have further information: http://wdc.kugi.kyoto-u.ac.jp/igrf/ http://geomag.usgs.gov/

Freescale Semiconductor, Inc. 23 Geomagnetic Field Sensitivity Full-Scale Range(0.1 T) (1000 T) MAG3110MAG3110

24 Freescale Semiconductor, Inc.

7 PCB Guidelines

Surface mount Printed Circuit Board (PCB) layout is a critical portion of the total design. The footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the PCB and the package. With the correct footprint, the packages will self-align when subjected to a solder reflow process. These guidelines are for soldering and mounting the Dual Flat No-Lead (DFN) package inertial sensors to PCBs. The purpose is to minimize the stress on the package after board mounting. The MAG3110 digital output magnetometers use the DFN package platform. This section describes suggested methods of soldering these devices to the PCB for consumer applications. Please see Freescale application note AN4247,”Layout Recommendation for PCBs Using a magnetometer Sensor” for a technical discussion on hard and soft-iron magnetic interference and general guidelines on layout and component selection applicable to any PCB using a magnetometer sensor. Freescale application note AN1902, “Quad Flat Pack No-Lead (QFN) Micro Dual Flat Pack No-Lead (DFN)” discusses the DFN package used by the MAG3110, PCB design guidelines for using DFN packages and temperature profiles for reflow soldering.

7.1 Overview of Sold ering Considerations

Information provided here is based on experiments executed on DFN devices. They do not represent exact conditions present at a customer site. Hence, information herein should be used as guidance only and process and design optimizations are recommended to develop an application specific solution. It should be noted that with the proper PCB footprint and solder stencil designs, the package will self-align during the solder reflow process.

7.2 Halogen Content

This package is designed to be Halogen Free, exceeding most industry and customer standards. Halogen Free means that no homogeneous material within the assembly package shall contain chlorine (Cl) in excess of 700 ppm or 0.07% weight/weight or bromine (Br) in excess of 900 ppm or 0.09% weight/weight.

7.3 PCB Mounting Recommendations

  1. The PCB land should be designed as Non Solder Mask Defined (NSMD) as shown in Figure 7. 2. No additional via pattern underneath package. 3. PCB land pad is 0.6 mm x 0.225 mm as shown in Figure 7. 4. Solder mask opening = PCB land pad edge + 0.125 mm larger all around = 0.725 mm x 1.950 mm 6. Stencil thickness is 100 or 125 mm. 7. Do not place any components or vias at a distance le ss than 2 mm from the package land area. This may cause additional package stress if it is too close to the package land area. 8. Signal traces connected to pads are as symmetric as possi ble. Put dummy traces on NC pads in order to have same length of exposed trace for all pads. 9. Use a standard pick and place process and equipment. Do not use a hand soldering process. 10. Assemble PCB when in an enclosure. Using caution, determi ne the position of screw down holes and any press fit. It is important that the assembled PCB remain flat after assembly to keep electronic operation of the device optimal. 11. The PCB should be rated for the multiple lead- free reflow condition with max 260°C temperature. 12. No copper traces on top layer of PC B under the package. This will cause planarity issues with board mount. Freescale DFN sensors are compliant with Restrictions on Hazardous Substances (RoHS), having halide free molding compound (green) and lead-free terminations. These terminations are compatible with tin-lead (Sn-Pb) as well as tin-silver-copper (Sn-Ag-Cu) solder paste soldering processes. Reflow profiles applicable to those processes can be used successfully for soldering the devices.

Figure 7. Footprints and Soldering Masks (dimensions in mm)

26 Freescale Semiconductor, Inc. PACKAGE DIMENSIONS CASE 2154-02 ISSUE A 10-PIN DFN

Freescale Semiconductor, Inc. 27 PACKAGE DIMENSIONS CASE 2154-02 ISSUE A 10-PIN DFN

28 Freescale Semiconductor, Inc. PACKAGE DIMENSIONS CASE 2154-02 ISSUE A 10-PIN DFN

Table 35. Revision history

  • Updated content on page 1.
  • Updated pin descriptions in Table 1.
  • Updated pin connection drawing and Figure 2 to reflect horizontal bar for pin 1.
  • Added Figure 3, Device Marking Diagram
  • Updated Output Data Range row in Table 2.
  • Updated Figure 4 to include pin names.
  • Updated Bit 7 in Table 31 and 32 for emphasis. Changed description as highlighted in Red and bold text. 9 09/2012
  • Added FXMS3110CDR1, Windows 8 option to ordering information.
  • Table 1: Updated Pin 6, SDA, description.
  • Table 2: added Sensor die-to-package row.
  • Updated Table 5, Boot time from power row Max value from deleted, Typ value added, 1.7.
  • Deleted section 4.1. Updated I 9.1 10/2012 • Table 2: added Sensor die-to-package row. 9.2 02/2013
  • Updated ordering table, deleted MAG3110FCR2 option.
  • Table title for Table 2 and Table 5: Updated VDD = 1.8 V to VDD = 2.4 V and added VDDIO = 1.8 V. “The user offsets are automatically subtracted by the MAG3110... “

Document Number: MAG3110 Rev. 9.2 Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware, Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of Freescale CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc.