FXMAR2102 ONSEMI | Alldatasheet
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© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FXMAR2102 • Rev. 1.0.3 FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications FXMAR2102 Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications
Features
Bi-Directional Interface between Any Two Levels: 1.65 V to 5.5 V No Direction Control Needed Internal 10 KΩ Pull-Up Resistors System GPIO Resources Not Required when OE Tied to VCCA I2C-Bus® Isolation A/B Port VOL = 175 mV (Typical), VIL = 150 mV, IOL = 6 mA Open -Drain Inputs / Outputs Works in Push Pull Environment Accommodates Standard-Mode and Fast-Mode I2C-Bus Devices Supports I2C Clock Stretching & Multi-Master Fully Configurable: Inputs and Outputs Track VCC Non -Preferential Power-Up; Either VCC Can Power-Up First Outputs Switch to 3-State if Either VCC is at GND Tolerant Output Enable: 5 V Packaged in 8-Terminal Leadless MicroPak™ (1.6 mm x 1.6 mm) and Ultrathin MLP (1.2 mm x 1.4 mm) ESD Protection Exceeds: - B Port: 8 kV HBM ESD (vs. GND & vs. VCCB ) - All Pins: 4 kV HBM ESD (per JESD22-A114) - 2 kV CDM (per JESD22-C101)
Description
The FXMAR2102 is a high -performance configurable dual-voltage-supply translator for bi-directional voltage translation over a wide range of input and output voltages levels. The FXMAR2102 also works in a push- pull environment. It is intended for use as a voltage translator between I2C-Bus® compliant masters and slaves. Internal 10 KΩ pull-up resistors are provided. The device is designed so the A port tracks the VCCA level and the B port tracks the VCCB level. This allows for bi-directional A/B-port voltage translation between any two levels from 1.65 V to 5.5 V. VCCA can equal VCCB from 1.65 V to 5.5 V. Either VCC can be powered-up first. Internal power-down control circuits place the device in 3-state if either VCC is removed. The two ports of the device have automatic direction- sense capability. Either port may sense an input signal and transfer it as an output signal to the other port.
Ordering Information
-40 to +85°C BU 8-Lead MicroPak™, 1.6 mm Wide 5000 Units on Tape and Reel FXMAR2102 UMX 8-Lead Ultrathin MLP, 1.2 mm x 1.4 mm
Figure 1. Block Diagram, 1 of 2 Channels
Figure 2. MicroPak™ (Top-Through View) Figure 3. UMLP (Top -Through View)
1 V CCA A- Side Power Supply
4 GND Ground
5 OE Output Enable Input
8 V CCB B- Side Power Supply
- If the OE pin is driven LOW, the FXMAR2102 is disabled and the A0, A1, B0, and B1 pins (including dynamic drivers)
are forced into 3-state and all four 10 KΩ internal pull-up resisters are decoupled from their respective VCC .
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FXMAR2102 • Rev. 1.0.3 4 FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications Absolute Maximum Ratings Stresses exceeding the Absolute M aximum R atings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Units VCCA , VCCB Supply Voltage –0.5 7.0 V VIN DC Input Voltage A Port –0.5 7.0 B Port –0.5 7.0 Control Input (OE) – 0.5 7.0 VO Output Voltage(2) An Outputs 3-State – 0.5 7.0 V Bn Outputs 3-State – 0.5 7.0 An Outputs Active – 0.5 VCCA + 0.5V Bn Outputs Active – 0.5 VCCB + 0.5 V IIK DC Input Diode Current A t VIN < 0 V – 50 mA IOK DC Output Diode Current At VO < 0 V – 50 mA At VO > VCC +50 IOH / IOL DC Output Source/Sink Current –50 +50 mA ICC DC V CC or Ground Current per Supply Pin ±100 mA PD Power Dissipation At 400 KHz 0.129 mW TSTG Storage Temperature Range –65 +150 °C ESD Electrostatic Discharge Capability Human Body Model, B-Port Pins 8 kV Human Body Model, All Pins (JESD22-A114) 4 Charged Device Mode, JESD22-C101 2 Note: 2. I O absolute maximum rating must be observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Units VCCA , VCCB Power Supply Operating 1.65 5.50 V VIN Input Voltage(3) A-Port 0 5.5 V B-Port 0 5.5 Control Input (OE) 0 V CCA ΘJA Thermal Resistance 8-Lead MicroPak™ 279 C°/W 8-Lead Ultrathin MLP 302 TA Free Air Operating Temperature –40 +85 °C Note: 3. All unused inputs and I/O pins must be held at VCCI or GND. VCCI is the VCC associated with the input side.
the device driving the OE pin.
- Apply power to the first VCC .
- Apply power to the second VCC .
- Drive the OE input HIGH to enable the device.
- Drive OE input LOW to disable the device.
- Remove power from either VCC .
- Remove power from the other VCC .
- Alternatively, the OE pin can be hardwired to VCCA
either VCC can be powered up or down first. Figure 4. Application Circuit
logic LOW of 0.4 V to the m aster. competition, given a 0.4 V VIL. Figure 6. Device Comparison
forever; however. This condition shuts down the I2C bus. condition from slave #2 to slave #1 and as the m aster. Figure 7. Bus Isolation
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FXMAR2102 • Rev. 1.0.3 9 FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications TA = –40°C to +85°C. Symbol Parameter Conditions V CCA (V) V CCB (V) Min. Typ. Max. Units VIHA High Level Input Voltage A Data Inputs An 1.65–5.50 1.65–5.50 VCCA – 0.4 V VCCA VIHB High Level Input Voltage B Data Inputs Bn 1.65–5.50 1.65–5.50 VCC B – 0.4 V VILA Low Level Input Voltage A V VCCA VILB Low Level Input VOL Low Level Output Voltage VIL = 0.15 V 0.4 V IOL = 6 mA IL Input Leakage Current Control Input OE, IOFF Power-Off Leakage Current An VIN or VO = 0 V to 5.5 V 0 5.50 ±2.0 µA Bn VIN or VO = 0 V to 5.5 V 5.50 0 ±2.0 IOZ 3-State Output Leakage(7) An, Bn VO = 0 V to 5.5 V, OE = VIL 5.50 5.50 ±2.0 µA An VO = 0 V to 5.5 V, OE = Don’t Care 5.50 0 ±2.0 Bn VO = 0 V to 5.5 V, OE = Don’t Care 0 5.50 ±2.0 ICCA /B Quiescent Supply Current(8,9) VIN = VCCI or Floating, 5.0 µA ICCZ Quiescent Supply Current(8) VIN = VCCI or GND, IO = 0, OE = VIL 1.65–5.50 1.65–5.50 5.0 µA ICCA Quiescent Supply Current(7) VIN = 5.5 V or GND, IO = 0, OE = Don’t Care, Bn to An 0 1.65–5.50 – 2.0 µA 1.65–5.50 0 2.0 ICCB Quiescent Supply Current(7) VIN = 5.5 V or GND, IO = 0, OE = Don’t Care, An to Bn 1.65–5.50 0 – 2.0 µA 0 1.65–5.50 2.0 R PU Resistor Pull-up Value VCCA & VCCB Sides 1.65–5.50 1.65–5.50 10 Ω Notes: 6. This table contains the output voltage for static conditions. Dynamic drive specifications are given in Dynamic Output Electrical Characteristics. 7. “Don’t Care” indicates any valid logic level. 8. V CCI is the VCC associated with the input side. 9. Reflects current per supply, VCCA or VCCB .
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FXMAR2102 • Rev. 1.0.3 10 FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications Dynamic Output Electrical Characteristics Output R ise / Fall Time(10) Output load: CL = 50 pF, RPU = NC, push / pull driver, and TA = -40°C to +85°C. Symbol Parameter VCCO (11) Typ. Typ. Typ. Typ. trise Output Rise Time; A Port, B Port(12) 3 4 5 7 ns tfall Output Fall Time; A Port, B Port(13) 1 1 1 1 ns Notes: 10. Output rise and fall times guaranteed by design simulation and characterization; not production tested. 11. VCCO is the VCC associated with the output side. 12. See Figure 12. 13. See Figure 13. Maximum Data Rate(14) Output load: CL = 50 pF, RPU = NC, push / pull driver, and TA = -40°C to +85°C. VCCA Direction VCCB Unit Minimum s 4.5 V to 5.5 V A to B 50 50 40 30 MHz B to A 50 50 40 40 3.0 V to 3.6 V A to B 50 50 40 19 MHz B to A 50 50 40 40 2.3 V to 2.7 V A to B 40 40 30 19 MHz B to A 40 40 30 30 1.65 V to 1.95 V A to B 40 40 30 19 MHz B to A 30 30 19 19 Note: 14. F-toggle guaranteed by design simulation; not production tested.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FXMAR2102 • Rev. 1.0.3 11 FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications AC Characteristics(15) Output Load: CL = 50 pF, RPU = NC , push / pull driver, and TA = -40°C to +85°C. Symbol Parameter VCCB Unit VCCA = 4.5 to 5.5 V tPLH A to B 1 3 1 3 1 3 1 3 ns B to A 1 3 2 4 3 5 4 7 tPHL A to B 2 4 3 5 4 6 5 7 ns B to A 2 4 2 5 2 6 5 7 tPZL OE to A 4 5 6 10 5 9 7 15 ns OE to B 3 5 4 7 5 8 10 15 tPLZ OE to A 65 100 65 105 65 105 65 105 ns OE to B 5 9 6 10 7 12 9 16 VCCA = 3.0 to 3.6 V tPLZ OE to A 100 115 100 115 100 115 100 115 ns OE to B 5 10 4 8 5 10 9 15 VCCA = 2.3 to 2.7 V tPLZ OE to A 100 115 100 115 100 115 100 115 ns OE to B 65 110 65 110 65 115 12 25 VCCA = 1.65 to 1.95 V tPHL A to B 5 8 3 7 3 7 3 7 ns B to A 4 8 3 7 3 7 3 7 tPZL OE to A 11 15 11 14 14 28 14 23 ns OE to B 6 14 6 14 6 14 9 16 tPLZ OE to A 75 115 75 115 75 115 75 115 ns OE to B 75 115 75 115 75 115 75 115 Notes: 15. AC characteristics are guaranteed by design and characterization. 16. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW ) (see Figure 15). Skew is guaranteed; not production tested.
Figure 8. AC Test Circuit Table 1. Propagation Delay Table(17)
- For tPZL and tPLZ testing, an external 2.2 KΩ pull-up resister to VCCO is required in order to force the I/O pins high
while OE is Low because when OE is low, the internal 10KΩ RPUs are decoupled from their respective VCC’s. Table 2. AC Load Table
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FXMAR2102 • Rev. 1.0.3 14 FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications Product-Specific Dimensions Symbol from JEDEC MO -220 Description NOM Value A Overall H eight 0.55 A1 PKG Standoff 0.012 A3 Lead Thickness 0.15 b L ead W idth 0.2 D B ody Length (X) 1.4 E B ody W idth (Y) 1.2 L L ead Length 0.3 e L ead Pitch 0.4 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
1.20±0.10
0.10 C A B
0.05 C 4 0.30±0.05 (7X) DETAIL A 0.20±0.05 (8X) 0.45 0.35 (7X) 0.625 0.25 (8X) 1.25 1.45 0.40 0.725 RECOMMENDED LAND PATTERN NOTES: A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC STANDARD. B. DIMENSIONS ARE IN MILLIMETERS. C. LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN. D. DRAWING FILENAME: MKT-UMLP08ArevD 0.40 (0.20) 4X 0.40±0.05 DETAIL A SCALE : 2X 0.20±0.05 45° SCALE : 2X LEAD OPTION 1 SCALE : 2X LEAD OPTION 2 R0.20 LEAD SHAPE AT PACKAGE EDGE PACKAGE EDGE A 1.40±0.10 B TOP VIEW 0.15±0.05 0.025±0.025 C SEATING PLANE 0.50±0.05 SIDE VIEW PIN #1 IDENT BOTTOM VIEW
1.60±0.10 1.60±0.10 TOP VIEW NOTES: A. PACKAGE CONFORMS TO JEDEC MO-255 VARIATION UAAD. B. DIMENSIONS ARE IN MILLIMETERS. C. LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN. D. DRAWING FILENAME: MKT-MAC08ArevE. 1 2 3 567 0.30±0.05 (0.15) (0.20) 0.30±0.05 BOTTOM VIEW 0.50 0.20±0.05(8X) 1.00±0.05 0.30±0.05 (7X) 0.05 C (0.20) 3X (0.09) DETAIL A SCALE 2:1 (0.10) RECOMMENDED LAND PATTERN 1.600.45 (2X) 0.40 (6X) 1.61 0.25 (8X) 0.50 PIN #1 IDENT A B C 0.025±0.025 0.50±0.05 SEATING PLANE DETAIL A
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