FXLS9XXXX NXP | Alldatasheet
Document overview
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- PDF pages: 254
Technical content
Datasheet sections
- 1 General description
- 2 Features
- 3 Applications
- 3.1 Automotive
- 3.2 Industrial
- 4 Ordering information
- 4.1 Ordering options
- 5 Marking
- 6 Application diagrams
- 6.1 DSI3 application diagrams
- 6.1.1 DSI3 discovery mode application diagram
- 6.2 PSI5 application diagrams
- 6.2.1 PSI5 parallel or universal mode application
- 6.2.2 PSI5 daisy chain mode application diagram
- 6.3 SPI application diagram
- 6.4 I2C application diagram
- 7 Block diagram
- 8 Device orientation diagrams
- 9 Pinning information
- 9.1 Pinning: SPI or I2C mode
- 9.2 Pin description: SPI or I2C mode
- 9.3 Pinning: DSI3 or PSI5 mode
- 9.4 Pin description: DSI3 or PSI5 mode
- 10 Electrical characteristics
- 10.1 Maximum ratings
- 10.2 Operating range - DSI / PSI5
- 10.3 Operating range - SPI / I2C
- 10.4 Electrical characteristics - supply and I/O
- 10.5 Electrical characteristics - temperature
- 10.6 Electrical characteristics - inertial sensor
- 10.7 Electrical characteristics - inertial sensor
- 10.8 Electrical characteristics - inertial sensor
- 10.9 Electrical characteristics - lateral inertial
- 10.10 Electrical characteristics - Z-axis inertial
- 10.11 Dynamic electrical characteristics - DSI3
- 10.12 Dynamic electrical characteristics - PSI5
- 10.13 Dynamic electrical characteristics - SPI
- 10.14 Dynamic electrical characteristics - I2C
- 10.15 Dynamic electrical characteristics - signal
- 10.16 Dynamic electrical characteristics - signal
- 10.17 Dynamic electrical characteristics - analog
- 10.18 Dynamic electrical characteristics - digital
- 10.19 Dynamic electrical characteristics -
- 10.20 Dynamic electrical characteristics - supply
- 11 Functional description
- 11.1 User accessible data array
- 11.1.1 User accessible data - general device
- 11.1.2 User accessible data - communication
- 11.1.3 User accessible data - sensor specific
- 11.1.4 User accessible data - sensor specific
- 11.1.5 User accessible data - traceability
- 11.2 Register definitions
- 11.2.1 Rolling counter register (COUNT)
- 11.2.2 Device status registers (DEVSTATx)
- 11.2.2.1 Channel 0 error flag (CH0_ERR)
- 11.2.2.2 Channel 1 error flag (CH1_ERR)
- 11.2.2.3 Communication error flag (COMM_ERR)
- 11.2.2.4 Memory or temperature error flag
- 11.2.2.5 Supply error flag (SUPPLY_ERR)
- 11.2.2.6 Test mode (TESTMODE)
- 11.2.2.7 Device reset (DEVRES)
- 11.2.2.8 Device initialization (DEVINIT)
- 11.2.2.9 VBUF under-voltage error (VBUFUV_ERR)
- 11.2.2.10 BUS IN under-voltage error (BUSINUV_
- 11.2.2.11 VBUF over-voltage error (VBUFOV_ERR)
- 11.2.2.12 Internal analog regulator voltage out of
- 11.2.2.13 Internal digital regulator voltage out of
- 11.2.2.14 Internal OTP regulator voltage out of range
- 11.2.2.15 Continuity monitor error (CONT_ERR)
- 11.2.2.16 NXP OTP array error (F_OTP_ERR)
- 11.2.2.17 User OTP array error (U_OTP_ERR)
- 11.2.2.18 User read/write array error (U_RW_ERR)
- 11.2.2.19 User OTP write in process status bit (U_W_
- 11.2.2.20 Channel 1 temperature sensor error
- 11.2.2.21 Channel 0 temperature sensor error
- 11.2.2.22 SPI MISO data mismatch error flag (MISO_
- 11.2.2.23 Oscillator training error (OSCTRAIN_ERR)
- 11.2.3 Communication protocol revision register
- 11.2.4 Margin read status register (MREAD_STAT)
- 11.2.4.1 Margin read active status (MARGIN_RD_
- 11.2.4.2 Margin read error status (MARGIN_RD_
Dual channel inertial sensor Rev. 6 — 8 February 2021 Product data sheet
1 General description
The FXLS9xxxx is a dual channel DSI3, PSI5, SPI, and I2C compatible lateral (X-axis or Y-axis) or vertical (Z-axis) inertial sensor.
2 Features
- Independent X-axis, Y-axis, or Z-axis ranges for each channel – Medium g ranges from ± 15.5 g to ± 150 g nominal full-scale range – High g ranges from ± 50 g to ± 500 g nominal full-scale range
- –40 °C to 125 °C operating temperature range
- DSI3 compatible – Discovery mode for physical location identification – High side bus switch output driver – Command and response mode support for device configuration – Periodic data collection mode support for sensor data transfers. – Background diagnostic mode support during periodic data collection mode
- PSI5 Version 2.1 compatible – Compatible modes: – P10P-500/3L – P10P-500/4H – A10P-228/1L – P10CRC-xxx/xx – P16CRC-xxx/xx – and many others – Programmable time slots with 1 µs resolution – Selectable baud rate: 125 kBd or 189 kBd – 10- and 16-bit data options – Selectable error detection: even parity, or 3-bit CRC – Optional daisy chain with external low side switch – Two-wire programming mode
- 32-bit SPI compatible serial interface – 3.3 V or 5 V single supply operation – Register read and write commands – Sensor data transmission commands – 12-bit data, left justified in a 16-bit data field – Command echo with 3-bit source identification – 2-bit basic status and 2-bit detailed status fields – 8-bit CRC
- I2C compatible serial interface (UM10204[1]) – Slave mode operation – Standard mode, fast mode, and fast mode plus support
- Independent programmable arming functions for each channel
- DSP – Dual, independent signal chains from ADC to Communications Interface – Up to a fourth order low-pass filter with rolloff frequency options from 12.5 Hz to 1500 Hz – Optional single pole high pass filter with fast startup and output rate
- Limiting – Optional moving average – Optional 16 to 1 output interpolation
- Pb-free 16-Pin QFN 4 mm x 4 mm x 1.45 mm package
3 Applications
3.1 Automotive
- Airbag, Collision/Crash detection
- Active suspension vibration monitoring
3.2 Industrial
- Machine condition monitoring
4 Ordering information
Table 1. Ordering information
4.1 Ordering options
Table 2. Ordering options
Table 2. Ordering options...continued
5 Marking
Figure 1. Part marking
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor
6 Application diagrams
6.1 DSI3 application diagrams
6.1.1 DSI3 discovery mode application diagram
BUS_I Optional Bus Termination BUSRTN IDATA BUS_O BUSIN BUSRTN BUSOUT aaa-030552 Figure 2. DSI3 discovery mode application diagram
description
Component value selection and range Comment R1 General purpose 330 Ω, 5 %,
200 PPM
The system level communication, EMC, and ESD testing determine the optimal value of this component. Optional bus termination for high inductance bus wire connections. For optimal EMC performance, this component along with C4 are to be placed as close to the BUS_I and BUSRTN connector pins as possible. C1 Ceramic 220 pF, 10 %, 50 V minimum, X7R The optimal value of this component should be determined by the system level communication, EMC, and ESD testing. For optimal EMC performance, this component along with R1 are to be placed as close to the BUS_I and BUSRTN connector pins as possible. C2 Ceramic 0.47 µF, 10 %, 10 V minimum, X7R The optimal value of this component should be determined based on the system level micro-cut immunity requirement. To achieve the specified power supply rejection, the minimum value including all tolerances is 0.22 µF. The maximum specified value including all tolerances is 2 µF. For optimal EMC performance, this component is to be placed as close to the VBUF and BUSRTN pins as possible. C3 Ceramic 100 pF, 10 %, 50 V minimum, X7R The optimal value of this component should be determined by the system level communication, EMC, and ESD testing. For optimal EMC performance, this component is to be placed as close to the BUS_O and BUSRTN connector pins as possible. C4 Ceramic 2.2 nF, 10 %, 50 V minimum, X7R The optimal value of this component should be determined by the system level communication, EMC, and ESD testing. Optional bus termination for high inductance bus wire connections. For optimal EMC performance, this component along with R1 are to be placed as close to the BUS_I and BUSRTN connector pins as possible. Note: The total bus capacitance must not exceed the values specified in the DSI3[2] standard. The external components are dependent on the bus master and bus impedance and may vary from application to application. Table 3. DSI3 discovery mode external component recommendations
6.2 PSI5 application diagrams
6.2.1 PSI5 parallel or universal mode application diagram
Figure 3. PSI5 parallel or universal mode application diagram resistance including all tolerances is 133 Ω. and BUSRTN connector pins as possible. Table 4. PSI5 parallel or universal mode external component recommendations
specified value including all tolerances is 2 µF. Note: The total bus capacitance must not exceed the values specified in the PSI5 standard. Table 4. PSI5 parallel or universal mode external component recommendations...continued rated temperature for operation. [2] If the high baud rate is used, NXP recommends reducing the value of C2. The actual value depends on the bus configuration and number of slaves.
6.2.2 PSI5 daisy chain mode application diagram
Figure 4. PSI5 daisy chain mode application diagram Table 5. PSI5 daisy chain mode external component recommendations
and BUSRTN connector pins as possible. specified value including all tolerances is 2 µF. Note: The total bus capacitance must not exceed the values specified in the PSI5 standard. current at the maximum rated temperature for operation. Table 5. PSI5 daisy chain mode external component recommendations...continued
6.3 SPI application diagram
Figure 5. SPI application diagram VCC power supply decoupling. Table 6. SPI external component recommendations
6.4 I2C application diagram
Figure 6. I2C application diagram Table 7. I2C external component recommendations
7 Block diagram
Figure 7. Dual channel internal block diagram
8 Device orientation diagrams
Figure 8. Orientation diagram Table 8. Dual axis device orientation
9 Pinning information
9.1 Pinning: SPI or I2C mode
Figure 9. Device pinout: SPI or I2C mode
9.2 Pin description: SPI or I2C mode
2 PCM1 / ARM1 Channel 1
- When the channel 1 arming output is selected, the pin can be configured as an open-drain, active low output with a pull-up current; or an open-drain, active high output with a pull-down current.
- When PCM mode is selected, this pin can be configured as a digital output with PCM signal proportional to the channel 1 sensor data. If unused, or in I2C mode, NXP recommends that this pin be unterminated. 3, 4, 5, 6 TEST Test Pin NXP recommends that these pins be unterminated. Optionally, this pin can be tied to VSS. 7, 14 VSS Supply Return This pin is the supply return node. 8 SS_B Slave select In SPI mode, this input pin provides the slave select for the SPI port. An internal pull-up device is connected to this pin. In I2C mode, this pin must be connected to VBUF with an external pull-up resistor as shown in Figure 6. 9 SCLK/SCL SPI Clock In SPI mode, this input pin provides the serial clock. An internal pull-down device is connected to this pin. In I2C mode, this input pin provides the serial clock. This pin must be connected to VBUF with an external pull-up resistor as shown in Figure 6. 10 MOSI SPI Data In In SPI mode, this pin functions as the serial data input to the SPI port. An internal pull-down device is connected to this pin. In I2C mode, NXP recommends that this pin be unterminated. Optionally, this pin can be connected to VSS. 11 MISO/SDA SPI Data Out In SPI mode, this pin functions as the serial data output. In I2C mode, this pin functions as the serial data input/output. This pin must be connected to VBUF with an external pull-up resistor as shown in Figure 6.
12 PCM0 / ARM0 Channel 0
- When the channel 0 arming output is selected, the pin can be configured as an open-drain, active low output with a pull-up current; or an open-drain, active high output with a pull-down current.
- When PCM mode is selected, this pin can be configured as a digital output with PCM signal proportional to the channel 0 sensor data. If unused, or in I2C mode, NXP recommends that this pin be unterminated. 13, 15, 16 VCC Supply This pin is connected to the supply for the device. An external capacitor must be connected between this pin and VSS as shown in Figure 5 and Figure 6. 17 PAD Die Attach Pad This pin is the die attach flag, and must be connected to VSS. See Section 16 for die attach pad connection details.
Table 9. Device pinout: SPI or I2C mode
9.3 Pinning: DSI3 or PSI5 mode
Figure 10. Device pinout: DSI3 or PSI5 mode pinout
9.4 Pin description: DSI3 or PSI5 mode
1 BUS_O Supply Out This pin is connected to the IDATA pin through an internal sense resistor
this pin can be connected to IDATA. channel FET which connects BUSRTN to the next slave in the daisy chain. necessary to connect only one pin is to the bus switch gate. If unused, or in DSI3 mode, NXP recommends that this pin be unterminated. Optionally, this pin can be tied to VSS. 7, 14 BUSRTN/VSS Supply Return This pin is the supply return node. 11 TEST_MISO SPI Data Out This pin must be left unconnected. Table 10. Device pinout: DSI3 or PSI5 mode pinout
13 VBUF Power
and VSS as shown in Figure 2, Figure 3, and Figure 4.
15 BUS_I Supply and
Figure 2, Figure 3, and Figure 4.
16 IDATA Communication
This pin modulates the response current for DSI3 and PSI5 communication. in Figure 2, Figure 3, and Figure 4. for die attach pad connection details. Table 10. Device pinout: DSI3 or PSI5 mode pinout...continued cross reference to the identifiers and descriptions found in Table 11.
- Indicates critical characteristic.
2 Parameter tested 100 % at final test during safe launch
3 Parameter verified by pass/fail testing at final test
4 Parameter verified by pass/fail testing at final test during safe launch
5 Parameter verified by qualification testing
6 Parameter verified by characterization
7 Functionality verified by modeling, simulation and/or design verification. internal system clock frequency.
9 Parameter verified by functional evaluation
documented in AN1902 with 1 signal layer and 1 ground layer.
11 Digital low-pass filter characteristics are specified independently and do not include g-
Table 11. Test notes legend
10.1 Maximum ratings
3386 BUS_I/VCC, IDATA, and BUS_O Continuous Current ISUPMAX 200 mA 6
3395 CDM (R = 0 Ω) VESD ±750 V 5
3396 Storage Tstg –55 to +150 °C 5
3397 Junction TJ –55 to +150 °C 7
3400 Thermal Resistance θJA 47 °C/W 7, 10
Table 12. Maximum ratings
10.2 Operating range - DSI / PSI5
10466 Supply Voltage (Undervoltage) V BUS_I_UV VBUS_I_UV_F — VLOW_min V 3, 6
Table 13. Operating range - DSI / PSI5
10471 Production Tested Operating Temperature Range TA –40 — +105 °C 1
10490 Guaranteed Operating Temperature Range TA –40 — +125 °C 5, 6, 7
Table 13. Operating range - DSI / PSI5...continued
10.3 Operating range - SPI / I2C
10504 Supply Voltage (Undervoltage) V
10507 Production Tested Operating Temperature Range TA –40 — +105 °C 1
10508 Guaranteed Operating Temperature Range TA –40 — +125 °C 5, 6, 7
Table 14. Operating range - SPI / I2C
10.4 Electrical characteristics - supply and I/O
10519 DSI High * IR_DSI_2 IR_DSI_1
Table 15. Electrical characteristics - supply and I/O
10525 Capacitance CVBUF 100 1000 2000 nF 7, 9
10543 ESR (including interconnect resistance) ESR 0 — 200 mΩ 7, 9
10526 VLOW Detection Threshold *VDELTA_THRESH VHIGH
10545 IRESP Detection Threshold (IBUS_O_q ≤ 24 mA) IRESP_Offset 6 12 18 mA 3, 6
10529 PSI5 Sync Pulse Pulldown Current ISYNC_PD — IR_PSI5 — mA 7
10530 Bus Switch Output High Voltage (BUSSW_L, ILoad = –100 µA) VBUSSW_L_OH VBUF
10562 Input Current High (at VIH) (SCLK/SCL, MOSI) IIH 10 20 70 µA 6
10565 Input Current Low (at VIL) (SS_B) IIL –70 –20 –10 µA 6
10563 MISO Output Leakage IMISO_Lkg –10 — 10 µA 6
Table 15. Electrical characteristics - supply and I/O...continued
10.5 Electrical characteristics - temperature sensor signal chain
10520 Temperature Measurement Range TRANGE –50 — +160 °C 7, 9
10559 Temperature Output at 25 °C T25 83 93 103 LSB 6, 7
Table 16. Electrical characteristics - temperature sensor signal chain
10558 Unsigned Temperature TRANGE 0 — 255 LSB 7, 8, 9
10556 Temperature Output Accuracy (8 bit) TACC –20 +20 °C 6, 7
10555 Standard Deviation of 50 readings, fSamp = 8 kHz TRMS ⎯ ⎯ +2 LSB 6, 7
Table 16. Electrical characteristics - temperature sensor signal chain...continued
10.6 Electrical characteristics - inertial sensor signal chain: High g
10584 High g, lateral, or Z-Axis, verified with a 50 g Range * SENSERRH –5 — +5 % 1
10626 High g (100 g Range, scales with user sensitivity scaling) * OFFHigh_1 –100 — +100 LSB 1
10583 Digital Offset After Offset Cancellation, lateral, or Z-Axis, All Ranges, 12
10635 Signed Sensor Data, 10 bit RANGESigned_10 –511 — +511 LSB 7, 8, 9
10628 Signed Sensor Data, 12 bit RANGESigned_12 –2047 — +2047 LSB 7, 8, 9
10636 Signed Error Code, 10 bit ERRSigned_10 — –512 — LSB 7, 8, 9
10637 Signed Error Code, 12 bit ERRSigned_12 — –2048 — LSB 7, 8, 9
10638 Unsigned Sensor Data, 10 bit RANGEUnsigned_10 1 — 1023 LSB 7, 8, 9
10639 Unsigned Sensor Data, 12 bit RANGEUnsigned_12 1 — 4095 LSB 7, 8, 9
10640 Unsigned Error Code, 10 bit, 12 bit ERRUnsigned — 0 — LSB 7, 8, 9
10634 Signed Sensor Data, 10 bit RANGESigned_10 –480 — +480 LSB 7, 8, 9
10645 Z-axis to X-Axis, Y-axis to X-Axis, Z-axis to Y-Axis, X-axis to Y-Axis VZX, VYX –5 — +5 % 6
10647 X-axis to Z-Axis, Y-axis to Z-Axis VXZ, VYZ –5 — +5 % 6
Table 17. Electrical characteristics - inertial sensor signal chain: High g
400 Hz, 4-Pole
Table 17. Electrical characteristics - inertial sensor signal chain: High g...continued SPI and DSI3 12-bit user gain settings. Table 18. High g adjusted offset specification limits
Table 18. High g adjusted offset specification limits...continued Table 19. PSI5, High g offset cancellation limits gain (lower range), the higher the noise, the wider the bandwidth, the higher the noise. and low-pass filter selections on the lateral, and Z-axis. Note: Peak values indicate the maximum deviation from the mean. Table 20. Lateral, High g, SPI/DSI3 12-bit noise specification
Table 20. Lateral, High g, SPI/DSI3 12-bit noise specification...continued Table 21. Z-Axis, High g, SPI/DSI3 12-bit noise specification settings and low-pass filter selections on the lateral, and Z-axis. Table 22. Lateral, High g, PSI5 10-bit noise specification Table 23. Z-Axis, High g, PSI5 10-bit noise specification
Table 23. Z-Axis, High g, PSI5 10-bit noise specification...continued
10.7 Electrical characteristics - inertial sensor signal chain: Medium g
10585 Medium g, lateral, or Z-Axis, Verified with a 15 g Range * SENSERRM –5 — +5 % 1
10627 Medium g (25 g Range, scales with user sensitivity scaling) * OFFMed_1 –100 — +100 LSB 1
Table 24. Electrical characteristics - inertial sensor signal chain: Medium g
Table 24. Electrical characteristics - inertial sensor signal chain: Medium g...continued SPI and DSI3 12-bit user gain settings. Table 25. Medium g, SPI/DSI3 12-bit offset specification
Table 25. Medium g, SPI/DSI3 12-bit offset specification...continued Table 26. Medium g, PSI5 10-bit offset specification gain (lower range), the higher the noise, the wider the bandwidth, the higher the noise. Note: Peak values indicate the maximum deviation from the mean. Table 27. Lateral, Medium g, SPI/DSI3 12-bit noise specification
Table 28. Z-axis, Medium g, SPI/DSI3 12-bit noise specification settings and low-pass filter selections. Table 29. Lateral, Medium g, PSI5 10-bit noise specifications Table 30. Z-axis, Medium g, PSI5 10-bit noise specification
10.8 Electrical characteristics - inertial sensor self-test
Table 31. Electrical characteristics - inertial sensor self-test
Table 31. Electrical characteristics - inertial sensor self-test...continued
44629 Digital Self-test 0xC, 16-bit Signed SNSDATAx Register Value DSTC0 E77F E780 E781 HEX 7
44630 Digital Self-test 0xD, 16-bit Signed SNSDATAx Register Value DSTD0 0FA3 0FA4 0FA5 HEX 7
44631 Digital Self-test 0xE, 16-bit Signed SNSDATAx Register Value DSTE0 EFA2 EFA3 EFA4 HEX 7
44632 Digital Self-test 0xF, 16-bit Signed SNSDATAx Register Value DSTF0 07B7 07B8 07B9 HEX 7
10.9 Electrical characteristics - lateral inertial sensor overload
10694 Medium g gg-cell_ClipMedX ± 500 — — g 7
10693 High g gg-cell_ClipHiX ± 2000 — — g 7
21074 Digital Clipping Limit (Medium g Lateral, must clip before transducer
21082 Digital Clipping Limit (High g Lateral, must clip before transducer and
Table 32. Electrical characteristics - lateral inertial sensor overload
10.10 Electrical characteristics - Z-axis inertial sensor overload
10698 Medium g gg-cell_ClipMedZ ± 500 — — g 7
10699 High g gg-cell_ClipHiZ ± 2000 — — g 7
21105 Digital Clipping Limit (Medium g Z-Axis, must clip before transducer
21113 Digital Clipping Limit (High g Z-Axis, must clip before transducer and
Table 33. Electrical characteristics - Z-axis inertial sensor overload
10.11 Dynamic electrical characteristics - DSI3
10723 Response Current Activation Time: Current Activated to 50 % tACT_RESP 200 — 400 ns 3, 7, 9
10731 Response Current Activation Time: Current Activated to 50 % tnACT_RESP — — 300 ns 7, 9
Table 34. Dynamic electrical characteristics - DSI3
10716 Response Chip Time tCHIP_CRM — 5 — µs 7, 8, 9
10746 Min Programmed Start Time: PDCM_RSPSTx < 0x0015 tSTART_PDCM_Min — 20 — µs 7, 8, 9
10745 Min Programmed Start Time: BDM Enabled tSTART_PDCMBDMMin — 51 — µs 7, 8, 9
10744 Max Programmed Start Time: PDCM_RSPSTx = 0x1FFF tSTART_PDCM_Max — 8191 — µs 7, 8, 9
49314 Response Chip Time tCHIP_BDM — tCHIP_PDCM — µs 7, 8, 9
10711 Time to program an OTP User Region tOTP_WRITE_MAX — — 10 ms 7, 8, 9
Table 34. Dynamic electrical characteristics - DSI3...continued
10.12 Dynamic electrical characteristics - PSI5
10748 Phase 1 tPSI5_INIT1 — 133 — ms 7, 8, 9
10758 Phase 2 (Synchronous Mode, k = 4, tS-S = 500 µs) tPSI5_INIT2_10s — 256 * tS-S — s 7, 8, 9
10757 Phase 2 (Asynchronous Mode, k = 8) tPSI5_INIT2_10a — 512 *
10756 Phase 3 (Synchronous Mode, tS-S = 500 µs) tPSI5_INIT3_10s — 2 * tS-S — s 7, 8, 9
10755 Phase 3 (Asynchronous Mode) tPSI5_INIT3_10a — 2 * tASYNC — s 7, 8, 9
10754 PSI5 Self-test Start Time tPSI5ST_START — 30 — ms 7, 8
10753 PSI5 Self-test Time, including Post OC Startup Offset tST — 223 — ms 7, 8
41756 Programming Mode Entry Window tPME — 127 — ms 7, 8, 9
10759 Reset to first sync pulse (Program Mode Entry) tRS_PM 6 — — ms 7, 8, 9
10779 Reset to first sync pulse (Normal Mode) tRS tPSI5_INIT1 — — s 7, 8, 9
10778 Sync Pulse Period tS-S 175 — — µs 7, 8, 9
10777 Sync Pulse Width tSYNC 9 — — µs 7, 8, 9
10776 Sync Pulse Reference LPF time constant tSYNC_LPF 120 280 — µs 7, 9
Table 35. Dynamic electrical characteristics - PSI5
10774 Sync Pulse Reference Discharge Activation Time tSYNC_LPF_RST — 154 — µs 7, 9
10773 Sync Pulse Detection Disable Time (PDCM_CMD_B = 0) tSYNC_OFF_500 — 450 — µs 7, 8, 9
10772 Analog Delay of Sync Pulse Detection tA_SYNC_DLY 50 — 600 ns 7, 9
10770 Sync Pulse Pulldown Function Activate Time tPD_ON — 16 — µs 7, 8
10766 Response Slew Time: 20 % to 80 % of IR_PSI5 tSLEW1_RESP 350 400 500 ns 1 ,7, 9
10764 Asynchronous Response Time tASYNC — 228 — µs 7, 8, 9
10763 Min Programmed Time Slot: PDCM_RSPSTx < 0x0014 tTIMESLOTx_MIN — 20 — µs 7, 8, 9
10790 Max Programmed Time Slot: PDCM_RSPSTx = 0x1FFF tTIMESLOTx_MAX — 8191 — µs 7, 8, 9
10789 Default Time Slot (PDCM_RSPSTx = 0x0000) tTIMESLOT_DFLT — 20 — µs 7, 8, 9
10786 Sync pulse to Daisy Chain Default Time Slot 1 (Low) tTIMESLOT_DC1_L — 192 — µs 7, 8, 9
10785 Sync pulse to Daisy Chain Default Time Slot 2 (Low) tTIMESLOT_DC2_L — 350 — µs 7, 8, 9
10784 Sync pulse to Daisy Chain Default Time Slot 1 (High) tTIMESLOT_DC1_H — 150 — µs 7, 8, 9
10783 Sync pulse to Daisy Chain Default Time Slot 2 (High) tTIMESLOT_DC2_H — 260 — µs 7, 8, 9
10782 Sync pulse to Daisy Chain Default Time Slot 3 (High) tTIMESLOT_DC3_H — 380 — µs 7, 8, 9
10761 From last bit of "SetAdr" Response to 80 % of VBUS_SW_OH tBUS_SW ⎯ ⎯ 300 µs 7
10760 The user must provide a sync pulse period within this range to
39810 The user must provide a sync pulse period within this range to
10793 Time to program one OTP User Region tOTP_WRITE_MAX — — 10 ms 7, 8, 9
Table 35. Dynamic electrical characteristics - PSI5...continued
10.13 Dynamic electrical characteristics - SPI
10794 Clock (SCLK) period (10 % of VCC to 10 % of VCC) tSCLK 88 — — ns 6
10801 Clock (SCLK) high time (90 % of VCC to 90 % of VCC) tSCLKH 30 — — ns 6
10802 Clock (SCLK) low time (10 % of VCC to 10 % of VCC) tSCLKL 30 — — ns 6
10800 Clock (SCLK) rise time (10 % of VCC to 90 % of VCC) tSCLKR — 10 25 ns 7
10803 Clock (SCLK) fall time (90 % of VCC to 10 % of VCC) tSCLKF — 10 25 ns 7
10799 SS_B asserted to SCLK high (SS_B = 10 % of VCC to SCLK = 10 % of
10798 SS_B asserted to MISO valid (SS_B = 10 % of VCC to MISO = 10/90 %
10797 Data setup time (MOSI = 10/90 % of VCC to SCLK = 10 % of VCC) tSETUP 20 — — ns 6
10796 MOSI Data hold time (SCLK = 90 % of VCC to MOSI = 10/90 % of VCC) tHOLD_IN 10 — — ns 6
10804 MISO Data hold time (SCLK = 90 % of VCC to MISO = 10/90 % of VCC) tHOLD_OUT 0 — — ns 6
10795 SCLK low to data valid (SCLK = 10 % of VCC to MISO = 10/90 % of
10807 SCLK low to SS_B high (SCLK = 10 % of VCC to SS_B = 90 % of VCC) tLAG 60 — — ns 6
10806 SS_B high to MISO disable (SS_B = 90 % of VCC to MISO = High Z) tDISABLE — — 60 ns 6
10805 Following Sensor Data Request Commands tSSN_SENSE 500 — — ns 6
10813 Following Register Reads/Writes Registers tSSN_R 500 — — ns 6
10812 Following Register Write to the UF_REGION_W Register tSSN_UF01 50 — — µs 6
10810 Time Between Sensor Data Requests (Same Channel, SPI Only, Arm
10808 SCLK low to SS_B low (SCLK = 10 % of VCC to SS_B = 90 % of VCC) tCLKSS 50 — — ns 6
Table 36. Dynamic electrical characteristics - SPI
10815 SS_B high to SCLK high (SS_B = 90 % of VCC to SCLK = 90 % of VCC) tSSCLK 50 — — ns 7
10818 SPI Data Latency tLAT_SPI — — 1 µs 7, 8
Table 36. Dynamic electrical characteristics - SPI...continued
10.14 Dynamic electrical characteristics - I2C
Table 37. Dynamic electrical characteristics - I2C
10825 Bus Capacitive Load CBUS — — 400 pF 7, 9
Table 37. Dynamic electrical characteristics - I2C...continued
10.15 Dynamic electrical characteristics - signal chain, low-pass filter
10872 SAMPLERATE = 00, 01 * tSigChain00,
10872 SAMPLERATE = 10 * tSigChain10 — 32 — µs 7, 8, 9
10871 SAMPLERATE = 11 * tSigChain11 — 64 — µs 7, 8, 9
21379 Cutoff Frequency, Filter Option #0, and #2, 4-Pole * fc0_16, fc2_16 — 400 — Hz 7, 8, 9, 11
21380 Cutoff Frequency, Filter Option #1, and #3, 3-Pole * fc1_16, fc3_16 — 400 — Hz 7, 8, 9, 11
21381 Cutoff Frequency, Filter Option #4, 3-Pole * fc4_16 — 325 — Hz 7, 8, 9, 11
21382 Cutoff Frequency, Filter Option #5, 2-Pole * fc5_16 — 370 — Hz 7, 8, 9, 11
21383 Cutoff Frequency, Filter Option #6, 2-Pole * fc6_16 — 180 — Hz 7, 8, 9, 11
21384 Cutoff Frequency, Filter Option #7, 2-Pole * fc7_16 — 100 — Hz 7, 8, 9, 11
21385 Cutoff Frequency, Filter Option #8, 4-Pole * fc8_16 — 1500 — Hz 7, 8, 9, 11
Table 38. Dynamic electrical characteristics - signal chain, low-pass filter
26413 Cutoff Frequency, Filter Option #9, 4-Pole * fc9_16 — 500 — Hz 7, 8, 9, 11
10860 Cutoff Frequency, Filter Option #10, 4-Pole * fc10_16 — 800 — Hz 7, 8, 9, 11
10870 Cutoff Frequency, Filter Option #11, 3-Pole * fc11_16 — 1200 — Hz 7, 8, 9, 11
10869 Cutoff Frequency, Filter Option #12, 3-Pole * fc12_16 — 120 — Hz 7, 8, 9, 11
10868 Cutoff Frequency, Filter Option #14, 2-Pole * fc14_16 — 120 — Hz 7, 8, 9, 11
38364 Cutoff Frequency, Filter Option #15, 2-Pole * fc15_16 — 50 — Hz 7, 8, 9, 11
38378 Cutoff Frequency, Filter Option #0, and #2, 4-Pole * fc0_32, fc2_32 — 200 — Hz 7, 8, 9, 11
38379 Cutoff Frequency, Filter Option #1, and #3, 3-Pole * fc1_32, fc3_32 — 200 — Hz 7, 8, 9, 11
38381 Cutoff Frequency, Filter Option #5, 2-Pole * fc5_32 — 185 — Hz 7, 8, 9, 11
38382 Cutoff Frequency, Filter Option #6, 2-Pole * fc6_32 — 90 — Hz 7, 8, 9, 11
38383 Cutoff Frequency, Filter Option #7, 2-Pole * fc7_32 — 50 — Hz 7, 8, 9, 11
38384 Cutoff Frequency, Filter Option #8, 4-Pole * fc8_32 — 750 — Hz 7, 8, 9, 11
38385 Cutoff Frequency, Filter Option #9, 3-Pole * fc9_32 — 250 — Hz 7, 8, 9, 11
38386 Cutoff Frequency, Filter Option #10, 4-Pole * fc10_32 — 400 — Hz 7, 8, 9, 11
38387 Cutoff Frequency, Filter Option #11, 4-Pole * fc11_32 — 600 — Hz 7, 8, 9, 11
38388 Cutoff Frequency, Filter Option #12, 3-Pole * fc12_32 — 60 — Hz 7, 8, 9, 11
38389 Cutoff Frequency, Filter Option #14, 2-Pole * fc14_32 — 60 — Hz 7, 8, 9, 11
38390 Cutoff Frequency, Filter Option #15, 4-Pole * fc15_32 — 25 — Hz 7, 8, 9, 11
38365 Cutoff Frequency, Filter Option #0, and #2, 4-Pole * fc0_64, fc2_64 — 100 — Hz 7, 8, 9, 11
38366 Cutoff Frequency, Filter Option #1, and #3, 3-Pole * fc1_64, fc3_64 — 100 — Hz 7, 8, 9, 11
38369 Cutoff Frequency, Filter Option #6, 2-Pole * fc6_64 — 45 — Hz 7, 8, 9, 11
38370 Cutoff Frequency, Filter Option #7, 2-Pole * fc7_64 — 25 — Hz 7, 8, 9, 11
38371 Cutoff Frequency, Filter Option #8, 4-Pole * fc8_64 — 375 — Hz 7, 8, 9, 11
38372 Cutoff Frequency, Filter Option #9, 3-Pole * fc9_64 — 125 — Hz 7, 8, 9, 11
38373 Cutoff Frequency, Filter Option #10, 4-Pole * fc10_64 — 200 — Hz 7, 8, 9, 11
38374 Cutoff Frequency, Filter Option #11, 4-Pole * fc11_64 — 300 — Hz 7, 8, 9, 11
38375 Cutoff Frequency, Filter Option #12, 3-Pole * fc12_64 — 30 — Hz 7, 8, 9, 11
38376 Cutoff Frequency, Filter Option #14, 2-Pole * fc14_64 — 30 — Hz 7, 8, 9, 11
Table 38. Dynamic electrical characteristics - signal chain, low-pass filter...continued
10.16 Dynamic electrical characteristics - signal chain
10863 Sample Time, Phase 0 t0CSAMP0 — 256 — µs 7, 8
10888 Sample Time, Phase 1 t0CSAMP1 — 256 — µs 7, 8
10885 Sample Time, Phase 2 t0CSAMP2 — 256 — µs 7, 8
10900 Sample Time, Phase 3 t0CSAMP3 — 256 — µs 7, 8
10897 Sample Time, Phase 4 t0CSAMP4 — 256 — µs 7, 8
10894 Sample Time, Phase 5 t0CSAMP5 — 256 — µs 7, 8
10896 Time in Phase 5 tOC5 — 1049 — ms 7, 8
39811 Sample Time, Phase 6a t0CSAMP6a — 256 — µs 7, 8
39813 Sample Time, Phase 6b t0CSAMP6b — 1024 — µs 7, 8
10882 Rate Limiting Output Update Time tRL_Rate — 2 — s 7, 8, 9
Table 39. Dynamic electrical characteristics - signal chain
10905 Count Limit OFFMONCNTLIMIT — 4096 — 1 7, 8
10904 Counter Size OFFMONCNTSIZE — 8192 — 1 7, 8
10881 Signal Delay (Sinc Filter to Output Delay, excluding LPF) tSigDelay — — 128 µs 7, 8
10877 Interpolation Latency tLAT_INTERP — tSigChainxx — s 7, 8
Table 39. Dynamic electrical characteristics - signal chain...continued
10.17 Dynamic electrical characteristics - analog self-test response time
10878 Medium g Lateral, LPF = 800 Hz, 4-Pole tST_Resp_MedX_800_4 750 795 1020 µs 7, 8
44634 Medium g Lateral, LPF = 1500 Hz, 4-Pole tST_Resp_MedX_1500_4 395 415 725 µs 7, 8
38147 Medium g Lateral, LPF = 400 Hz, 4-Pole tST_Resp_MedX_400_4 1510 1590 1810 µs 7, 8
38151 Medium g Lateral, LPF = 400 Hz, 3-Pole tST_Resp_MedX_400_3 1420 1490 1710 µs 7, 8
38150 Medium g Lateral, LPF = 180 Hz, 2-Pole tST_Resp_MedX_180_2 3030 3190 3470 µs 7, 8
38149 Medium g Lateral, LPF = 300 Hz, 4-Pole tST_Resp_MedX_300_4 2010 2120 2360 µs 7, 8
38148 Medium g Lateral, LPF = 188 Hz, 4-Pole tST_Resp_MedX_188_4 3210 3380 3680 µs 7, 8
38152 High g Lateral, LPF = 800 Hz, 4-Pole tST_Resp_HiX_800_4 750 795 892 µs 7, 8
44636 High g Lateral, LPF = 1500 Hz, 4-Pole tST_Resp_HiX_1500_4 395 415 490 µs 7, 8
38153 High g Lateral, LPF = 400 Hz, 4-Pole tST_Resp_HiX_400_4 1510 1590 1720 µs 7, 8
38154 High g Lateral, LPF = 400 Hz, 3-Pole tST_Resp_HiX_400_3 1420 1490 1620 µs 7, 8
38155 High g Lateral, LPF = 180 Hz, 2-Pole tST_Resp_HiX_180_2 3030 3190 3400 µs 7, 8
38156 High g Lateral, LPF = 300 Hz, 4-Pole tST_Resp_HiX_300_4 2010 2120 2280 µs 7, 8
Table 40. Dynamic electrical characteristics - analog self-test response time
38157 High g Lateral, LPF = 188 Hz, 4-Pole tST_Resp_HiX_188_4 3210 3380 3600 µs 7, 8
38158 Medium g Z-Axis, LPF = 800 Hz, 4-Pole tST_Resp_MedZ_800_4 750 795 1010 µs 7, 8
44637 Medium g Z-Axis, LPF = 1500 Hz, 4-Pole tST_Resp_MedZ_1500_4 395 415 710 µs 7, 8
38159 Medium g Z-Axis, LPF = 400 Hz, 4-Pole tST_Resp_MedZ_400_4 1510 1590 1810 µs 7, 8
38160 Medium g Z-Axis, LPF = 400 Hz, 3-Pole tST_Resp_MedZ_400_3 1420 1490 1700 µs 7, 8
38161 Medium g Z-Axis, LPF = 180 Hz, 2-Pole tST_Resp_MedZ_180_2 3030 3190 3470 µs 7, 8
38162 Medium g Z-Axis, LPF = 300 Hz, 4-Pole tST_Resp_MedZ_300_4 2010 2120 2360 µs 7, 8
38163 Medium g Z-Axis, LPF = 188 Hz, 4-Pole tST_Resp_MedZ_188_4 3210 3380 3680 µs 7, 8
38164 High g Z-Axis, LPF = 800 Hz, 4-Pole tST_Resp_HiZ_800_4 750 795 994 µs 7, 8
44638 High g Z-Axis, LPF = 1500 Hz, 4-Pole tST_Resp_HiZ_1500_4 395 415 675 µs 7, 8
38165 High g Z-Axis, LPF = 400 Hz, 4-Pole tST_Resp_HiZ_400_4 1510 1590 1800 µs 7, 8
38166 High g Z-Axis, LPF = 400 Hz, 3-Pole tST_Resp_HiZ_400_3 1420 1490 1690 µs 7, 8
38167 High g Z-Axis, LPF = 180 Hz, 2-Pole tST_Resp_HiZ_180_2 3030 3190 3470 µs 7, 8
38168 High g Z-Axis, LPF = 300 Hz, 4-Pole tST_Resp_HiZ_300_4 2010 2120 2360 µs 7, 8
38169 High g Z-Axis, LPF = 188 Hz, 4-Pole tST_Resp_HiZ_188_4 3210 3380 3680 µs 7, 8
Table 40. Dynamic electrical characteristics - analog self-test response time...continued
10.18 Dynamic electrical characteristics - digital self-test response time
44639 LPF ≤ 60 Hz tDST_Resp_50 — — 50 ms 7, 8
38176 Fixed Pattern Response Time: Self-test Activation/Deactivation tST_FP_Resp — — 100 µs 7, 8
Table 41. Dynamic electrical characteristics - digital self-test response time
10.19 Dynamic electrical characteristics - transducer
10917 Medium g fgcell_3dB_mid 1500 2500 4500 Hz 7
10915 High g fgcell_3dB_hi 4000 7000 13000 Hz 7
10921 Medium g fgcell_delay100_mid — — 250 µs 7
10919 High g fgcell_delay100_hi — — 250 µs 7
10923 Medium g fgcell_3dB_mid 1500 2500 4500 Hz 7
10925 High g fgcell_3dB_hi 1500 2500 7500 Hz 7
10927 Medium g fgcell_delay100_mid — — 250 µs 7
10929 High g fgcell_delay100_hi — — 250 µs 7
Table 42. Dynamic electrical characteristics - transducer
10.20 Dynamic electrical characteristics - supply and support circuitry
10930 VCC = VCCMIN to POR Release tVCC_POR — — 1 ms 7, 8, 9
10936 POR to Sensor Data Valid tPOR_DataValid — — 30 ms 7, 8, 9
10935 DSP Setting Change to Sensor Data Valid: DS3, SPI, I2C tRANGE_DataValid — — 6 ms 7, 8, 9
10934 SPI: SS_B high to Reset tSOFT_RESET_SPI — — 700 ns 7, 8
30152 I2C: Command Complete to Reset (No ACK follows) tSOFT_RESET_I2C — — 700 ns 7, 8
30151 DSI3: Command/Response Complete to Reset tSOFT_RESET_DSI — — 11 µs 7, 8
41495 PSI5: Command/Response Complete to Reset tSOFT_RESET_PSI — — 120 µs 7, 8
Table 43. Dynamic electrical characteristics - supply and support circuitry
10932 Oscillator Training Time tOscTrain — 4 — ms 7, 8
10942 Oscillator Cycles in Training Time nOSC_4ms_TYP — 40000 — 1/fOSC 7, 8
10944 Oscillator Training Window OscTrainWIN 38000 — 42000 1/fOSC 7, 8
10943 Oscillator Training Adjustment Threshold OscTrainADJ –400 — 400 1/fOSC 7, 8
10941 Oscillator Training Step Size OscTrainRES 250 1/fOSC 7, 8
10946 Quiescent Current Settling Time (Power Applied to Iq = IIDLE ± 2 mA) tSET — — 4 ms 7, 9
10931 Survival Time (BUS_I disconnect without Reset, CBUF=1 µF, Bus with 1
10952 Reset Time (BUS_I disconnect time to Reset, CBUF=1 µF, Bus with 1
10953 Survival Time (BUS_I disconnect without Reset, CBUF=470 nF, Bus with
10954 Reset Time (BUS_I disconnect time to Reset, CBUF=470 nF, Bus with 1
10947 BUS_I < VBUS_I_UV_F to IRESP Deactivation tBUS_I_POR — — 5 µs 7
10958 VBUF < VBUF_UV_F to IRESP Deactivation tVBUF_POR — — 5 µs 7
10957 Undervoltage/Overvoltage Recovery Delay tUVOV_RCV — 100 — µs 7
36822 Capacitor Test Disconnect Time tCAPTST_TIME — 1 — µs 7
Table 43. Dynamic electrical characteristics - supply and support circuitry...continued
11 Functional description
11.1 User accessible data array
11.1.1 User accessible data - general device information
Table 44. User accessible data - general device information
Table 44. User accessible data - general device information...continued
11.1.2 User accessible data - communication information
Table 45. User accessible data - communication information
Table 45. User accessible data - communication information...continued
11.1.3 User accessible data - sensor specific information
Table 46. User accessible data - sensor specific information
Table 46. User accessible data - sensor specific information...continued
11.1.4 User accessible data - sensor specific information
Table 47. User accessible data - sensor specific information
Table 47. User accessible data - sensor specific information...continued
11.1.5 User accessible data - traceability information
Table 48. User accessible data - traceability information
Table 48. User accessible data - traceability information...continued
11.2 Register definitions
11.2.1 Rolling counter register (COUNT)
count every 100 µs and the counter rolls over every 25.6 ms. Table 49. Rolling counter register (COUNT)
11.2.2 Device status registers (DEVSTATx)
Table 50. Device status registers (DEVSTATx)
11.2.2.1 Channel 0 error flag (CH0_ERR)
11.2.2.2 Channel 1 error flag (CH1_ERR)
11.2.2.3 Communication error flag (COMM_ERR)
11.2.2.4 Memory or temperature error flag (MEMTEMP_ERR)
11.2.2.5 Supply error flag (SUPPLY_ERR)
SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in Table 51.
0 No Response until the supply
the supply monitor timer expires.
1 No transmissions occur if the timer
normal transmissions resume. normal transmissions resume. Table 51. Supply error flag (SUPPLY_ERR)
11.2.2.6 Test mode (TESTMODE)
by a test mode operation or by a power cycle.
0 Test mode is not active
1 Test mode is active
Table 52. Test mode (TESTMODE)
11.2.2.7 Device reset (DEVRES)
includes the error in the status field.
0 Normal operation
1 Device reset occurred
Table 53. Device reset (DEVRES)
11.2.2.8 Device initialization (DEVINIT)
data is valid for read through one of the device communication inter-faces (tPOR_DataValid).
1 Device Initialization in Process
Table 54. Device initialization (DEVINIT)
11.2.2.9 VBUF under-voltage error (VBUFUV_ERR)
specified in Section 10.4. See Section 11.4 for details on the VBUF under-voltage monitor. SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in Section 11.2.2.5.
0 No error detected
1 VBUF Voltage Low
Table 55. VBUF under-voltage error (VBUFUV_ERR)
11.2.2.10 BUS IN under-voltage error (BUSINUV_ERR)
the SUP_ER-R_DIS bit in the DEVLOCK_WR register as shown in Section 11.2.2.5.
1 BUS_IN Voltage Low
Table 56. BUS IN under-voltage error (BUSINUV_ERR)
11.2.2.11 VBUF over-voltage error (VBUFOV_ERR)
specified in Section 10.4. See Section 11.4 for details on the VBUF over-voltage monitor. SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in Section 11.2.2.5.
1 VBUF Voltage High
Table 57. VBUF over-voltage error (VBUFOV_ERR)
11.2.2.12 Internal analog regulator voltage out of range error (INTREGA_ERR)
in the DEVSTAT1 register. If any supply error is present, the timer is reset to tUVOV_RCV. register as shown in Section 11.2.2.5.
1 Internal Analog Regulator Voltage Out of Range
Table 58. Internal analog regulator voltage out of range error (INTREGA_ERR)
11.2.2.13 Internal digital regulator voltage out of range error (INTREG_ERR)
in the DEVSTAT1 register. If any supply error is present, the timer is reset to tUVOV_RCV. register as shown in Section 11.2.2.5.
1 Internal Digital Regulator Voltage Out of Range
Table 59. Internal digital regulator voltage out of range error (INTREG_ERR)
11.2.2.14 Internal OTP regulator voltage out of range error (INTREGF_ERR)
in the DEVSTAT1 register. If any supply error is present, the timer is reset to tUVOV_RCV. register as shown in Section 11.2.2.5.
1 Internal OTP Regulator Voltage Out of Range
Table 60. Internal OTP regulator voltage out of range error (INTREGF_ERR)
11.2.2.15 Continuity monitor error (CONT_ERR)
1 Error detected in the continuity of the monitor circuit
Table 61. Continuity monitor error (CONT_ERR)
11.2.2.16 NXP OTP array error (F_OTP_ERR)
disable the automatic clearing of this error in PSI5 mode.
1 Error Detected in the Factory OTP Array
Table 62. NXP OTP array error (F_OTP_ERR)
11.2.2.17 User OTP array error (U_OTP_ERR)
automatic clearing of this error in PSI5 mode.
1 Error Detected in the User OTP Array
Table 63. User OTP array error (U_OTP_ERR)
11.2.2.18 User read/write array error (U_RW_ERR)
automatic clearing of this error in PSI5 mode.
1 Error Detected in the User Read/Write Array
Table 64. User read/write array error (U_RW_ERR)
11.2.2.19 User OTP write in process status bit (U_W_ACTIVE)
0 No OTP Write in Process
1 OTP Write in Process
Table 65. User OTP write in process status bit (U_W_ACTIVE)
11.2.2.20 Channel 1 temperature sensor error (TEMP1_ERR)
1 Over- or Under-Temperature error condition detected
Table 66. Channel 1 temperature sensor error (TEMP1_ERR)
11.2.2.21 Channel 0 temperature sensor error (TEMP0_ERR)
Table 67. Channel 0 temperature sensor error (TEMP0_ERR)
11.2.2.22 SPI MISO data mismatch error flag (MISO_ERROR)
including the error status through the SPI.
1 MISO Data Mismatch
Table 68. SPI MISO data mismatch error flag (MISO_ERROR)
11.2.2.23 Oscillator training error (OSCTRAIN_ERR)
including the error status through any communication interface. Table 69. Oscillator training error (OSCTRAIN_ERR)
11.2.3 Communication protocol revision register (COMMREV)
revision for the communication protocol used.
Table 70. Communication protocol revision register (COMMREV) with the register contents equal to 0x00.
11.2.4 Margin read status register (MREAD_STAT)
user enabled OTP margin read test. Table 71. Margin read status register (MREAD_STAT) operation. It is intended for use only after user OTP programming during manufacturing.
11.2.4.1 Margin read active status (MARGIN_RD_ACT)
0 No Margin Read Test is in Process
1 Margin Read Test is in Process
Table 72. Margin read active status (MARGIN_RD_ACT)
11.2.4.2 Margin read error status (MARGIN_RD_ERR)
The margin read error status bit is set if a user enabled OTP margin read test has failed. Section 11.2.7.1 for details regarding the user enabled OTP margin read test.
0 No Margin Read Test Failure
1 Margin Read Test Failure
Table 73. Margin read error status (MARGIN_RD_ERR)
11.2.5 Temperature register (TEMPERATURE)
the channel 0 temperature sensor. The temperature value is specified in Section 10.5. Section 10. This includes the performance of the temperature register values. Table 74. Temperature register (TEMPERATURE)
11.2.6 Device lock register (DEVLOCK_WR)
ENDINIT bit and reset control bits. Table 75. Device lock register (DEVLOCK_WR)
11.2.6.1 End initialization bit (ENDINIT)
bit can only be cleared by a device reset.
- An error detection is enabled for all user writable registers. The error detection code is continuously calculated on the user writable registers and verified against a previously calculated error detection code.
- The offset cancellation filter is forced to its final stage.
- Self-test is disabled and inhibited.
- Register Writes are inhibited with the exception of the RESET[1:0] bits in the DEVLOCK_WR register. In DSI3 mode, when the ENDINIT bit is set, the device is forced to PDCM according to the device settings and no longer responds to CRM commands. In PSI5 mode, the ENDINIT bit is automatically set when the device exits Initialization Phase 3. Product data sheet Rev. 6 — 8 February 2021
11.2.6.2 Supply error reporting disable bit (SUP_ERR_DIS)
11.2.6.3 Reset control bits (RESET[1:0])
the order shown in Table 76 or the device will reset. Table 76. Reset control bits (RESET[1:0]) write array error detection.
11.2.7 Write OTP enable register
registers. This register is included in the user read/write array error detection. Table 77. Write OTP enable register
11.2.7.1 Margin read enable bit (MARGIN_RD_EN)
programming during manufacturing.
- Read the MREAD_STAT register to confirm that the MARGIN_RD_ACT and
MARGIN_RD_ERR bits are both cleared.
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor 2. Write 0x40 to the WRITE_OTP_EN register to set the MARGIN_RD_EN bit. This initiates the OTP margin read test which completes the sequence listed in steps a through i. a. The UF2 block is read. The ECC is checked for double bit errors and the CRC is verified. If an ECC error or CRC error exists or if UF2 block is unlocked, the MARGIN_RD_ERR bit is set and the test is terminated. b. A margin read low test is run with the read threshold reduced by 25 %. The data is checked against the expected values in the mirror registers. If a double bit ECC error or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and the test is terminated. c. A margin read high test is run with the read threshold increased by 25 %. The data is checked against the expected values in the mirror registers. If a double bit error or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and the test is terminated. d. The UF0 block is read. The ECC is checked for double bit errors and the CRC is verified. If an ECC error or CRC error exists or if UF0 block is unlocked, the MARGIN_RD_ERR bit is set and the test is terminated. e. A margin read low test is run with the read threshold reduced by 25 %. The data is checked against the expected values in the mirror registers. If a double bit ECC error or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and the test is terminated. f. A margin read high test is run with the read threshold increased by 25 %. The data is checked against the expected values in the mirror registers. If a double bit error or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and the test is terminated. g. The UF1 block is read. The ECC is checked for double bit errors and the CRC is verified. If an ECC error or CRC error exists or if UF1 block is unlocked, the MARGIN_RD_ERR bit is set and the test is terminated. h. A margin read low test is run with the read threshold reduced by 25 %. The data is checked against the expected values in the mirror registers. If a double bit ECC error or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and the test is terminated. i. A margin read high test is run with the read threshold increased by 25 %. The data is checked against the expected values in the mirror registers. If a double bit error or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and the test is terminated. 3. Read the MREAD_STAT register to confirm that the MARGIN_RD_ACT bit is set and the MARGIN_RD_ERR bit is cleared. 4. Delay 1.5 ms minimum. 5. Read the MREAD_STAT register to confirm that the MARGIN_RD_ACT bit is cleared. Check the state of the MARGIN_RD_ERR bit.
- If the MARGIN_RD_ERR bit is cleared, the margin read test passed.
- If the MARGIN_RD_ERR bit is set, the margin read test failed. 6. When the test is complete, the MARGIN_RD_EN bit is cleared. 7. When the test is complete and the MREAD_STAT register has been read, the MARGIN_RD_ACT and the MARGIN_RD_ERR bit are cleared. The user enabled OTP margin read test can only be enabled when the ENDINIT bit is not set. Product data sheet Rev. 6 — 8 February 2021
11.2.7.2 Write OTP enable and programming bits
OTP are written as shown in Table 78. Table 78. Write OTP enable and programming bits be completed independently according to the procedure below. support these two user modes, the EX_PADDR bit is used as described in Table 78. appropriate CRC_xxx register is automatically set, locking the array from future writes. commands, but no new values can be written to the OTP.
- Read the appropriate CRC_UFx register and confirm the LOCK_Uxx bit is not set.
- Write the desired values to the user array registers for only the region to be written
using the procedures in Section 11.2.10.
- The user must take care to ensure that the proper data is written to each region. If a register write is executed to a new region, the base address changes to the new region. The previous data written to the register block remains in the shared registers and is written to OTP if the Write OTP sequence is completed. 3. Execute a write to the WRITE_OTP_EN register with the appropriate bits set for the desired region to program.
- Once the WRITE_OTP_EN register write is completed, a CRC is calculated for the data to be written to the region, the register values are written to OTP and the region is locked from future writes. The UOTP_WR_INIT bit remains set. 4. Delay tOTP_WRITE_MAX to allow the device to complete the writes to OTP. 5. Verify that the OTP write successfully completed by reading back all of the OTP registers using Register Read commands as defined in Section 11.2.10. 6. Repeat steps 1 through 4 for all regions to be programmed. The procedure for writing to the user OTP array UF2 region is: 1. Read the CRC_UF2 register and confirm the LOCK_UF2 bit is not set. 2. Write the desired values to the user array registers. 3. Execute a write to the WRITE_OTP_EN register with region 2 selected and the EX_COMMTYPE and EX_PADDR bit set as desired.
- Once the WRITE_OTP_EN register write is completed, a CRC is calculated for the data to be written to the region, the register values are written to OTP and the region is locked from future writes. The UOTP_WR_INIT bit remains set. 4. Delay tOTP_WRITE_MAX to allow the device to complete the writes to OTP and an automatic read of the UF2 registers from OTP. 5. Verify that the OTP write successfully completed by reading back all of the OTP registers using Register Read commands.
11.2.8 Bus switch control register (BUSSW_CTRL)
Table 79. Bus switch control register (BUSSW_CTRL) The BUSSW_CTRL bit controls the state of the BUSSW_L pin. Table 80. BUSSW_L pin state
Table 80. BUSSW_L pin state...continued cause corruption of the register write response.
11.2.9 PSI5 test register (PSI5_TEST)
The PSI5 test register is a user read/write register that contains the PSI5 test control. This register is included in the user read/write array error detection. Table 81. PSI5 test register (PSI5_TEST)
11.2.9.1 PSI5 test bit (PSI5_TEST)
- The device switches the BUS_I transceiver to PSI5 mode.
- The system holds the BUS_I node constant for 2 ms minimum to allow the BUS_I
command receiver to capture the average voltage.
- The system must transmit a sync pulse meeting the specifications in Section 10.
- The device transmits a response to the sync pulse with the following configuration:
b. The response starts in the time slot selected in the PDCM_RSPST0 register. c. The response bit time is configured in the CHIPTIME register. e. Two start bits are transmitted as specified in Section 13.3.2. f. 10-bits of data equal to 0x2AA are transmitted.
- Once the transmission is complete, the PSI5_TEST bit is cleared and the device
returns to the communication mode as defined in the COMMTYPE register. write message, regardless of whether or not the reply attempted was successful.
11.2.10 UF region selection registers (UF_REGION_x)
the status bits for the UF0 and UF1 regions to be accessed. mode, SPI mode, I2C mode or PSI5 Programming Mode. Table 82. UF region selection registers (UF_REGION_x)
- Write the desired address range to be read to the REGION_LOAD[3:0] bits in the
Table 83. Region load bits
- Delay a minimum of tSSN_UF01.
- Optional: Execute a register read of the UF_REGION_R register and confirm the
Table 84. Region active bits
- Execute a Register Read of the desired registers from the UF0, UF1, or F register
section. Complete all desired Register Reads of the selected UF Region.
- Repeat steps 1 through 4 for the next desired UF region to read.
- The user must take care to ensure that the desired registers are addressed. For example, if the REGION_LOAD bits are set to 0xA and the user executes a read of address $C2, the contents of registers $A2 are transmitted. No error detection is included other than a read of the REGION_ACTIVE bits.
- For COMMTYPE options with multiple protocol options (COMMTYPE = '000' or '001'), no error detection is included other than a read of the REGION_ACTIVE bits. The user must take care to ensure that the REGION_LOAD, bits are not inadvertently changed by an alternative protocol while executing register reads.
- In DSI3, BDM, writes to registers are inhibited. For this reason, reads of the UF0, UF1, and F registers will only be possible for the region selected by the REGION_ACTIVE bits at the time ENDINIT is set.
- In SPI and I2C mode, once the ENDINIT bit is set, writes to registers other than the RESET[1:0] bits are inhibited. For this reason, reads of the UF0, UF1, and F registers will only be possible for the region selected by the REGION_ACTIVE bits at the time ENDINIT is set.
11.2.11 Communication type register (COMMTYPE)
included in the read/write array error detection.
Table 85. Communication type register (COMMTYPE)
11.2.11.1 Communication type (COMMTYPE[2:0])
Table 86. Communication type (COMMTYPE[2:0]) communication mode register changes are handled. 2, 3, 4, 5 (SPI) Any No protocol change occurs. 6, 7 (I2C) Any No protocol change occurs. Table 87. COMMTYPEs and effect on device
- In PSI5 / SPI mode (COMMTYPE = 1), SPI transactions are ignored by the device until PSI5 initialization 3 is complete. SPI Test Mode Entry is not restricted.
- In PSI5 / SPI mode (COMMTYPE = 1), only SPI read register transactions are available.
- In DSI3 / SPI mode (COMMTYPE = 0) and PSI5 / SPI mode (COMMTYPE = 1), registers accesses by protocol are completed in the order received. Care must be taken to prevent from incorrect addressing of the F, UF0, and UF1 registers.
- In SPI only mode and in I2C only mode, the BUS_I undervoltage detection is disabled to allow for 3.3 V system operation. the VBUF undervoltage detection replaces the BUS_I undervoltage detection.
- If the COMMTYPE register is pre-programmed in OTP to a specific communication type, the user must prevent writes to this register when writing the UF2 register to OTP. If a pre-programmed COMMTYPE register is over-written and then written to OTP, the UF2 CRC verification will fail.
11.2.12 Physical address register (PHYSADDR)
is assigned either during Discovery Mode or during Command and Response Mode. Mode and uses the programmed physical address for Command and Response Mode. be reset to the OTP array value after a reset. writable, but has no impact on device operation or performance. Table 88. Physical address register (PHYSADDR)
11.2.13 Source identification registers (SOURCEID_x)
Mode. These registers are included in the read/write array error detection. Table 89. Source identification registers (SOURCEID_x)
Table 89. Source identification registers (SOURCEID_x)...continued
11.2.13.1 Data source enable bits (SIDx_EN)
described in Section 11.2.13.3.
11.2.13.2 PDCM format control bits (PDCMFORMAT[2:0])
Table 90. See Section 12.4.2 for PDCM response format details. Table 90. PDCM format control bits (PDCMFORMAT[2:0]) size applies to all modes except Programming Mode which has a fixed size of 10 bits. Table 91. PDCM format control bits
impact on device operation or performance.
11.2.13.3 Source identification (SOURCEID_x)
0 SPI Error ResponseSOURCEID_0
1 CH0_SNSDATA0
0 SPI Error ResponseSOURCEID_1
1 CH0_SNSDATA1
0 SPI Error ResponseSOURCEID_2
1 CH1_SNSDATA0
0 SPI Error ResponseSOURCEID_3
1 CH1_SNSDATA1
Table 92. SPI source identification (SOURCEID_x) associated transmission time shown in Table 93.
0 NA NASOURCEID_0
1 PDCM_RSPST0 CH0_SNSDATA0
0 NA NASOURCEID_1
1 PDCM_RSPST1 CH0_SNSDATA1
0 NA NASOURCEID_2
1 PDCM_RSPST2 CH1_SNSDATA0
0 NA NASOURCEID_3
1 PDCM_RSPST3 CH1_SNSDATA1
Table 93. DSI3 source identification (SOURCEID_x) as shown in Table 94. The SOURCEID_x bits have no effect in PSI5 mode.
0 NA NASOURCEID_
Table 94. PSI5 source identification (SOURCEID_x) for details regarding the effect of the SIDx_EN bits.
11.2.14 Communication timing register (TIMING_CFG)
register is included in the read/write array error detection. Table 95. Communication timing register (TIMING_CFG)
11.2.14.1 Periodic data collection mode period (PDCM_PER[3:0])
Table 96. Periodic data collection mode period (PDCM_PER[3:0])
Table 96. Periodic data collection mode period (PDCM_PER[3:0])...continued are met. See Section 11.5.1 for details regarding oscillator training. In PSI5 asynchronous mode, oscillator training is not applicable. In PSI5 Programming Mode, oscillator training is not applicable. In PSI5 Daisy Chain command phase, oscillator training is not applicable. are met. See Section 11.5.1 for details regarding oscillator training. are met. See Section 11.5.1 for details regarding oscillator training.
11.2.14.2 Oscillator training protocol selection bit (OSCTRAIN_SEL)
COMMTYPE values that enable multiple protocols as shown in Table 97.
0 DSI30
1 SPI
0 PSI51
Table 97. Oscillator training protocol selection bit (OSCTRAIN_SEL)
11.2.14.3 Clock calibration value reset (CK_CAL_RST)
Section 11.5.1 for details regarding oscillator training.
11.2.14.4 Command and response mode period (CRM_PER[1:0])
impact on device operation or performance. device operation or performance. Table 98. Command and response mode period (CRM_PER[1:0])
11.2.14.5 Clock calibration enable (CK_CAL_EN)
I2C communication interface. See Section 11.5.1 for details regarding oscillator training. to clearing the CK_CAL_RST bit. tolerance specified in Section 10.20. Table 99. Clock calibration enable (CK_CAL_EN)
11.2.15 Chip time and bit time register (CHIPTIME)
Table 100. Chip time and bit time register (CHIPTIME)
Table 100. Chip time and bit time register (CHIPTIME)...continued
11.2.15.1 PSI5 self-test repetition bits (ST_RPT[1:0])
for details regarding the PSI5 startup self-test. Table 101. PSI5 self-test repetition bits (ST_RPT[1:0])
11.2.15.2 PSI5 error latching enable bit (PSI5_ERRLATCH)
1 Automatic error clearing is disabled and internal errors are latched until reset as
Table 102. PSI5 error latching enable bit (PSI5_ERRLATCH)
11.2.15.3 Simultaneous sampling enable (SS_EN)
latency methods. See Section 12.4.7 for details regarding sample timing.
0 Synchronous Sampling Mode: Latency relative to transmission start time (PDCM_
1 Simultaneous Sampling Mode: Latency relative to the start of the Periodic Data
Table 103. DSI3 simultaneous sampling enable (SS_EN) latency methods to accommodate synchronized sampling or simultaneous sampling.
0 Synchronous Sampling Mode (Latency relative to Time Slot)
1 Simultaneous Sampling Mode (Latency relative to sync pulse)
Table 104. PSI5 simultaneous sampling enable (SS_EN)
0 Synchronous sampling mode: The data for all sources is latent relative to the
1 Simultaneous sampling mode: The data for all sources is latent relative to the falling
edge of slave select for the response to the Sensor Data Request for SOURCEID_0. enabled SOURCEID register address. Table 105. SPI simultaneous sampling enable (SS_EN) impact on device operation or performance.
11.2.15.4 Chip time (CHIPTIME)
Background Diagnostic Mode is always set to 5 µs with slew control enabled. Table 106. Chip time (CHIPTIME)
Table 106. Chip time (CHIPTIME)...continued on device operation or performance.
11.2.16 Timing configuration #2 register (TIMING_CFG2)
Table 107. Timing configuration #2 register (TIMING_CFG2)
11.2.16.1 PSI5 initialization phase 2 D19 and D20 change bit (PSI5_INIT2_D19)
Table 108. PSI5 initialization phase 2 D19 and D20 change bit (PSI5_INIT2_D19) writable, but has no impact on device operation or performance.
11.2.16.2 Oscillator training error counter (OSCTRAIN_ERRCNT[2:0])
Section 11.5.2 for details regarding oscillator training error detection. Table 109. Oscillator training error counter (OSCTRAIN_ERRCNT[2:0])
Table 109. Oscillator training error counter (OSCTRAIN_ERRCNT[2:0])...continued
11.2.16.3 Capacitor test disable bit (CAPTEST_OFF)
DSI3 mode as shown in Table 110.
1 Capacitor test will not run
Table 110. Capacitor test disable bit (CAPTEST_OFF) on device operation or performance. device operation or performance.
11.2.16.4 Background diagnostic mode fragment size (BDM_FRAGSIZE)
Table 111. Background diagnostic mode fragment size (BDM_FRAGSIZE) impact on device operation or performance. device operation or performance.
11.2.16.5 Background diagnostic mode enable (BDM_EN)
0 Disabled
1 Enabled
Table 112. Background diagnostic mode enable (BDM_EN) device operation or performance.
11.2.17 PSI5 configuration register (PSI5_CFG)
Table 113. PSI5 configuration register (PSI5_CFG)
11.2.17.1 Sync pulse pull-down enable bit (SYNC_PD)
regarding the sync pulse pulldown.
1 Enabled for all PSI5 operating modes
Table 114. Sync pulse pull-down enable bit (SYNC_PD) device operation or performance.
11.2.17.2 PSI5 daisy chain selection bit (DAISY_CHAIN)
0 Normal Mode (Asynchronous or Parallel,
Table 115. PSI5 daisy chain selection bit (DAISY_CHAIN) device operation or performance. on device operation or performance.
11.2.17.3 PSI5 low response current selection bit (PSI5_ILOW)
current specified in Section 10.4 as shown in Table 116.
0 Normal Response Current
1 Low Response Current
Table 116. PSI5 low response current selection bit (PSI5_ILOW) device operation or performance.
11.2.17.4 Dual transmission mode (DUALTRANS)
0 As specified in
Table 117. Dual transmission mode (DUALTRANS)
device operation or performance. on device operation or performance.
11.2.17.5 Error message information extension bit (EMSG_EXT)
PSI5 error message information as shown in Table 118.
1 Additional PSI5 reserved codes are used for internal error distinction (See
Table 118. Error message information extension bit (EMSG_EXT) device operation or performance.
11.2.17.6 PSI5 response message error detection selection bit (P_CRC)
Section 11.2.18.1 for details regarding response message error detection.
0 Parity
1 CRC
Table 119. PSI5 response message error detection selection bit (P_CRC) device operation or performance.
11.2.17.7 Initialization phase 2 data extension bit (INIT2_EXT)
0 D33 through D48 are not transmitted
Table 120. Initialization phase 2 data extension bit (INIT2_EXT)
device operation or performance.
11.2.17.8 Asynchronous mode bit (ASYNC)
described in Section 11.2.18.1 only if the DAISY_CHAIN bit is not set. device operation or performance.
11.2.18 DSI3 and PSI5 start time registers (PDCM_RSPSTx_x)
Table 121. DSI3 and PSI5 start time registers (PDCM_RSPSTx_x)
Table 121. DSI3 and PSI5 start time registers (PDCM_RSPSTx_x)...continued
11.2.18.1 Periodic data collection mode response start time (PDCM_RSPSTx[12:0])
data and SOURCEID. The value is stored in 1.0 µs increments.
0 See Table 123
Table 122. Periodic data collection mode response start time cause data contention in the system. Table 123. Synchronous mode: Source ID response start time time slots which will cause data contention.
1 SOURCEID_0 CH0_SNSDATA0 Asynchronous
Table 124. Asynchronous mode: Source ID response start time
Table 124. Asynchronous mode: Source ID response start time...continued no impact on device operation or performance.
11.2.18.2 Broadcast read command type selection bits (BRC_RSP[1:0])
Table 125. Broadcast read command type selection bits (BRC_RSP[1:0]) synchronize to alternate responses when BDM commands are received.
- If the last command prior to a BDM command is a BRC0, a device programmed to respond only to BRC0 commands will not respond to the first BDM command and will then respond to every other BDM command until the next BRC command is received.
- If the last command prior to a BDM command is a BRC0, a device programmed to respond only to BRC1 commands will respond to the first BDM command, and will then response to every other BDM command until the next BRC command is received.
- If the last command prior to a BDM command is a BRC1, a device programmed to respond only to BRC0 commands will respond to the first BDM command, and will then response to every other BDM command until the next BRC command is received.
- If the last command prior to a BDM command is a BRC1, a device programmed to respond only to BRC1 commands will not respond to the first BDM command and will then respond to every other BDM command until the next BRC command is received. In PSI5 mode, the BRC_RSP[1:0] bits are readable and writable, but have no impact on device operation or performance. In SPI and I2C mode, the BRC_RSP[1:0] bits are readable and writable, but have no impact on device operation or performance. Product data sheet Rev. 6 — 8 February 2021
11.2.19 DSI3 and PSI5 command blocking time registers (PDCM_CMD_B_x)
mode. These registers are included in the read/write array error detection. Table 126. DSI3 and PSI5 command blocking time registers (PDCM_CMD_B_x) Section 12.1.1 for details regarding the command receiver and command blocking. response transmissions are occurring to provide the most stable BUS_I voltage. Table 127. DSI3 mode: Command blocking time bits regarding the PSI5 sync pulse receiver and command blocking. Table 128. PSI5 mode: Command blocking time bits impact on device operation or performance.
11.2.20 SPI configuration control register
included in the read/write array error detection. Table 129. SPI configuration control register
11.2.20.1 SPI status reporting selection bit (SPI_STATUS)
Table 130. See Section 14.5. Table 130. SPI status reporting selection bit (SPI_STATUS)
11.2.20.2 SPI data field size bit (DATASIZE)
The SPI data field size bit controls the size of the SPI data field as shown in Table 131. Table 131. SPI data field size bit (DATASIZE)
11.2.20.3 SPI CRC length and seed bits (SPI_CRC_LEN[1:0], SPICRCSEED[3:0])
The SPI_CRC_LEN[1:0] bits select the CRC length for SPI mode as shown in Table 132. is enabled for both MISO and MOSI on the next SPI mode command. for both MISO and MOSI on the next SPI mode command. Table 132. SPI CRC length and seed bits (SPI_CRC_LEN[1:0], SPICRCSEED[3:0])
11.2.21 Who Am I register
is included in the read/write array error detection. Table 133. Who Am I register
Table 133. Who Am I register...continued register value is transmitted in response to a read command. Table 134. WHO_AM_I bits
11.2.22 I2C slave address register
included in the read/write array error detection. Table 135. I2C slave address register the actual register value is transmitted in response to a read command. Table 136. I2C_ADDRESS bits
11.2.23 Channel 0 and Channel 1 user configuration #1 registers (CH0_CFG_U1,
registers are included in the read/write array error detection.
Table 137. Channel 0 and Channel 1 user configuration #1 registers (CH0_CFG_U1, CH1_CFG_U1)
11.2.23.1 Low-pass filter and sample rate selection bits (LPF[3:0], SAMPLERATE[1:0])
Table 138. Low-pass filter and sample rate selection bits (LPF[3:0], SAMPLERATE[1:0])
11.2.23.2 User sensitivity shift selection bits (U_SNS_SHIFT[1:0])
11.2.24 Channel 0 and Channel 1 user configuration #2 registers (CH0_CFG_U2,
registers are included in the read/write array error detection. Table 139. Channel 0 and Channel 1 user configuration #2 registers (CH0_CFG_U2, CH1_CFG_U2)
11.2.24.1 User sensitivity multiplier bits (U_SNS_MULT[7:0])
Table 140. Sensitivity shift factors
Table 141. Example user shift and multiplier configuration for typical scale range
Note: Table 141 includes some typical device ranges. Other ranges are possible with the user-selected shift and multiplier values. Table 141. Example user shift and multiplier configuration for typical scale range...continued Note: Table 142 includes some typical device ranges. Other ranges are possible with the user-selected shift and multiplier values. Table 142. Example user shift and multiplier configuration for typical psi5 scale range
11.2.25 Channel 0 and Channel 1 user configuration #3 registers (CH0_CFG_U3,
registers are included in the read/write array error detection. Table 143. Channel 0 and Channel 1 user configuration #3 registers (CH0_CFG_U3, CH1_CFG_U3)
11.2.25.1 Unsigned data select bit (UNSIGNEDDATA)
sensor data transmissions as shown in Table 144. Table 144. Unsigned data select bit (UNSIGNEDDATA)
0 Signed Data Signed Data Signed Data
1 Unsigned Data Unsigned Data Unsigned Data
Table 144. Unsigned data select bit (UNSIGNEDDATA)...continued
11.2.25.2 Channel data type 0 selection bits (CHxDATATYPE0)
SNSDATA0_L and SNSDATA0_H registers for each channel. Table 145. Channel data type 0 selection bits (CHxDATATYPE0)
11.2.25.3 Channel data type 1 selection bits (CHxDATATYPE1)
SNSDATA1_L and SNSDATA1_H registers for each channel. Table 146. Channel data type 1 selection bits (CHxDATATYPE1)
Table 146. Channel data type 1 selection bits (CHxDATATYPE1)...continued
11.2.25.4 Signal chain moving average selection bits (MOVEAVG[1:0])
used for the signal chain moving average filter. Table 147. Signal chain moving average selection bits (MOVEAVG[1:0])
11.2.26 Channel 0 and Channel 1 user configuration #4 registers (CH0_CFG_U4,
registers are included in the read/write array error detection. Table 148. Channel 0 and Channel 1 user configuration #4 registers (CH0_CFG_U4, CH1_CFG_U4)
11.2.26.1 Reset offset cancellation startup bit (RESET_OC)
11.2.26.2 Signal inversion bit (INVERT)
0 As shown in
1 Inverted
Table 149. Signal inversion bit (INVERT)
11.2.26.3 Offset cancellation filter selection bits (OC_FILT[1:0])
for details regarding offset cancellation. Table 150. Offset cancellation filter selection bits (OC_FILT[1:0])
11.2.26.4 Arming pin configuration bits (ARM_CFG[2:0]) and PCM range selection bit (PCM)
Table 151. Arming pin configuration bits (ARM_CFG[2:0]) and PCM range selection bit (PCM)
Table 151. Arming pin configuration bits (ARM_CFG[2:0]) and PCM range selection bit (PCM)...continued downsampling state and all history registers. Section 11.8 for more information regarding the PCM output.
11.2.27 Channel 0 and Channel 1 user configuration #5 register (CH0_CFG_U5,
registers are included in the read/write array error detection. Table 152. Channel 0 and Channel 1 user configuration #5 register (CH0_CFG_U5, CH1_CFG_U5)
11.2.27.1 Self-test control bits (ST_CTRL[3:0])
the device as shown in Table 153. The self-test control bits are writable in DSI3 command and response mode. The self-test control bits are writable in SPI Mode. The self-test control bits are writable in I2C Mode. The self-test control bits are writable in PSI5 programming mode.
DSP write to registers inhibited. Table 153. Self-test control bits (ST_CTRL[3:0])
11.2.27.2 Offset cancellation test limit bits (OC_LIMIT[2:0])
0x0 The post PSI5 self-test offset test is disabled. Table 154. Offset cancellation test limit bits (OC_LIMIT[2:0])
11.2.27.3 DSP disable bit (DSP_DIS)
sensor data from the associated channel is not used.
0 DSP operational as specified
Table 155. DSP disable bit (DSP_DIS) Care must be taken to ensure the DSP is not disabled for sources that are enabled.
11.2.28 Channel 0 and Channel 1 arming configuration registers (CH0_ARM_CFG,
in moving average mode, or count mode. includes the downsampling state and all history registers. Table 156. Channel 0 and Channel 1 arming configuration registers (CH0_ARM_CFG, CH1_ARM_CFG)
11.2.28.1 Arming function down sampling selection bits (ARM_DS[1:0])
arming function. See Section 11.9.4.
0 0 Provide every Sensor Data Request sample to the arming function for the relevant channel. 0 1 Provide every other Sensor Data Request sample to the arming function for the relevant channel. 1 0 Provide every fourth Sensor Data Request sample to the arming function for the relevant channel. 1 1 Provide every eighth Sensor Data Request sample to the arming function for the relevant channel. Table 157. Arming function down sampling selection bits (ARM_DS[1:0])
11.2.28.2 Arming pulse stretch (ARM_PS[1:0])
The ARM_PS[1:0] bits set the programmable pulse stretch time for the arming outputs. derived from the internal oscillator, so the tolerance on this oscillator applies. Table 158. Arming pulse stretch (ARM_PS[1:0])
11.2.28.3 Arming window size (ARM_WS_N[1:0], A_WS_P[1:0])
Table 159. Positive arming window size definitions (moving average mode) Table 160. Negative arming window size definitions (moving average mode)
Table 161. Arming count limit definitions (count mode)
11.2.29 Arming threshold registers (CHx_ARM_T_P, CHx_ARM_T_N)
Table 162. Arming threshold registers (CHx_ARM_T_P, CHx_ARM_T_N) values and the corresponding threshold. Table 163. Example threshold register values and corresponding threshold
11.2.30 Offset cancellation user configuration register (OC_PHASE_CFG)
included in the read/write array error detection. Table 164. Offset cancellation user configuration register (OC_PHASE_CFG)
11.2.30.1 Channel 0 and Channel 1 offset cancellation final phase control bit (CH0_OCFINAL,
control the final offset cancellation phase for normal mode as shown in Table 165. Table 165. Channel 0 offset cancellation final phase control bit (CH0_OCFINAL, control the final offset cancellation phase for normal mode as shown in Table 166. Table 166. Channel 1 offset cancellation final phase control bit (CH0_OCFINAL,
11.2.31 User offset calibration registers (Chx_U_OFFSET_L, Chx_U_OFFSET_H)
correction value for the sensor data.
Table 167. User offset calibration registers (Chx_U_OFFSET_L, Chx_U_OFFSET_H) result in a compressed output range or a railed output.
11.2.32 Channel-specific status register (CH0_STAT, CH1_STAT)
specific status information. Table 168. Channel-specific status register (CH0_STAT, CH1_STAT)
11.2.32.1 Signal clipped status bit (SIGNALCLIP)
data transmission that includes the error in the status field. In PSI5 mode, the SIGNALCLIP bit has no impact on device operation or performance.
11.2.32.2 Offset cancellation phase status (OCPHASE[2:0])
cancellation filter as described in Section 11.6.4.6. Table 169. Offset cancellation phase status (OCPHASE[2:0])
111 Not Applicable
Table 169. Offset cancellation phase status (OCPHASE[2:0])...continued
11.2.32.3 Self-test incomplete (ST_INCMPLT)
PSI5 internal self-test procedure has started.
0 An Analog or Digital Self-test has been activated since the last reset
Table 170. Self-test incomplete (ST_INCMPLT)
11.2.32.4 Self-test active flag (ST_ACTIVE)
11.2.32.5 Offset error flag (OFFSET_ERR)
clearing of this error in PSI5 mode.
1 Offset error detected
Table 171. Offset error flag (OFFSET_ERR)
11.2.32.6 Self-test error flag (ST_ERROR)
11.2.33 Device status copy register (DEVSTAT_COPY)
details regarding the DEVSTAT register contents. This register is readable in DSI3 mode, SPI mode, I2C mode or PSI5 programming mode. Table 172. Device status copy register (DEVSTAT_COPY)
11.2.34 Sensor data #0 registers (CHx_SNSDATA0_L, CHx_SNSDATA0_H)
regarding the 16-bit sensor data. SNSDATA0_L register first, followed by the SNSDATA0_H register. Table 173. Sensor data #0 registers (CHx_SNSDATA0_L, CHx_SNSDATA0_H)
11.2.35 Sensor data #1 registers (CHx_SNSDATA1_L, CHx_SNSDATA1_H)
regarding the 16-bit sensor data. SNSDATA1_L register first, followed by the SNSDATA1_H register.
Table 174. Sensor data #1 registers (CHx_SNSDATA1_L, CHx_SNSDATA1_H)
11.2.36 Channel-specific factory configuration register (CHx_CFG_F)
the factory programmed OTP array error detection. Table 175. Channel-specific factory configuration register (CHx_CFG_F)
11.2.36.1 Range indication bits (RANGE[3:0])
Table 176. Range indication bits (RANGE[3:0])
Table 176. Range indication bits (RANGE[3:0])...continued
11.2.36.2 Axis indication bits (AXIS[1:0])
Table 177. Axis indication bits (AXIS[1:0])
11.2.37 Self-test deflection storage registers
included in the factory programmed OTP array error detection. process for these registers. Table 178. Self-test deflection storage registers
in the CHx_CFG_U5 registers as described in Section 11.2.27.1. calculating the self-test limits.
11.2.38 IC type register
Table 179. IC type register
11.2.39 IC revision register
Table 180. IC revision register
11.2.40 IC manufacturer identification register
programmed OTP array error detection. Table 181. IC manufacturer identification register
11.2.41 Part number register
programmed OTP array error detection. process for these registers. Table 182. Part number register
0 User Selectable
1 SPI32
2 DSI3
3 PSI5
4 I2C
8 User Selectable
9 SPI32
10 DSI3
11 PSI5
12 I2C
Table 183. Part number: Protocol type
0 RESERVED
1 RESERVED
2 RESERVED
3 X Y
4 X Z
5 RESERVED
6 RESERVED
7 Y Z
Table 184. Part number: Axis
2 Medium g
3 High g
Table 185. Part number: Channel 0 range Table 186. Part number: Channel 1 range
11.2.42 Device serial number registers
process for these registers.
Table 187. Device serial number registers Table 188. Example serial number decoding
11.2.43 ASIC wafer ID registers
wafer number, wafer X, and Y coordinates and the wafer lot number for the device ASIC. These registers are included in the factory programmed OTP array error detection. process for these registers. Table 189. ASIC wafer ID registers
11.2.44 Transducer wafer ID registers
process for these registers.
Table 190. Transducer wafer ID registers
11.2.45 User data registers (USERDATA_0 - USERDATA_E)
register read process for these registers. Table 191. User data registers (USERDATA_0 - USERDATA_E)
11.2.45.1 PSI5 initialization phase 2 data transmissions of user data
Table 192. PSI5 initialization phase 2 data transmissions of user data
Table 192. PSI5 initialization phase 2 data transmissions of user data...continued
11.2.46 User data registers (USERDATA_10 - USERDATA_1E)
register read process for these registers. Table 193. User data registers (USERDATA_10 - USERDATA_1E)
11.2.47 Lock and CRC registers
the lock bit, the block identifier, and the block OTP array CRC use for error detection.
Table 194. Lock and CRC registers register block before and after programming. Table 195. Lock bit, block identifier, and CRC states
11.2.48 Reserved registers
in a valid response. The data for reserved bits may be logic 0 or logic 1.
11.2.49 Invalid register addresses
Section 11.1 will result in a valid response. The data for the registers will be '0x00'. response. The data for the registers will be the current contents of the register.
11.3 OTP and read/write register array CRC verification
11.3.1 NXP OTP registers
OTP ECC as well as an independent 4-bit CRC for each 16 byte block. Table 196. Memory type code: NXP OTP register
11.3.2 User OTP only registers
(lowest address first) in the register map. Table 197. Memory type code: User OTP register
11.3.3 OTP modifiable registers
independent 4-bit CRC stored in the CRC_UF2 register. to left (MSB first) and from top to bottom (lowest address first) in the register map. Table 198. Memory type code: CRC verified OTP registers Table 199. Memory type code: ENDINIT CRC verified OTP registers
11.4 Voltage regulators
thresholds. A reference generator provides a reference voltage for the ΣΔ converter. Figure 11. Voltage regulation and monitoring
11.4.1 VBUF regulator capacitor and capacitor monitor
causing the VBUF_ERR bit to be set in the DEVSTAT1 register. diagrams in Figure 12, Figure 13, and Figure 14.
11.4.1.1 VBUF capacitance monitor timing, DSI3
Figure 12. VBUF capacitor monitor timing, DSI3
11.4.1.2 VBUF capacitance monitor timing, PSI5
Figure 13. VBUF capacitor monitor timing, PSI5 synchronous mode
11.4.1.3 VBUF capacitance monitor timing, PSI5 asynchronous mode
Figure 14. VBUF capacitor monitor timing, psi5 asynchronous mode
11.4.2 BUS_I, VBUF, VREG, VREGA, undervoltage monitor
- DSI3 – If any supply falls below the specified threshold during a command transmission in Command and Response Mode, the command is ignored, and no DSI3 response transmission occurs. Once the supply returns above the threshold, the device will resume decoding commands as specified in Section 11.2.2.5. – If any supply falls below the specified threshold during a response transmission in Command and Response Mode, the response is terminated. No attempt is made to resend the response. Once the supply returns above the threshold, the device will resume decoding commands as specified in Section 11.2.2.5. – If any supply falls below the specified threshold during a command transmission in Periodic Data Collection Mode, the command is ignored and no periodic response occurs during that period. Once the supply returns above the threshold, the device will resume periodic transmissions in response to commands as specified in Section 11.2.2.5. Any partially received Background Diagnostic Mode command is flushed and the device will begin decoding a new Background Diagnostic Mode command. – If any supply falls below the specified threshold during a periodic response transmission in Periodic Data Collection Mode, the response is terminated. No attempt is made to resend the response. Once the supply returns above the threshold, the device will resume periodic transmissions in response to commands as specified in Section 11.2.2.5. Any partially received Background Diagnostic Mode command is flushed and the device will begin decoding a new Background Diagnostic Mode command. – If any supply falls below the specified threshold during a Background Diagnostic Mode response transmission in Periodic Data Collection Mode, the response is terminated. No attempt is made to resend the response. Once the supply returns above the threshold, the device will resume periodic transmissions in response to commands as specified in Section 11.2.2.5. Any partially received Background Diagnostic Mode command is flushed and the device will begin decoding a new Background Diagnostic Mode command. Product data sheet Rev. 6 — 8 February 2021
- PSI5 – If any supply falls below the specified threshold, all PSI5 transmissions are terminated for the present sync pulse or asynchronous transmission cycle. Once the supply returns above the threshold, the device will resume responses as specified in Section 11.2.2.5.
- SPI – If any supply falls below the specified threshold, SPI responses are terminated. Once the supply returns above the threshold, the device will resume command decode and response transmissions as specified in Section 11.2.2.5.
- I2C – If any supply falls below the specified threshold, I2C transactions are terminated. Once the supply returns above the threshold, the device will resume responses as specified in Section 11.2.2.5. See Figure 15 for an example of a supply line interruption during a DSI3 or PSI5 response. aaa-030609time BUS_I BUS_I micro-cut occurs response terminated BUS_I undervoltage detected POR IBUS_I VREGA VREG VBUF
Figure 15. BUS_I micro-cut response (DSI3 or PSI5)
11.5 Internal oscillator
The device includes a factory trimmed oscillator as specified in Section 10.20.
11.5.1 Oscillator training
communication methods to reduce emissions.
11.5.1.1 DSI3 oscillator training
- The device counts the number of oscillator cycles in nCRM_PER_4ms_TYP periods
- nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training
window (OscTrainWIN) specified in Section 10.20, an oscillator adjustment is made. Otherwise, no adjustment is made. target is decreased by OscTrainRES. is increased by OscTrainRES. blocking time for the command ending the nCRM_PER_OSC calculation. untrained value with the untrained tolerance specified in Section 10.20. Figure 16. Command and response mode oscillator training timing diagram
- The device counts the number of oscillator cycles in nPDCM_PER_4ms_TYP periods
- nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training
window (OscTrainWIN) specified in Section 10.20, an oscillator adjustment is made. Otherwise, no adjustment is made. target is decreased by OscTrainRES. is increased by OscTrainRES. blocking time for the command ending the nPDCM_PER_OSC calculation. Figure 17. Periodic data collection mode oscillator training timing diagram
11.5.1.2 PSI5 oscillator training
against the values stored in the PDCM_PER[2:0] bits of the user read/write register array. calculates the number of transmission periods for every 4 ms (nPSI5_PER_4ms_TYP).
- The device counts the number of oscillator cycles in nPSI5_PER_4ms_TYP periods
- nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training
window (OscTrainWIN) specified in Section 10.20, an oscillator adjustment is made. Otherwise, no adjustment is made. target is decreased by OscTrainRES. is increased by OscTrainRES. blocking time for the command ending the nPDCM_PER_OSC calculation.
Figure 18. PSI5 oscillator training timing diagram
- In order to benefit from the PSI5 oscillator training accuracy improvements, the oscillator must be trained prior to data transmissions in Initialization phase 2. For this reason, if oscillator training is enabled in PSI5 mode, the device will not respond to sync pulses during initialization phase 1, but oscillator training will be enabled tRS_PM after reset.
11.5.1.3 SPI oscillator training
transmission periods for every 4 ms (nSPI_PER_4ms_TYP).
- The device counts the number of oscillator cycles in nSPI_PER_4ms_TYP periods
- nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training
window (OscTrainWIN) specified in Section 10.20, an oscillator adjustment is made. Otherwise, no adjustment is made. target is decreased by OscTrainRES. is increased by OscTrainRES. c. The oscillator frequency target value is changed.
11.5.1.4 I2C oscillator training
every 4 ms (nSPI_PER_4ms_TYP).
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor 1. The device counts the number of oscillator cycles in nI2C_PER_4ms_TYP periods (nOSC_4ms). 2. nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training window (OscTrainWIN) specified in Section 10.20, an oscillator adjustment is made. Otherwise, no adjustment is made. a. If nOSC_4ms is greater than nOSC_4ms_TYP + OscTrainADJ, the oscillator frequency target is decreased by OscTrainRES. b. If nOSC_4ms is less than nOSC_4ms_TYP - OscTrainADJ, the oscillator frequency target is increased by OscTrainRES. c. The oscillator frequency target value is changed.
11.5.2 Oscillator training error handling
If oscillator training is enabled by the user, but the conditions are not correct to complete oscillator training, the OSC-TRAIN_ERR bit is set in the DEVSTAT register. The following conditions will result in the OSCTRAIN_ERR bit being set.
- The CLK_CAL_EN bit in the TIMING_CFG register is set and the measured period (nOSC_4ms) for any mode is outside the Oscillator Training Window (OscTrainWIN).
- The result of the comparison is filtered with an up and down counter.
- If nOSC_4ms is outside the oscillator training window, the counter is incremented.
- If nOSC_4ms is inside the oscillator training window, the counter is decremented.
- If the counter reaches the OSCTRAIN_ERRCNT setting in the TIMING_CFG2 register, the OSCTRAIN_ERR bit is set.
- The up and down counter has a maximum value of 127 and a minimum value of 0.
- The Command and Response Mode period established by the PDCM_PER and CRM_PER settings does not fall within the 500 µs to 4 ms window.
- The Command and Response Mode period established by the PDCM_PER and CRM_PER settings is not a whole number divisor of 4 ms.
11.6 Inertial sensor signal path
11.6.1 Inertial sensor transducer
The device transducer is an overdamped mass-spring-damper system defined by the following transfer function: (2) Where: ζ = Damping Ratio ωn = Natural Frequency = 2∗Π∗ fn See Section 10.19 for transducer parameters. Product data sheet Rev. 6 — 8 February 2021
11.6.2 Inertial sensor self-test interface
described in Section 11.2.27. A diagram of the self-test interface is shown in Figure 19. Figure 19. Self-test interface selected via the ST_CTRL[3:0] bits.
11.6.2.1 Raw self-test deflection verification
raw self-test limits in Section 10.7.
11.6.2.2 Delta self-test deflection verification
Note: This value is truncated. Note: This value is rounded up.
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Where: ΔSTACC = The accuracy of the self-test deflection relative to the stored deflection as specified in Section 10.8. STDATA = The value stored in the appropriate CHx_STy_z register as defined in Section 11.2.37.
11.6.2.3 Startup digital self-test
In DSI3 mode, SPI mode or I2C mode, during device initialization (ENDINIT not set), the user can activate a digital self-test by writing to the ST_CTRL[3:0] bits in the CHx_CFG_U5 register. The digital self-test inputs a known signal stream into the front end of the DSP. After a delay defined by the low-pass filter selected, the output sensor data reaches a fixed value which can be verified by the user. The digital self-test values are listed in Section 11.2.27.1.
11.6.2.4 Fixed pattern self-test
In DSI3 mode, SPI mode or I2C mode, during device initialization (ENDINIT not set), the user can activate a fixed pattern self-test by writing to the ST_CTRL[3:0] bits in the CHx_CFG_U5 register. Fixed pattern self-tests force the DSP output to a set of known values, enabling the user to verify each bit of the sensor data. The fixed pattern self-test values are listed in Section 11.2.27.1.
11.6.2.5 PSI5 automatic startup self-test procedure
Figure 20 shows the PSI5 self-test procedure which is run automatically at startup on each channel if the device is a PSI5 device. The minimum gain settings are used for this procedure: U_SNS_SHIFT = '00', U_SNS_MULT = 0x00. Product data sheet Rev. 6 — 8 February 2021
Fixed Cap Test Pass? Self-test failed. Figure 20. PSI5 self-test procedure only be cleared by a device reset.
11.6.3 Inertial sensor ΣΔ converter
at a frequency of 1 MHz. A simplified block diagram is shown in Figure 6. Figure 21. ΣΔ converter block diagram
11.6.4 Inertial sensor digital signal processor
diagram illustrating the signal processing flow within the DSP is shown in Figure 22. Figure 22. Signal chain diagram Table 200. Signal chain diagram legend
Table 200. Signal chain diagram legend...continued
11.6.4.1 Decimation sinc filter
order Sinc Filter with a decimation ratio of 16. Figure 23. Sinc filter response 3rd order sinc filter magnitude response
11.6.4.2 Signal trim and compensation
Table 201. Signal trim and compensation variable descriptions
11.6.4.3 Digital clipping
specified in Section 10.9 and Section 10.10.
11.6.4.4 Low-pass filter
Data from the Sinc filter is processed by an infinite impulse response (IIR) low-pass filter. are selected with the LPF[3:0] bits in the CHx_CFG_U1 registers.
rate are illustrated in Figure 24 through Figure 49. Table 202. LPF #0 and LPF #2 Table 203. LPF #1 and LPF #3 Table 204. LPF #4 Table 205. LPF #5
Table 205. LPF #5...continued Table 206. LPF #6 Table 207. LPF #7 Table 208. LPF #8
Table 208. LPF #8...continued Table 209. LPF #9 Table 210. LPF #A Table 211. LPF #B
Table 211. LPF #B...continued Table 212. LPF #C Table 213. LPF #D Table 214. LPF #E
Table 214. LPF #E...continued Table 215. LPF #F Figure 24. 400 Hz, 4-pole low-pass filter response magnitude
Figure 49. 50 Hz, 4-pole low-pass filter response signal delay
11.6.4.5 User sensitivity scaling
11.6.4.6 Offset cancellation
The device provides an optional offset cancellation circuit to remove internal offset error. A simplified block diagram of the offset cancellation is shown in Figure 50. Figure 50. Offset cancellation block diagram
coefficients are specified in Table 216. low-pass filter details and timing for the startup phases is shown in Table 216. for 15 ms before continuing updates. Table 216. Offset cancellation phases and times: DSI3, SPI, and I2C modes
Table 217. Offset cancellation phases and times: PSI5 modes Figure 51. 0.04 Hz offset cancellation low–pass filter characteristics
Figure 52. 0.005 Hz offset cancellation low-pass filter characteristics
11.6.4.7 Moving average
enabled, interpolation is disabled.
11.6.4.8 Data interpolation
The device includes 16 to 1 linear data interpolation to minimize the system sample jitter. Each result produced by the digital signal processing chain is delayed one sample time. An example of the output interpolation is shown in Figure 53.
Figure 53. Output interpolation example: Linear interpolation (16 to 1)
11.6.4.9 Output scaling
Table 218 shows the output scaling for each output data type and protocol. Table 218. Output scaling
Table 219. Sensor data variables
11.7 Temperature sensor
11.7.1 Temperature sensor signal chain
parameters are specified in Section 10.5 and Section 10.18. Figure 54. Temperature sensor signal chain block diagram
11.7.2 Temperature sensor output scaling equations
Equation 15 is used to convert temperature readings with the variables as specified.
Table 220. Temperature sensor output scaling equation variables
11.8 PCM output function
if the ARM_CFG bits in the CHx_CF-G_U4 registers are configured for PCM output.
- The non-interpolated sensor data output as defined in the DATATYPE0 bits in the Chx_CFG_U3 register is saturated to 10-bits as shown in Section 11.6.4.9 and converted to an unsigned value.
- The 10-bit sensor value is input into a summer clocked at 10 MHz.
- The carry from the summer circuit is output to the PCM pin. A block diagram of the PCM output is shown in Figure 55. aaa-030638 10 bit ADDER A B CARRY SUM fCLK DSPout [20:11] as defined in DATATYPE0 PCM FF D CLK Q Q
Figure 55. PCM output function block diagram
11.9 Arming function
selected by the state of the ARM_CFG bits in the CHx_CFG_U4 registers.
11.9.1 Arming function: moving average mode
Where n is the current sample. meet the minimum time between requests (tACC_REQ_x) specified in Section 10.13. associated channel, and the pulse stretch counter is set as described in Section 11.9.5. The arming pin output is deasserted only when the pulse stretch counter expires. Figure 56 shows the arming output operation for different SPI conditions. Figure 56. Arming function block diagram - moving average mode
11.9.2 Arming function: count mode
The sample rate for each channel is determined by the SPI sensor data sample rate. minimum time between requests (tACC_REQ_x) specified in Section 10.13. counter is set as described in Section 11.9.5. The associated arm pin output is deasserted only when the pulse stretch counter expires. Figure 58 shows the arming output operation for different SPI conditions. Figure 57. Arming function block diagram - count mode Figure 58. Arming condition, moving average and count mode
11.9.3 Arming function: unfiltered mode
threshold, an arming condition is indicated. Figure 59 contains a block diagram of the Arming Function operation in Unfiltered Mode. Figure 60 shows the Arming output operation under the different SPI request conditions. Figure 59. Arming function block diagram - unfiltered mode Figure 60. Arming condition, unfiltered mode
11.9.4 Arming function down sampling
bits in the CHx_ARM_CFG registers.
the ARM_DS[1:0] bits is reached.
11.9.5 Arming pulse stretch function
evaluated sample. See Figure 58. Exception conditions listed in Section 14.5 do not impact prior arming function responses. pulse stretch counter regardless of the sensor value.
11.9.6 Arming pin output structure
active high and active low pin output structures are shown in Figure 61. Figure 61. Arming function - pin output structure
12 DSI3 protocol
describe the DSI3 Signal Function Class features supported by the device.
12.1 DSI3 physical layer
12.1.1 Command receiver
pulse train for decoding by the DSI data link layer. Figure 62. Command receiver physical layer internal signals for the logic. specified in Section 10.4 and Section 10.20. Figure 63. DSI3 command receiver timing diagram: valid command
Figure 64. DSI3 command receiver timing diagram: micro-cut
12.1.2 Response transmitter
and timing parameters are specified in Section 10.4 and Section 10.11. Figure 65. DSI3 transmitter block diagram
12.1.3 Discovery mode current sense
Figure 66. Discovery mode current sense circuit block diagram
Figure 67. DSI3 discovery mode sensing timing diagram
12.2 Address assignment
12.2.1 Address assignment method for parallel connected slaves
configuration. See Section 12.3 for details regarding Command and Response Mode.
12.2.2 Address assignment method for bus switch connected daisy chain devices
address as described in Section 12.2.1, or an un-programmed address. on the bus. See Section 12.3 for details regarding Command and Response Mode. assigned physical address for further configuration. On power up, the device bus switch output defaults to deactivated.
12.2.3 DSI3 discovery mode: Address assignment method for resistor connected
uses Discovery Mode to obtain its physical address (PADDR[3:0]).
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor The master device must initiate Discovery Mode automatically after power is applied to the bus segment by sending a sequence of Discovery Commands. Discovery mode timing is defined in Section 10.11. If the ENDINIT bit is not set and the PADDR[3:0] field is set to '0000', the device will detect a Discovery Command tSTART_DISC after a power-on reset and for intervals of tPER_Disc until Discovery Mode has ended (the maximum value of tSTART_DISC). Discovery Mode follows the sequence listed here. Figure 68 shows a timing diagram of the Discover Protocol for a 4 device segment. 1. The master powers up the bus segment to a known state. 2. The master transmits the Discovery Command. 3. After a predetermined delay (tSTART_DISC_RSP), all devices without a physical address activate a current ramp to the 2x response current at a ramp rate of iDISC_RAMP. 4. Each device monitors the current through its sense resistor (ΔiSENSE). a. If the current is above iRESP, the device disables its response current, increments its physical address counter, and waits for the next Discovery Command. b. If the current is low (ΔiSENSE less than iRESP), the device continues to ramp its response current to 2* iRESP in time tDISC_RAMP_RSP and maintains the current at 2* iRESP for time tDISC_IDLE_RSP. c. After time tDISC_IDLE_RSP, if a device has not detected a current through its current sense resistor of iRESP, the device accepts physical address '1' and disables its response current. 5. After a pre-defined period (tPER_DISC), the master transmits another Discovery Command. 6. Steps 3 and 4 are repeated, with the device accepting the address in its address assignment counter if the sense current is low. 7. The master repeats step 5 until it has transmitted Discovery Commands for all the devices it expects on the bus. 8. Device initialization can now begin using Command and Response Mode. Once the Discovery Mode is complete, a physical address is assigned to the device, and Command and Response Mode is used with the assigned physical address for further configuration. Product data sheet Rev. 6 — 8 February 2021
Figure 68. DSI3 discovery mode timing diagram
12.3 DSI3 command and response mode
initialization of the device.
12.3.1 DSI3 command and response mode command reception
read from and write to registers within the device memory structure. Figure 69. Command and response mode example command
Table 221. Command and response mode example command descriptions
12.3.1.1 Bit encoding
Figure 70. Command and response mode command bit encoding
12.3.1.2 Command message format
The command and response mode command format is shown in Table 222. Table 222. Command and response mode - command format Table 223. Command and response mode - field definitions
12.3.1.3 Error checking
command is ignored and the device does not respond.
- A seed value is preset into the least significant bits of the shift register.
- Using a serial CRC calculation method, the receiver rotates the received message
- When the calculation on the last bit of the CRC is rotated into the shift register, the
shift register contains the CRC check result.
- If the shift register contains all zeros, the CRC is correct.
- If the shift register contains a value other than zero, the CRC is incorrect.
Table 224. Command and response mode command CRC Some example CRC calculations are shown in Table 225 . Table 225. Command and response mode - CRC calculation examples
12.3.2 DSI3 command and response mode response transmission
Figure 71. Command and response mode response example Table 226. Command and response mode response example
12.3.2.1 Symbol encoding
symbol (9 chip), 12-bit data packet.
Figure 72. Response symbol encoding the two symbols that contain the same value for all three chips are also dis-carded.
1010 A 1 2 2
1011 B 2 2 1
1100 C 1 2 0
1101 D 2 0 0
1110 E 1 0 1
Table 227. Symbol mapping
1111 F 1 2 1
Table 227. Symbol mapping...continued
12.3.2.2 Response message format
The command and response mode response format is shown in Table 228. Table 228. Command and response mode - response format Table 229. Command and response mode - field definitions
12.3.2.3 Error checking
- A seed value is preset into the least significant bits of the shift register.
- Using a serial CRC calculation method, the transmitter rotates the transmitted
message into the least significant bits of the shift register, MSB first.
- Following the transmitted message, the transmitter feeds eight zeros into the shift
register, to match the length of the CRC.
- When the last zero is fed into the input adder, the shift register contains the CRC.
Table 230. Command and response mode response CRC Some example CRC calculations are shown in Table 225.
12.3.3 DSI3 command and response mode timing
parameters are specified in Section 10.11. Figure 73. Command and response mode timing diagram
12.3.4 DSI3 command and response mode command summary
Table 231. DSI3 command and response mode command summary
12.3.4.1 Register read command
physical address, including the DSI Global Device Address of '0000'. The Register Read command uses the byte address definitions shown in Section 11.1. device will respond with all zero data. Table 232. Register read command format in the PHYSADDR register. Otherwise, the command is ignored. RA[7:1] RA[7:1] contains the upper 7 bits of the byte address for the register to be read. Table 233. Register read command format description Table 234. Register read command: response format PA[3:0] DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register. Table 235. Register read command: response format description Section 11.1 will result in a valid response. The data for the registers will be '0x0000'.
12.3.4.2 Register write command
as explained in Section 12.3.4.3. The Register Write command uses the byte address definitions shown in Section 11.1. Writable registers along with their Byte addresses are shown in Section 11.1. Table 236. Register write command format in the PHYSADDR register. Otherwise, the command is ignored. RA[7:0] RA[7:0] contains the byte address of the register to be read. RD[7:0] RD[7:0] contains the data to be written to the register addressed by RA[7:0]. Table 237. Register write command format description Table 238. Register write command: response format PA[3:0] DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register. Table 239. Register write command: response format description response. The data for the registers will be the current contents of the register.
12.3.4.3 Global register write command to the PHYSADDR register
- The Register Write command is written to the PHYSADDR register.
- The PADDR[3:0] bits of the PHYSADDR register are equal to '0000' prior to the
register write being executed. Table 240. Global register write command format PA[3:0] The DSI Global address of '0000'. RA[7:0] RA[7:0] must be set to the PHYSADDR register address. RD[3:0] RD[3:0] contains the new physical address for the device. Table 241. Global register write command format description Table 242. Global register write command: response format PA[3:0] The new DSI physical address programmed to the PADDR[3:0] bits in the PHYSADDR register. RD[7:0] The data contained in the PHYSADDR register after the register write is executed. Table 243. Global register write command: response format description
12.3.4.4 Enter periodic data collection mode command
Table 247. If the PA[3:0] field in the command matches the Global address of '0000', register (this includes PADDR = 0x0). No response is transmitted for a global command. and the BDM_EN bit in the TIMING_CFG2 register as shown in Table 244.
Table 244. PDCM enable command and BDM_EN bit status Table 245. Enter periodic data collection mode command format in the PHYSADDR register or the Global Address of '0000'. Otherwise, the command is ignored. Table 246. Enter periodic data collection mode command format description Table 247. Enter periodic data collection mode command: response format PA[3:0] DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register. Table 248. Enter periodic data collection mode command: response format description
12.3.4.5 Reserved commands
transmitted. The data included in the response is undefined. Table 249. Reserved commands
Table 249. Reserved commands...continued in the PHYSADDR register. Otherwise, the command is ignored. Table 250. Reserved commands description Table 251. Reserved command response format PA[3:0] DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register. Table 252. Reserved command response format description
12.4 DSI3 periodic data collection mode and background diagnostic mode
mode is enabled and the optional background diagnostic mode is enabled.
12.4.1 DSI3 periodic data collection mode and background diagnostic mode
12.4.1.1 Bit encoding
described in Section 12.3.1.1.
12.4.1.2 Command message format
Response Mode, as described in Section 12.3.1.2. Broadcast Read Commands supported by the device. Figure 74. Background diagnostic mode command bit encoding
- Background Diagnostic Mode commands are transmitted and decoded in 2- or 4-bit fragments depending on the state of the BDM_FRAGSIZE bit in the TIMING_CFG2 register.
- The device responds with the Periodic Data Collection Mode response if and only if the command is a Broadcast Read Command or a command fragment.
- A Broadcast Read Command or any command length other than 2 or 4 bits resets the Background Diagnostic Mode command decode.
- The device responds with a Background Diagnostic Mode response only when a full 32-bit command is received and the decoded command is a valid Command and Response Mode command. See Section 12.4.4 for additional details on Background Diagnostic Mode timing.
12.4.1.3 Error checking
checking for Command and Response Mode, and described in Section 12.3.1.3. No error checking is employed for the Broadcast Read Commands.
12.4.2 DSI3 periodic data collection mode response transmission
data as shown in Figure 75 and described in the following sections.
Figure 75. Periodic data mode response transmission
12.4.2.1 Symbol encoding
for Command and Response Mode responses, and described in Section 12.3.2.1.
12.4.2.2 Response message format
Table 254. Field sizes are defined by the PDCMFORMAT[2:0] bits in the SOURCEID_x register in Section 11.2.13. Table 253. Periodic data collection mode response format
- If enabled in the PDCMFORMAT[2:0] bits, the SOURCEID field includes the value stored in the SOURCEID_x[3:0] bits of the SOURCEID_x register.
- If enabled in the PDCMFORMAT[2:0] bits, the Keep Alive Counter field is a 2-bit rolling message counter that is independently incremented for each SOURCEID. The initial value of the counter is '00'.
- If enabled, the status field is transmitted as listed in Table 254. See Section 12.7 for details on exception handling.
- The Sensor Data field includes the sensor data as selected by the DATATYPEx bits for the SOURCEID.
- The CRC field includes an 8-bit CRC as defined in Section 12.4.2.3. Sensor data field values[3:0] Description DEVSTAT state SUP_ER-R_DIS state Error priority STATUS field size = 4 STATUS field size = 0 0 0 0 0 Normal Mode N/A N/A 16 Sensor Data 0 0 0 1 Normal Mode, User Array Not Locked (UF2 region has not been locked) N/A N/A 15 Sensor Data The Sensor Data Field Error Code is transmitted for a minimum of one transmission 0 0 1 0 Self-test Incomplete or Self-test Active or Self- test Error Present Bit set in CHx_STAT: ST_INCMPLT or ST_ACTIVE or ST_ERROR N/A 14 Sensor Data The Sensor Data Field Error Code is transmitted for a minimum of one transmission
Table 254. Periodic data collection mode status field definition
0 No Response until the supply monitor timer expires
Table 254. Periodic data collection mode status field definition...continued
12.4.2.3 Error checking
CRC calculator MSB first, consistent with the transmission order of the message.
- A seed value is preset into the least significant bits of the shift register.
- Using a serial CRC calculation method, the transmitter rotates the transmitted
message into the least significant bits of the shift register, MSB first.
- Following the transmitted message, the transmitter feeds eight zeros into the shift
register, to match the length of the CRC.
- When the last zero is fed into the input adder, the shift register contains the CRC.
The CRC polynomial and seed for periodic data collection mode are shown in Table 255. Table 255. Periodic data collection mode response CRC Some example CRC calculations are shown in Table 256. Table 256. Periodic data collection mode - CRC calculation examples
Table 256. Periodic data collection mode - CRC calculation examples...continued
12.4.3 DSI3 periodic data collection mode timing
parameters are specified in Section 10.11. Figure 76. Periodic data collection mode timing diagram
12.4.4 Background diagnostic mode response transmission
12.4.4.1 Symbol encoding
12.4.4.2 Response message format
used for Command and Response Mode responses and is described in Section 12.3.2.2.
- If a complete 32-bit command is received and decoded to a valid Command and Response Mode command, the device provides a Background Diagnostic Mode response.
- Responses are initiated by the master transmitting 1-bit Broadcast Read Commands following a completed Background Diagnostic Mode command transmission.
- Responses are transmitted in one or two symbol fragments (depending on the state of the BDM_FRAGSIZE bit) following the 1-bit Broadcast Read Command, using the same timing window within the frame that the Background Diagnostic Mode Command used.
- Responses are transmitted if and only if Broadcast Read Commands are received. Product data sheet Rev. 6 — 8 February 2021
- Four or eight consecutive Broadcast Read Commands are required following a valid Background Diagnostic Mode command to complete a response transmission (depending on the state of the BDM_FRAGSIZE bit).
- If any command other than the Broadcast Read Command is received, no response is transmitted and the remainder of the Broadcast Read Command response is terminated.
- The data to be transmitted in the response is latched just before the first symbol of the background diagnostic mode response. See Figure 77 for Background Diagnostic Mode timing.
12.4.4.3 Error checking
Command and Response Mode, and described in Section 12.3.1.3.
12.4.5 DSI3 background diagnostic mode timing
Figure 77. Background diagnostic mode timing diagram
12.4.6 DSI3 periodic data collection mode and background diagnostic mode
12.4.7 DSI3 PDCM data transmission modes
12.4.7.1 Simultaneous sampling mode (SS_EN = 1)
Figure 78. Simultaneous sampling mode
12.4.7.2 Synchronous sampling mode with minimum latency (SS_EN = 0)
Figure 79. Synchronous sampling mode with minimum latency
12.5 Initialization timing
Figure 80. Initialization timing
12.6 Maximum number of devices on a network
12.6.1 Pre-configured, parallel connected network
- The capability of the master device, including, but not limited to: – The bus operating voltage – The bus supply current – The bus current limit – The bit rate – The response current detection capability (distinguishing response current from quiescent current)
- The total quiescent current of all slaves on the network.
12.6.2 Bus switch connected daisy chain network
- The capability of the master device, including, but not limited to: – The bus operating voltage – The bus supply current – The bus current limit – The bit rate – The response current detection capability (distinguishing response current from quiescent current)
- The total quiescent current of all slaves on the network.
- The current handling capability and resulting voltage drop of the external bus switches in the network.
12.6.3 Resistor connected daisy chain network using discovery mode
BUS_O pin during Discovery Mode (IBUS_O_q).
- The capability of the master device, including, but not limited to: – The bus operating voltage – The bus supply current – The bus current limit – The bit rate – The response current detection capability (distinguishing response current from quiescent current)
- The total quiescent current of all slaves on the network.
- The maximum allowed quiescent current drawn from the BUS_O pin of other slaves in the system.
- The resulting voltage drop of the Discovery Mode resistors in all slaves in the network.
12.7 DSI3 exception handling
- ST_INCMPLT set, PDCM disabled. The device must be reinitialized VBUS_I Error N/A VBUS_I < VBUS_I_UV_F • Response Current Deactivated
- BUSIN_UV_ERR set, PDCM Status set as specified in Section 12.4.2.2
- The device ignores commands in CRM
Table 257. Exception conditions and response
- VBUFUV_ERR set, PDCM Status set as specified in Section 12.4.2.2
- The device ignores commands in CRM Internal Regulator Error N/A Internal regulator under- voltage condition
- The device is held in Reset
- No response to DSI commands
- If activated, BUSSW_L is deactivated
- The device must be reinitialized when the internal regulator returns above the threshold OTP Error Detection Fault (Factory Array) N/A Error detected in factory programmed OTP array.
- Periodic Data Collection Mode response data set to error response
- F_OTP_ERR set, PDCM Status set as specified in Section 12.4.2.2 OTP Error Detection Fault (User Array) N/A Error detected in User programmed OTP array and the LOCK_U bit is set.
- Periodic Data Collection Mode response data set to error response
- U_OTP_ERR set, PDCM Status set as specified in Section 12.4.2.2 No N/A N/AUser R/W Array Error Detection Fault Yes Error detected in user read write registers and the ENDINIT bit is set.
- Periodic Data Collection Mode response data set to error response
- U_RW_ERR set, PDCM Status set as specified in Section 12.4.2.2 No ST activated during initialization
- Internal self-test circuitry enabled
- Self-test Activation Incomplete status cleared
- Sensor Data Registers (SNSDATAx_x) contain self-test active data
- ST_ACTIVE set Self-test Activated Yes ST activated in Periodic Data Collection Mode
- Periodic Data Collection Mode sensor response data normal
- Self-test Activation ignored No In initialization, before Self- test
- Normal Responses to Command and Response ModeSelf-test Never Activated after Reset Yes In PDCM, Self-test incomplete
- Periodic Data Collection Mode sensor response data normal
- ST_INCMPLT set, PDCM Status set as specified in Section 12.4.2.2
Table 257. Exception conditions and response...continued
12.7.1 Daisy chain and discovery mode error handling
Discovery Mode as programmed. in Daisy Chain as programmed. in Discovery Mode as programmed. in Daisy Chain as programmed. Discovery Mode as programmed. Not Applicable. Not Applicable. Discovery Mode as programmed. Table 258. DSI3 error handling - discovery mode and daisy chain mode
13 PSI5 protocol
13.1 Communication interface overview
configuration for multiple satellite modules in parallel. Figure 81. PSI5 satellite interface diagram
13.2 Data transmission physical layer
transmission (IDATA). The PSI5 master sup-plies a pre-regulated voltage to this device.
13.2.1 Synchronization pulse
Figure 82. Synchronous communication overview
13.2.1.1 Synchronization pulse detection
supply voltage. Figure 83 shows a block diagram of the Sync pulse detection circuit. Figure 83. Synchronization pulse detection circuit
minimum value of tSYNC). If the counter is above the limit, a valid sync pulse is detected.
- The valid Sync pulse detection signal is set.
- The detection counter is reset and disabled for tSYNC_OFF (referenced from tTRIG).
specifications for each option.
- The Sync pulse detection low-pass filter is reset for a specified time (tSYNC_LPF_RESET).
Figure 84. Synchronization pulse detection timing
Figure 85. Sync pulse characteristics
13.2.1.2 Synchronization pulse pulldown function
Phase 1, and in Daisy Chain Mode until the Run Command is received.
13.3 Data transmission data link layer
13.3.1 Bit encoding
The device outputs data by modulation of the VCC current using Manchester Encoding. data are transmitted, a transition occurs at the start of a bit time. Figure 86. Manchester data bit encoding
13.3.2 PSI5 data transmission
Manchester-encoded transmission frame is illustrated in Figure 87.
Figure 87. Example Manchester encoded data transfer - PSI5-x10x
13.3.2.1 PSI5-x10P transmission mode
Table 259. PSI5-x10P transmission mode
13.3.2.2 PSI5-x10C transmission mode
Table 260. PSI5-x10C transmission mode
13.3.2.3 PSI5-x16P transmission mode
the data packet and the lower 6-bits are all zeros. Table 261. PSI5-x16P transmission mode
13.3.2.4 PSI5-x16C transmission mode
the data packet and the lower 6-bits are all zeros. Table 262. PSI5-x16C transmission mode
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Start bits Sensor data (See Section 11.6.4.9) CRC Init Data 0 0 0 0 0 0 10-bit Initialization Data as specified in Section 13.4.2.1 C2 C1 C0 Table 262. PSI5-x16C transmission mode...continued
13.3.3 Error detection
13.3.3.1 Parity error detection
bits in the transmitted message must be an even number. Table 263. PSI5 3-bit CRC calculation examples
13.3.4 PSI5 data field and data range values
the PDCMFORMAT bits in the SOURCEID_x registers as described in Section 11.2.13.2. (EMSG_EXT = 1 in PSI5_CFG) (EMSG_EXT = 0 in PSI5_CFG) +32704 7FC0 +511 1FF +32640 7F80 +510 1FE Reserved Reserved Table 264. PSI5 data values
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor 16-bit data values 10-bit data value Dec Hex Dec Binary Hex (EMSG_EXT = 1 in PSI5_CFG) (EMSG_EXT = 0 in PSI5_CFG) +32576 7F40 +509 1FD +32512 7F00 +508 1FC +32448 7EC0 +507 1FB +32384 7E80 +506 1FA +32320 7E40 +505 1F9 +32256 7E00 +504 1F8 +32192 7DC0 +503 1F7 +32128 7D80 +502 1F6 +32064 7D40 +501 1F5 +32000 7D00 +500 1F4 Reserved Sensor Defect Error +31936 7CC0 +499 1F3 +31872 7C80 +498 1F2 +31808 7C40 +497 1F1 +31744 7C00 +496 1F0 Reserved Reserved +31680 7BC0 +495 1EF Communication Error (OSCTRAIN_ERR bit) +31616 7B80 +494 1EE Test Mode Enabled (TESTMODE bit set) +31552 7B40 +493 1ED Offset Error (CH0 or CH1 OFFSET_ ERR bit set) +31488 7B00 +492 1EC Temperature Error (TEMP0_ERR or TEMP1_ERR bit set) +31424 7AC0 +491 1EB Memory Error (F_OTP_ERR, U_OTP_ ERR or U_RW_ERR set) Reserved (Error Mapped to 0x1F4) +31360 7A80 +490 1EA Sensor Self-test Error (CH0 or CH1 ST_ ERROR bit set) Sensor Self-test Error +31296 7A40 +489 1E9 Reserved Reserved +31232 7A00 +488 1E8 Sensor Busy Sensor Busy +31168 79C0 +487 1E7 Sensor Ready Sensor Ready +31104 7980 +486 1E6 Sensor Ready, but Unlocked Sensor Ready, but Unlocked +31040 7940 +485 1E5 +30976 7900 +484 1E4 +30912 78C0 +483 1E3 Reserved Reserved NA NA +482 1E2 Bidirectional Communication: RC "Error" Bidirectional Communication: RC "Error" Table 264. PSI5 data values...continued
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor 16-bit data values 10-bit data value Dec Hex Dec Binary Hex (EMSG_EXT = 1 in PSI5_CFG) (EMSG_EXT = 0 in PSI5_CFG) NA NA +481 1E1 Bidirectional Communication: RC "OK" Bidirectional Communication: RC "OK" +30720 7800 +480 1E0 Maximum positive sensor value Maximum positive sensor value +129 to +192 0081 to 00C0 +3 003 +65 to +128 0041 to 0080 +2 002 +1 to +64 0001 to 0040 +1 001 Positive sensor values Positive sensor values 0 0000 0 000 Zero Zero –1 to –64 FFFF to FFC0 –1 3FF –65 to –128 FFBF to FF80 –2 3FE –129 to –192 FF7F to FF40 –3 3FD Negative sensor values Negative sensor values –30720 8800 –480 220 Maximum negative sensor value Maximum negative sensor value –30784 87C0 –481 1000011111 21F –31744 8400 –496 1000010000 210 Initialization Data Codes 10-bit Status Data Nibble 1 - 16 (0000 - 1111) (Dx) –31808 83C0 –497 1000001111 20F –32767 8000 –512 1000000000 200 Initialization Data IDs Block ID 1 - 16 (10-bit Mode) (IDx)
13.4 Initialization
- Initialization Phase 1: No Data transmissions occur
- Initialization Phase 2: Sensor self-test and transmission of configuration information
- Initialization Phase 3: Transmission of the "Sensor Busy" and / or "Sensor Ready" / "Sensor Defect" messages Product data sheet Rev. 6 — 8 February 2021
Figure 89. PSI5 initialization timing, synchronous mode Figure 90. PSI5 initialization timing, asynchronous mode
13.4.1 PSI5 initialization phase 1
- Internal delay to ensure analog circuitry has stabilized (tPOR_PSI5)
- Offset cancellation low-pass filter initialization begins (tPSI5ST_START)
- Monitor for the Programming Mode Entry Sequence (tPME)
- If the Programming Mode Entry Sequence is not detected, the device enters
13.4.2 PSI5 initialization phase 2
Table 265. PSI5 initialization phase 2 data transmission order The Initialization phase 2 time is calculated using Equation 17.
13.4.2.1 PSI5 initialization phase 2 data transmissions
channel. The data content and transmission format is shown in Table 267 and Table 268. using the equation in Section 13.4.2. Table 266. Initialization phase 2 time
1111 USERDATA_7[7:4] User Specific Data User
0001 USERDATA_8[7:4] User Specific Data User
Table 267. Channel 0 PSI5 initialization phase 2 data
1111 CH1_STOFFSET_N[3:0] Channel 1 Post Negative Self-test Offset, Low
Table 267. Channel 0 PSI5 initialization phase 2 data...continued
1010 USERDATA_C[7:4] User Specific Data User
Table 268. Channel 1 PSI5 Initialization Phase 2 Data
1111 USERDATA_E[7:4] User Specific Data User
Table 268. Channel 1 PSI5 Initialization Phase 2 Data...continued transmitted. This can only occur if the internal self-test sequence passes the first time. channel, the latest self-test, and offset values are transmitted.
transmitted, F10, D33 - D48 will include self-test data from the last failed attempt.
13.4.3 Internal self-test
13.4.4 Initialization phase 3
Table 264. The number of "Sensor Busy" messages transmitted in initialization phase 3 varies depending on the mode of operation, and the number of self-test repetitions. Once internal self-test is completed, the device transmits 2 "Sensor Ready" commands. passed on both channels or the total number of repeats have completed. The ENDINIT bit is automatically set when the device exits Initialization Phase 3.
13.5 Normal mode
13.5.1 Asynchronous mode
13.5.2 Simultaneous sampling mode
programming the SS_EN bit to "Simultaneous Sampling Mode". programmed in the PDCM_RSPSTx registers, relative to tTRIG.
Figure 91. Simultaneous sampling mode
13.5.3 Synchronous sampling mode with minimum latency
minimum latency by programming the SS_EN bit to "Synchronous Sampling Mode". PDCM_RSPSTx registers, relative to tTRIG. Figure 92. Synchronous sampling mode with minimum latency
13.6 PSI5 default mode (un-programmed PSI5 device)
Un-programmed FXLS93xxx PSI5 devices include a default PSI5 transmission mode. mode with the minimum user gain and the default 400 Hz, 4-Pole low-pass filter.
Figure 93. PSI5 default mode transmission Table 269. Default PSI5-P16C transmission mode Table 270. Default PSI5-P16C transmission mode timing parameters Table 271. Default PSI5-P16C transmission mode, High g sensor data configuration
Table 272. Default PSI5-P16C transmission mode, Medium g sensor data configuration
13.7 Dual transmission mode
transmitted as shown in Table 273 through Table 276. Table 273. Dual transmission mode 10-bit transmission data with parity Table 274. Dual transmission mode 10-bit transmission data with CRC Table 275. Dual transmission mode 16-bit transmission data with parity
Table 275. Dual transmission mode 16-bit transmission data with parity...continued Table 276. Dual transmission mode 16-bit transmission data with CRC
13.8 Daisy chain mode
relative to tTRIG (rising edge of Sync pulse).
- After a power on delay of tRS_PM, the device waits for a PSI5 "Set Address" command
defined in Table 278 and Table 279. consecutive sync pulses or 5 consecutive missing sync pulses. defined in Table 292, with the exception of the time slot. uses the Source ID 0, address-based time slot specified in Table 280.
- After receiving a valid address and completing the response, the device will decode
responses are transmitted in the address-based time slot specified in Table 280.
- When the "Run Mode" command is received, the device responds to the command
Table 277. Daisy chain: Run mode configuration
- Upon completion of Initialization Phase 3, the ENDINIT bit is set, the device enters normal mode and responds to all sync pulses with sensor data according to Table 278,Table 279, and Table 280. SAdr FC Response (OK)CMD type A2 A1 A0 F2 F1 F0 Command RC RD1 Short 0 0 0 A2 A1 A0 Set Sensor Address (Daisy Chain) OK SAdr Short 1 1 1 0 0 0 Broadcast Message - "Run Mode" OK 0x000 Short SAdr = 1, 2, 3, 4, 5, 6 0 0 0 Activate Low Side Bus Switch OK 0x000 Short SAdr = 1, 2, 3, 4, 5, 6 1 1 1 Deactivate Low Side Bus Switch OK 0x111 Short SAdr = 1, 2, 3, 4, 5, 6 A2 A1 A0 Set Sensor Address (Daisy Chain) OK SAdr
Table 278. Daisy chain programming commands and responses Table 279. Daisy chain programming response code definitions
Table 279. Daisy chain programming response code definitions...continued Table 280. Valid daisy chain addresses Note: Writes to Sensor Address 7 are ignored. address, daisy chain mode is disabled.
13.9 Error handling
13.9.1 Daisy chain error handling
Supply Error Daisy chain commands ignored. The device will not participate in daisy chain. Communication Error No effect. The device will participate in Daisy Chain as programmed. Test Mode Enabled Daisy chain commands ignored. The device will not participate in daisy chain. Offset Error No effect. The device will participate in daisy chain as programmed. Temperature Error No effect. The device will participate in daisy chain as programmed. Memory Error No effect. The device will participate in daisy chain as programmed. Self-test Error No effect. The device will participate in daisy chain as programmed. Device Not Locked No effect. The device will participate in daisy chain as programmed. Table 281. Daisy chain error handling
13.9.2 Initialization phase 2 error handling
initialization phase 2 as necessary and then transition to initialization phase 3. Temperature Error No Effect. The device will attempt to transmit Initialization Phase 2 data. Memory Error No Effect. The device will attempt to transmit Initialization Phase 2 data. Table 282. Initialization phase 2 error handling
13.9.3 Initialization phase 3 error handling
more Sensor Ready commands are transmitted before entering Run Mode. Temperature Error No Effect. The device will attempt to transmit Initialization Phase 3 data. Memory Error No Effect. The device will attempt to transmit Initialization Phase 3 data. Table 283. Initialization phase 3 error handling
13.9.4 Normal mode error handling with internal error automatic clearing
allowing for temporary error conditions to be cleared once the error condition is removed.
13.9.4.1 Standard error reporting
Table 284. Standard error reporting [1] An offset error on either channel results in an offset error response from both channels. [2] A self-test error on either channel results in a self-test error response from both channels.
13.9.4.2 PSI5 error extension option
Table 285. PSI5 error extension option [1] An offset error on either channel results in an offset error response from both channels. [2] A self-test error on either channel results in a self-test error response from both channels.
13.9.5 Normal mode error handling with internal error latching
PSI5_ERRLATCH bit is set. Internal errors are latched until reset.
13.9.5.1 Standard error reporting
Table 286. Standard error reporting
Table 286. Standard error reporting...continued [1] An offset error on either channel results in an offset error response from both channels. [2] A self-test error on either channel results in a self-test error response from both channels.
13.9.5.2 PSI5 error extension option
Table 287. PSI5 error extension option [1] An offset error on either channel results in an offset error response from both channels. [2] A self-test error on either channel results in a self-test error response from both channels.
13.10 PSI5 programming mode
for use in normal operation.
13.10.1 PSI5 programming mode entry
- At least 31 sync pulses are detected, directly preceding the Programming Mode Entry
Short Command during the Programming Mode Entry Window shown in Figure 89.
- The window timing is defined in Section 10.12 (tPME).
- The Sync pulses and Programming Mode Entry command must be received with a sync pulse period of tS-S_PM If the Programming Mode entry requirement is not met: Product data sheet Rev. 6 — 8 February 2021
- Programming Mode Entry is blocked until the device is reset.
- The device proceeds with PSI5 Initialization Phase 2, and PSI5 Initialization Phase 3.
- The device enters normal mode, and responds as programmed to normal sync
- Normal transmissions to sync pulses are terminated.
- The device will detect commands if the start condition is met as described in
- The device responds only to valid PSI5 Short and XLong Commands addressed to
Sensor Address '001', as defined in Section 13.10.3.
13.10.2 PSI5 programming mode - data link layer
13.10.2.1 PSI5 programming mode - command bit encoding
pulses are expected at a rate of tS-S_PM.
13.10.2.2 PSI5 programming mode - command message format
- A minimum of 5 consecutive logic '0's (with no sync bits)
- A minimum of 31 consecutive logic '1's (this includes logic '1's transmitted for the
The command message format is shown in Table 289. Table 288. Programming mode via PSI5 command data format Table 289. Programming mode via PSI5 command data format - response message to ensure that there will never be more than 3 logic '0' bits in a row.
Table 290. Programming mode via PSI5 XLONG command data format with sync bits Table 291. Programming mode via PSI5 XLONG command data format with sync bits - response is no delay restriction between the command and the first sync pulse for the response. S_PM) or a framing error may occur. Table 292. Programming mode via PSI5 response message settings
13.10.2.3 Short frame command and response format
and responses are defined in Section 13.10.3. The device only supports a short command for programming mode entry. Table 293. Programming mode via PSI5 short command Table 294. Response format
13.10.2.4 Long frame command and response format
shown in Table 295. The device does not support the long frame command. Table 295. Programming mode via PSI5 long command Table 296. Response format
13.10.2.5 Extra long frame command and response format
and writes. The device can provide register data in response to a read or write request. responses are defined in Section 13.10.3. The device supports register read and register write extra long commands. Table 297. Programming mode via PSI5 long command Table 298. Response format
13.10.2.6 Command message CRC
example CRC calculation values for 10-bit data transmissions.
13.10.2.7 Command sync pulse blanking time
13.10.2.8 Command timeout
with a Short Frame Framing Error response as defined in Section 13.10.4.
13.10.3 PSI5 programming mode command and response summary
001 Write WData to register RA7:RA0 Varies Varies OK WData RA7:RA0 Error ErrN 0x000
Table 299. Programming mode via PSI5 commands and responses Table 300. Programming mode via PSI5 response code definitions
13.10.4 Programming mode via PSI5 error response summary
0000 General General Error No
0001 Framing Framing Error (4 consecutive zeros) Yes
0010 CRC CRC Error on Received Message Yes
0011 Address Sensor Address Not Supported No (Invalid Address is ignored)
0100 FC Function Code Not Supported No (N/A)
Table 301. Error response summary
Table 301. Error response summary...continued
13.11 PSI5 OTP programming procedure
- Load desired data into the desired registers using PSI5 Write commands.
- Write the necessary OTP program sequence to the WRITE_OTP_EN register for the
desired OTP region to be written.
- Delay tPROG_TIME after the completion of the Write OTP program to allow for
completion of the OTP writes.
- Read the DEVSTAT and DEVSTAT2 registers to confirm that no errors occurred
- Read back the register values that were written and compare to the desired values to
confirm successful OTP writes.
14 Standard 32-bit SPI protocol
Figure 94. Standard 32-bit SPI protocol timing diagram
14.1 SPI command format
Table 302. SPI command format
14.2 SPI response format
Table 303. SPI response format
Table 303. SPI response format...continued
14.3 Command summary
Table 304. Command summary
14.3.1 Register read command
- No SPI Error is detected (See Section 14.5.6)
- No MISO Error is detected (See Section 14.5.7) If the conditions are met, the device responds to the register read request as shown in Section 14.3.1.2. Otherwise, the device responds with the Error Response as defined in Product data sheet Rev. 6 — 8 February 2021
edge of SS_B for the Register Read command.
14.3.1.1 Register read command message format
Table 305. Register read command message format RA[7:1] RA[7:1] contains the word address of the register to be read. Table 306. Register read command message format description
14.3.1.2 Register read response message format
Table 307. Register read response message format Table 308. Register read response message format description
14.3.2 Register write command
and the contents of RA[7:1] low byte (RA[0] = 0) in the lower byte.
- No SPI Error is detected (See Section 14.5.6) Product data sheet Rev. 6 — 8 February 2021
- The ENDINIT bit is cleared – This applies to all registers with the exception of the RESET[1:0] bits in the DEVLOCK_WR register If the conditions are met, the register write is executed and the device responds to the register write request as shown in Section 14.3.2.2. Otherwise, no register is written and the device responds with the Error Response as defined in Section 14.2. The register is not written until the transfer during which the register write was requested has been completed. A register write command to a read-only register will not execute, but will result in a valid response.
14.3.2.1 Register write command message format
Table 309. Register write command message format RA[7:0] RA[7:1] contains the byte address of the register to be written. Table 310. Register write command message format description
14.3.2.2 Register write response message format
Table 311. Register write response message format Table 312. Register write response message format description
14.3.3 Sensor data request commands
14.3.3.1 Sensor data request command message format
Table 313. Sensor data request command message format C[3:1] = SOURCEID[2:0] Source Identification code for the requested sensor data. See Section 11.2.13. Table 314. Sensor data request command message format description
14.3.3.2 Sensor data request response message format
1 C[3] C[2] C[1] ST[1:0] SD[11:0] Optional SD
Table 315. Sensor data request response message format C[3:1] = SOURCEID[2:0] Source Identification code for the requested sensor data. See Section 11.2.13. Table 316. Sensor data request response message format description
14.3.4 Reserved commands
error handling conditions specified in Section 14.5.
14.3.4.1 Reserved command message format
14.3.4.2 Reserved command response message format
Table 317. Reserved command response message format Table 318. Reserved command response message format description
14.4 Error checking
14.4.1 Default 8-bit CRC
14.4.1.1 Command error checking
command is ignored and the device responds with the SPI Error response.
- A seed value is preset into the least significant bits of the shift register.
- Using a serial CRC calculation method, the receiver rotates the received message
- When the calculation on the last bit of the CRC is rotated into the shift register, the
shift register contains the CRC check result.
- If the shift register contains all zeros, the CRC is correct.
- If the shift register contains a value other than zero, the CRC is incorrect.
The CRC polynomial and seed are shown in Table 319. Table 319. SPI command message CRC Some example CRC calculations are shown in Table 321.
14.4.1.2 Response error checking
- A seed value is preset into the least significant bits of the shift register.
- Using a serial CRC calculation method, the transmitter rotates the transmitted
message into the least significant bits of the shift register, MSB first.
- Following the transmitted message, the transmitter feeds eight zeros into the shift
register, to match the length of the CRC.
- When the last zero is fed into the input adder, the shift register contains the CRC.
The CRC polynomial and seed are shown in Table 320. Table 320. SPI CRC polynomial and seed Some example CRC calculations are shown in Table 321. Table 321. SPI 8-bit CRC calculation examples
14.4.2 Selectable 4-bit CRC
programming the SPI_CFG register as described in Section 11.2.20.
14.4.2.1 SPI command format with 4-bit CRC
Table 322. SPI command format with 4-bit CRC
14.4.2.2 SPI response format with 4-bit CRC
Table 323. SPI response format with 4-bit CRC
14.4.2.3 Command error checking with 4-bit CRC
ignored and the device responds with the SPI Error response.
- A seed value determined by the SPICRCSEED[3:0] value in the SPI_CFG register is
preset into the least significant bits of the shift register.
- Using a serial CRC calculation method, the receiver rotates the received message
- When the calculation on the last bit of the CRC is rotated into the shift register, the
shift register contains the CRC check result.
- If the shift register contains all zeros, the CRC is correct.
- If the shift register contains a value other than zero, the CRC is incorrect.
The CRC polynomial and seed are shown in Table 324. Table 324. SPI command message CRC, 4 bit
14.4.2.4 Response error checking with 4-bit CRC
- A seed value determined by the SPICRCSEED[3:0] value is preset into the least
significant bits of the shift register.
- Using a serial CRC calculation method, the transmitter rotates the transmitted
message into the least significant bits of the shift register, MSB first.
- Following the transmitted message, the transmitter feeds four zeros into the shift
register, to match the length of the CRC.
- When the last zero is fed into the input adder, the shift register contains the CRC.
The CRC polynomial and seed are shown in Table 325. Table 325. SPI response message CRC, 4-bit
14.4.2.5 Message counter (KAC) with 4-bit CRC
14.4.2.6 Example 4-bit CRC calculations
Some example CRC calculations for 32-bit SPI commands are shown in Table 326.
Table 326. SPI 4-bit CRC calculation examples
14.4.3 Selectable 3-bit CRC
programming the SPI_CFG register as described in Section 11.2.20.
14.4.3.1 SPI command format with 3-bit CRC
Table 327. SPI command format with 3-bit CRC
14.4.3.2 SPI response format with 3-bit CRC
Table 328. SPI response format with 3-bit CRC
Table 328. SPI response format with 3-bit CRC...continued
14.4.3.3 Command error checking with 3-bit CRC
ignored and the device responds with the SPI Error response.
- A seed value determined by the SPICRCSEED[2:0] value in the SPI_CFG register is
preset into the least significant bits of the shift register.
- Using a serial CRC calculation method, the receiver rotates the received message
- When the calculation on the last bit of the CRC is rotated into the shift register, the
shift register contains the CRC check result.
- If the shift register contains all zeros, the CRC is correct.
- If the shift register contains a value other than zero, the CRC is incorrect.
The CRC polynomial and seed are shown in Table 329. Table 329. SPI command message CRC, 3 bit Some example CRC calculations are shown in Table 263.
14.4.3.4 Response error checking with 3-bit CRC
- A seed value determined by the SPICRCSEED[2:0] value is preset into the least
significant bits of the shift register.
- Using a serial CRC calculation method, the transmitter rotates the transmitted
message into the least significant bits of the shift register, MSB first.
- Following the transmitted message, the transmitter feeds three zeros into the shift
register, to match the length of the CRC.
- When the last zero is fed into the input adder, the shift register contains the CRC.
The CRC polynomial and seed are shown in Table 330.
Table 330. SPI response message CRC, 3-bit
14.4.3.5 Message (KAC) with 3-bit CRC
14.4.3.6 Example 3-bit CRC calculations
Some example CRC calculations for 32-bit SPI commands are shown in Table 331. Table 331. SPI 3-bit CRC calculation examples
14.5 Exception handling
14.5.1 Standard basic status reporting field
for the previous SPI command.
14.5.1.1 Basic status field for responses to register commands
Table 332. Basic status field for responses to register commands
14.5.1.2 Basic status field for responses to sensor data request commands
Table 333. Basic status field for responses to sensor data request commands
14.5.2 Alternative basic status reporting field
Table 334. Alternative basic status reporting field
Figure 95. Internal status mapping and SPI basic status content
14.5.3 Standard detailed status field reporting
Table 335. SPI error response status field definition
Table 335. SPI error response status field definition...continued
14.5.4 Alternative detailed status field reporting
Table 336. Alternate SPI error response status field definition
Table 336. Alternate SPI error response status field definition...continued
14.5.5 Error responses
Table 337. Error responses SD[11:0] Sensor Data or the Sensor Data Field Error Code.
- For unsigned data, the Sensor Data Field Error Code is 0x000
- For signed data, the Sensor Data Field Error Code is 0x800 See Section 14.5.3 for Sensor Data Request commands. For all other commands, all bits are '0'. SF[3:0] Status. See Section 14.5.3
Table 338. Error response description
14.5.6 SPI error
- SCLK is high when SS_B is asserted
- The number of SCLK rising edges detected while SS_B is asserted is not equal to 0 or
- SCLK is high when SS_B is deasserted
- A command message CRC error is detected (MOSI)
- A Sensor Data Request is received for a SOURCEID that is not enabled
- A Register Write command to any register other than the DEVLOCK_WR register is received while ENDINIT is set. Product data sheet Rev. 6 — 8 February 2021
14.5.7 SPI data output verification error
The device includes a function to verify the integrity of the data output to the MISO pin. MISO_ERR flag in the DEVSTAT3 register is set. as defined in Section 14.5.3. during the subsequent SPI message. as defined in Section 14.5.3. during the subsequent SPI message. Figure 96. SPI data output verification
14.6 SPI timing diagram
Figure 97. SPI timing diagram
15 Inter-integrated circuit (I2C) interface
The device includes an interface compliant to the NXP I2C bus specification UM10204[1]. values and the total bus capacitance.
15.1 I2C bit transmissions
must be stable when SCL is high and change when SCL is low as shown in Figure 99. After the START signal has been transmitted by the master, the bus is considered busy. Timing for the start condition is specified in Section 10.14. Figure 98. I2C bit transmissions
15.2 I2C start condition
A bus operation is always started with a start condition (START) from the master.
considered busy. Timing for the start condition is specified in Section 10.14. A start condition (START) and a repeat START condition (rSTART) are identical. Figure 99. I2C start condition
15.3 I2C byte transmissions
for the Acknowledge bit. Timing for the byte transmissions is specified in Section 10.14. Figure 100. I2C byte transmissions
15.4 I2C acknowledge and not acknowledge transmissions
Section 10.14 must also be taken into account.
- No receiver is present on the bus with the transmitted address.
- The addressed receiver is unable to receive or transmit because it is performing some
real-time function and is not ready to start communication with the master.
- The receiver receives unrecognized data or commands.
- The receiver cannot receive any more data bytes.
- The master-receiver signals the end of the transfer to the slave transmitter.
transfer, or a repeated START to initiate a new transfer. An example ACK and NACK are shown in Figure 101. Figure 101. I2C acknowledge and not acknowledge transmission
15.5 I2C stop condition
A bus operation is always terminated with a stop condition (STOP) from the master. Figure 102. After the STOP has been transmitted by the master, the bus is considered free. Timing for the stop condition is specified in Section 10.14. Figure 102. I2C stop condition
15.6 I2C register transfers
15.6.1 Register write transfers
- The master transmits a START condition
- The master transmits the 7-bit slave address
- The master transmits a '0' for the Read/Write Bit to indicate a Write operation
- The slave transmits an ACK
- The master transmits the register address to be written
- The slave transmits an ACK
- The master transmits the data byte to be written to the register address
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor 8. The slave transmits an ACK 9. The master transmits a STOP condition S Slave address W A Register address A REGISTER DATA A P Master transmission Slave transmission The device automatically increments the register address allowing for multiple register writes to be completed in one trans-action. In this case, the register write data transfers are constructed as follows: 1. The master transmits a START condition 2. The master transmits the 7-bit slave address 3. The master transmits a '0' for the Read/Write Bit to indicate a Write operation 4. The slave transmits an ACK 5. The master transmits the register address to be written 6. The slave transmits an ACK 7. The master transmits the data byte to be written to the register address 8. The slave transmits an ACK 9. The master transmits the data byte to be written to the register address +1 10.The slave transmits an ACK 11.Repeat step 9 and step 10 until all registers are written 12.The master transmits a STOP condition
15.6.2 Register read transfers
The device supports I2C register read data transfers. Register read data transfers are constructed as follows: 1. The master transmits a START condition 2. The master transmits the 7-bit slave address 3. The master transmits a '0' for the Read/Write Bit to indicate a Write operation 4. The slave transmits an ACK 5. The master transmits the register address to be read 6. The slave transmits an ACK 7. The master transmits a repeat START condition 8. The master transmits the 7-bit slave address 9. The master transmits a '1' for the Read/Write Bit to indicate a Read operation 10.The slave transmits an ACK 11.The slave transmits the data from the register addressed 12.The master transmits a NACK 13.The master transmits a STOP condition S Slave address W A Register address A rSTART Slave address R A Register data N P Master transmission Slave transmission The device automatically increments the register address allowing for multiple register reads to be completed in one trans-action. In this case, the register read data transfers are constructed as follows: Product data sheet Rev. 6 — 8 February 2021
- The master transmits a START condition
- The master transmits the 7-bit slave address
- The master transmits a '0' for the Read/Write Bit to indicate a Write operation
- The slave transmits an ACK
- The master transmits the register address to be read
- The slave transmits an ACK
- The master transmits a repeat START condition
- The master transmits the 7-bit slave address
- The master transmits a '1' for the Read/Write Bit to indicate a Read operation
15.6.3 Sensor data register read wrap around options
optimize the number of I2C transactions necessary for continuous reads of sensor data.
15.6.3.1 Single channel register read wrap around
back to the DEVSTAT_COPY register as shown in . Table 339. Dual channel register read wrap around
Table 339. Dual channel register read wrap around...continued
15.7 I2C timing diagram
Figure 103. I2C timing diagram
Figure 104. Package outline for LQFN16 (SOT1688-1(SC))
Figure 105. Package outline detail for LQFN16 (SOT1688-1(SC))
Figure 106. Package outline notes for LQFN16 (SOT1688-1(SC))
Figure 107. Package outline for LQFN16 (SOT1688-1(DD))
Figure 108. Package outline detail for LQFN16 (SOT1688-1(DD))
Figure 109. Package outline notes for LQFN16 (SOT1688-1(DD))
17 Soldering
Figure 110. Reflow soldering footprint part 1 for HLQFN16 (SOT1688-1(SC))
Figure 111. Reflow soldering footprint part 2 for HLQFN16 (SOT1688-1(SC))
Figure 112. Reflow soldering footprint part 3 for HLQFN16 (SOT1688-1(SC))
Figure 113. Reflow soldering footprint part 4 for HLQFN16 (SOT1688-1(SC))
Figure 114. Reflow soldering footprint part 5 for HLQFN16 (SOT1688-1(SC))
Figure 115. Reflow soldering footprint part 1 for HLQFN16 (SOT1688-1(DD))
Figure 116. Reflow soldering footprint part 2 for HLQFN16 (SOT1688-1(DD))
Figure 117. Reflow soldering footprint part 3 for HLQFN16 (SOT1688-1(DD))
Figure 118. Reflow soldering footprint part 4 for HLQFN16 (SOT1688-1(DD))
Figure 119. Reflow soldering footprint part 5 for HLQFN16 (SOT1688-1(DD))
18 References
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor [4] AEC - Q100 - Rev-H, September 11, 2014 - Failure Mechanism Based Stress Test Qualification for Integrated Circuits http://www.aecouncil.com/Documents/AEC_Q100_Rev_H_Base_Document.pdf http://www.aecouncil.com/Documents/AEC_Q100_Rev_H_Base_Document.pdf [5] PSI5 Technical Specification Version 2.1, Dated October 8, 2012 Product data sheet Rev. 6 — 8 February 2021
- FXLS9xxxx, v.6, Dual Channel Inertial Sensor, supercedes and replaces FXLS9xxxx, v.5.15, Dual Channel Inertial Sensor.
- Global changes: – Performed minor grammatical and typographic revisions throughout. – Updated all images to comply with NXP image standards. FXLS9xxxx v.5.15 20201208 Product data sheet — FXLS9xxxx v.5.14
Table 340. Revision history
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor
20 Legal information
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Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected Product data sheet Rev. 6 — 8 February 2021
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified or documented vulnerabilities. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. Suitability for use in automotive applications — This NXP product has been qualified for use in automotive applications. It has been developed in accordance with ISO 26262, and has been ASIL-classified accordingly. If this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as “Critical Applications”), then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer. Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to customer’s incorporation of any product in a Critical Application.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. Product data sheet Rev. 6 — 8 February 2021
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Tables Tab. 3. DSI3 discovery mode external component Tab. 4. PSI5 parallel or universal mode external Tab. 5. PSI5 daisy chain mode external component Tab. 16. Electrical characteristics - temperature Tab. 17. Electrical characteristics - inertial sensor Tab. 20. Lateral, High g, SPI/DSI3 12-bit noise Tab. 21. Z-Axis, High g, SPI/DSI3 12-bit noise Tab. 22. Lateral, High g, PSI5 10-bit noise Tab. 23. Z-Axis, High g, PSI5 10-bit noise Tab. 24. Electrical characteristics - inertial sensor Tab. 25. Medium g, SPI/DSI3 12-bit offset Tab. 27. Lateral, Medium g, SPI/DSI3 12-bit noise Tab. 28. Z-axis, Medium g, SPI/DSI3 12-bit noise Tab. 29. Lateral, Medium g, PSI5 10-bit noise Tab. 30. Z-axis, Medium g, PSI5 10-bit noise Tab. 31. Electrical characteristics - inertial sensor Tab. 32. Electrical characteristics - lateral inertial Tab. 33. Electrical characteristics - Z-axis inertial Tab. 38. Dynamic electrical characteristics - signal Tab. 39. Dynamic electrical characteristics - signal Tab. 40. Dynamic electrical characteristics - analog Tab. 41. Dynamic electrical characteristics - digital Tab. 42. Dynamic electrical characteristics - Tab. 43. Dynamic electrical characteristics - supply Tab. 44. User accessible data - general device Tab. 45. User accessible data - communication Tab. 46. User accessible data - sensor specific Tab. 47. User accessible data - sensor specific Tab. 48. User accessible data - traceability Tab. 56. BUS IN under-voltage error (BUSINUV_ Tab. 58. Internal analog regulator voltage out of Tab. 59. Internal digital regulator voltage out of Tab. 60. Internal OTP regulator voltage out of range Tab. 65. User OTP write in process status bit (U_ Tab. 66. Channel 1 temperature sensor error Tab. 67. Channel 0 temperature sensor error Tab. 68. SPI MISO data mismatch error flag (MISO_ Tab. 70. Communication protocol revision register Tab. 71. Margin read status register (MREAD_ Product data sheet Rev. 6 — 8 February 2021
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Tab. 72. Margin read active status (MARGIN_RD_ Tab. 73. Margin read error status (MARGIN_RD_ Tab. 79. Bus switch control register (BUSSW_ Tab. 82. UF region selection registers (UF_ Tab. 85. Communication type register Tab. 89. Source identification registers Tab. 90. PDCM format control bits Tab. 95. Communication timing register (TIMING_ Tab. 96. Periodic data collection mode period Tab. 97. Oscillator training protocol selection bit Tab. 98. Command and response mode period Tab. 102. PSI5 error latching enable bit (PSI5_ Tab. 103. DSI3 simultaneous sampling enable (SS_ Tab. 104. PSI5 simultaneous sampling enable (SS_ Tab. 105. SPI simultaneous sampling enable (SS_ Tab. 107. Timing configuration #2 register (TIMING_ Tab. 108. PSI5 initialization phase 2 D19 and D20 Tab. 109. Oscillator training error counter Tab. 111. Background diagnostic mode fragment size Tab. 112. Background diagnostic mode enable Tab. 114. Sync pulse pull-down enable bit (SYNC_ Tab. 115. PSI5 daisy chain selection bit (DAISY_ Tab. 116. PSI5 low response current selection bit Tab. 118. Error message information extension bit Tab. 119. PSI5 response message error detection Tab. 120. Initialization phase 2 data extension bit Tab. 121. DSI3 and PSI5 start time registers (PDCM_ Tab. 122. Periodic data collection mode response Tab. 123. Synchronous mode: Source ID response Tab. 124. Asynchronous mode: Source ID response Tab. 125. Broadcast read command type selection Tab. 126. DSI3 and PSI5 command blocking time Tab. 130. SPI status reporting selection bit (SPI_ Tab. 132. SPI CRC length and seed bits (SPI_CRC_ Tab. 137. Channel 0 and Channel 1 user configuration #1 registers (CH0_CFG_U1, Tab. 138. Low-pass filter and sample rate selection Tab. 139. Channel 0 and Channel 1 user configuration #2 registers (CH0_CFG_U2, Tab. 141. Example user shift and multiplier Tab. 142. Example user shift and multiplier Tab. 143. Channel 0 and Channel 1 user configuration #3 registers (CH0_CFG_U3, Tab. 144. Unsigned data select bit Product data sheet Rev. 6 — 8 February 2021
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Tab. 145. Channel data type 0 selection bits Tab. 146. Channel data type 1 selection bits Tab. 147. Signal chain moving average selection bits Tab. 148. Channel 0 and Channel 1 user configuration #4 registers (CH0_CFG_U4, Tab. 150. Offset cancellation filter selection bits (OC_ Tab. 151. Arming pin configuration bits (ARM_ CFG[2:0]) and PCM range selection bit Tab. 152. Channel 0 and Channel 1 user configuration #5 register (CH0_CFG_U5, Tab. 154. Offset cancellation test limit bits (OC_ Tab. 156. Channel 0 and Channel 1 arming configuration registers (CH0_ARM_CFG, Tab. 157. Arming function down sampling selection Tab. 159. Positive arming window size definitions Tab. 160. Negative arming window size definitions Tab. 162. Arming threshold registers (CHx_ARM_T_ Tab. 163. Example threshold register values and Tab. 164. Offset cancellation user configuration Tab. 165. Channel 0 offset cancellation final phase control bit (CH0_OCFINAL, CH1_ Tab. 166. Channel 1 offset cancellation final phase control bit (CH0_OCFINAL, CH1_ Tab. 167. User offset calibration registers (Chx_U_ Tab. 168. Channel-specific status register (CH0_ Tab. 169. Offset cancellation phase status Tab. 172. Device status copy register (DEVSTAT_ Tab. 173. Sensor data #0 registers (CHx_ Tab. 174. Sensor data #1 registers (CHx_ Tab. 175. Channel-specific factory configuration Tab. 191. User data registers (USERDATA_0 - Tab. 192. PSI5 initialization phase 2 data Tab. 193. User data registers (USERDATA_10 - Tab. 198. Memory type code: CRC verified OTP Tab. 199. Memory type code: ENDINIT CRC verified Tab. 201. Signal trim and compensation variable Tab. 216. Offset cancellation phases and times: Tab. 217. Offset cancellation phases and times: PSI5 Tab. 220. Temperature sensor output scaling Tab. 221. Command and response mode example Product data sheet Rev. 6 — 8 February 2021
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Tab. 222. Command and response mode - command Tab. 223. Command and response mode - field Tab. 224. Command and response mode command Tab. 225. Command and response mode - CRC Tab. 226. Command and response mode response Tab. 228. Command and response mode - response Tab. 229. Command and response mode - field Tab. 230. Command and response mode response Tab. 231. DSI3 command and response mode Tab. 235. Register read command: response format Tab. 237. Register write command format description .. 159 Tab. 239. Register write command: response format Tab. 241. Global register write command format Tab. 242. Global register write command: response Tab. 243. Global register write command: response Tab. 244. PDCM enable command and BDM_EN bit Tab. 245. Enter periodic data collection mode Tab. 246. Enter periodic data collection mode Tab. 247. Enter periodic data collection mode Tab. 248. Enter periodic data collection mode Tab. 252. Reserved command response format Tab. 253. Periodic data collection mode response Tab. 254. Periodic data collection mode status field Tab. 255. Periodic data collection mode response Tab. 256. Periodic data collection mode - CRC Tab. 258. DSI3 error handling - discovery mode and Tab. 265. PSI5 initialization phase 2 data Tab. 270. Default PSI5-P16C transmission mode Tab. 271. Default PSI5-P16C transmission mode, Tab. 272. Default PSI5-P16C transmission mode, Tab. 273. Dual transmission mode 10-bit Tab. 274. Dual transmission mode 10-bit Tab. 275. Dual transmission mode 16-bit Tab. 276. Dual transmission mode 16-bit Tab. 278. Daisy chain programming commands and Tab. 279. Daisy chain programming response code Tab. 288. Programming mode via PSI5 command Tab. 289. Programming mode via PSI5 command Tab. 290. Programming mode via PSI5 XLONG Tab. 291. Programming mode via PSI5 XLONG command data format with sync bits - Tab. 292. Programming mode via PSI5 response Tab. 293. Programming mode via PSI5 short Tab. 295. Programming mode via PSI5 long Product data sheet Rev. 6 — 8 February 2021
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Tab. 297. Programming mode via PSI5 long Tab. 299. Programming mode via PSI5 commands Tab. 300. Programming mode via PSI5 response Tab. 306. Register read command message format Tab. 308. Register read response message format Tab. 310. Register write command message format Tab. 312. Register write response message format Tab. 313. Sensor data request command message Tab. 314. Sensor data request command message Tab. 315. Sensor data request response message Tab. 316. Sensor data request response message Tab. 317. Reserved command response message Tab. 318. Reserved command response message Tab. 332. Basic status field for responses to register Tab. 333. Basic status field for responses to sensor Tab. 336. Alternate SPI error response status field Figures Fig. 3. PSI5 parallel or universal mode application Fig. 13. VBUF capacitor monitor timing, PSI5 Fig. 14. VBUF capacitor monitor timing, psi5 Fig. 16. Command and response mode oscillator Fig. 17. Periodic data collection mode oscillator Fig. 23. Sinc filter response 3rd order sinc filter Fig. 24. 400 Hz, 4-pole low-pass filter response Fig. 25. 400 Hz, 4-pole low-pass filter response Fig. 26. 400 Hz, 3-pole low-pass filter response Fig. 27. 400 Hz, 3-pole low-pass filter response Fig. 28. 325 Hz, 3-pole low-pass filter response Fig. 29. 325 Hz, 3-pole low-pass filter response Fig. 30. 370 Hz, 2-pole low-pass filter response Fig. 31. 370 Hz, 2-pole low-pass filter response Fig. 32. 180 Hz, 2-pole low-pass filter response Product data sheet Rev. 6 — 8 February 2021
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Fig. 33. 180 Hz, 2-pole low-pass filter response Fig. 34. 100 Hz, 2-pole low-pass filter response Fig. 35. 100 Hz, 2-pole low-pass filter response Fig. 36. 1500 Hz, 4-pole low-pass filter response Fig. 37. 1500 Hz, 4-pole low-pass filter response Fig. 38. 500 Hz, 3-pole low-pass filter response Fig. 39. 500 Hz, 3-pole low-pass filter response Fig. 40. 800 Hz, 4-pole low-pass filter response Fig. 41. 800 Hz, 4-pole low-pass filter response Fig. 42. 1200 Hz, 4-pole low-pass filter response Fig. 43. 1200 Hz, 4-pole low-pass filter response Fig. 44. 120 Hz, 3-pole low-pass filter response Fig. 45. 120 Hz, 3-pole low-pass filter response Fig. 46. 120 Hz, 2-pole low-pass filter output Fig. 47. 120 Hz, 2-pole low-pass filter output Fig. 48. 50 Hz, 4-pole low-pass filter response Fig. 49. 50 Hz, 4-pole low-pass filter response Fig. 51. 0.04 Hz offset cancellation low–pass filter Fig. 52. 0.005 Hz offset cancellation low-pass filter Fig. 53. Output interpolation example: Linear Fig. 54. Temperature sensor signal chain block Fig. 56. Arming function block diagram - moving Fig. 57. Arming function block diagram - count Fig. 58. Arming condition, moving average and Fig. 59. Arming function block diagram - unfiltered Fig. 63. DSI3 command receiver timing diagram: Fig. 64. DSI3 command receiver timing diagram: Fig. 66. Discovery mode current sense circuit block Fig. 67. DSI3 discovery mode sensing timing Fig. 69. Command and response mode example Fig. 70. Command and response mode command Fig. 71. Command and response mode response Fig. 73. Command and response mode timing Fig. 74. Background diagnostic mode command bit Fig. 76. Periodic data collection mode timing Fig. 77. Background diagnostic mode timing Fig. 79. Synchronous sampling mode with minimum Fig. 87. Example Manchester encoded data Fig. 89. PSI5 initialization timing, synchronous Fig. 90. PSI5 initialization timing, asynchronous Fig. 92. Synchronous sampling mode with minimum Fig. 94. Standard 32-bit SPI protocol timing Fig. 95. Internal status mapping and SPI basic Fig. 101. I2C acknowledge and not acknowledge Fig. 104. Package outline for LQFN16 Product data sheet Rev. 6 — 8 February 2021
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Fig. 105. Package outline detail for LQFN16 Fig. 106. Package outline notes for LQFN16 Fig. 107. Package outline for LQFN16 Fig. 108. Package outline detail for LQFN16 Fig. 109. Package outline notes for LQFN16 Fig. 110. Reflow soldering footprint part 1 for Fig. 111. Reflow soldering footprint part 2 for Fig. 112. Reflow soldering footprint part 3 for Fig. 113. Reflow soldering footprint part 4 for Fig. 114. Reflow soldering footprint part 5 for Fig. 115. Reflow soldering footprint part 1 for Fig. 116. Reflow soldering footprint part 2 for Fig. 117. Reflow soldering footprint part 3 for Fig. 118. Reflow soldering footprint part 4 for Fig. 119. Reflow soldering footprint part 5 for Product data sheet Rev. 6 — 8 February 2021
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor
11.2.6.2 Supply error reporting disable bit (SUP_
11.2.8 Bus switch control register (BUSSW_
11.2.10 UF region selection registers (UF_
11.2.11 Communication type register
11.2.13 Source identification registers
11.2.13.2 PDCM format control bits
11.2.14 Communication timing register (TIMING_
11.2.14.1 Periodic data collection mode period
11.2.14.2 Oscillator training protocol selection bit
11.2.14.3 Clock calibration value reset (CK_CAL_
11.2.14.4 Command and response mode period
11.2.15.2 PSI5 error latching enable bit (PSI5_
11.2.16 Timing configuration #2 register (TIMING_
11.2.16.1 PSI5 initialization phase 2 D19 and D20
11.2.16.2 Oscillator training error counter
11.2.16.4 Background diagnostic mode fragment size
11.2.16.5 Background diagnostic mode enable
11.2.17.1 Sync pulse pull-down enable bit (SYNC_
11.2.17.2 PSI5 daisy chain selection bit (DAISY_
11.2.17.3 PSI5 low response current selection bit
11.2.17.5 Error message information extension bit
11.2.17.6 PSI5 response message error detection
11.2.17.7 Initialization phase 2 data extension bit
11.2.18 DSI3 and PSI5 start time registers (PDCM_
11.2.18.1 Periodic data collection mode response
11.2.18.2 Broadcast read command type selection
11.2.19 DSI3 and PSI5 command blocking time
11.2.20.1 SPI status reporting selection bit (SPI_
11.2.20.3 SPI CRC length and seed bits (SPI_CRC_
11.2.23 Channel 0 and Channel 1 user
configuration #1 registers (CH0_CFG_U1,
11.2.23.1 Low-pass filter and sample rate selection
11.2.23.2 User sensitivity shift selection bits (U_SNS_
11.2.24 Channel 0 and Channel 1 user
configuration #2 registers (CH0_CFG_U2,
11.2.24.1 User sensitivity multiplier bits (U_SNS_
11.2.25 Channel 0 and Channel 1 user
configuration #3 registers (CH0_CFG_U3,
11.2.25.2 Channel data type 0 selection bits
11.2.25.3 Channel data type 1 selection bits
11.2.25.4 Signal chain moving average selection bits
11.2.26 Channel 0 and Channel 1 user
configuration #4 registers (CH0_CFG_U4,
11.2.26.1 Reset offset cancellation startup bit
11.2.26.3 Offset cancellation filter selection bits (OC_
11.2.26.4 Arming pin configuration bits (ARM_
CFG[2:0]) and PCM range selection bit Product data sheet Rev. 6 — 8 February 2021
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor
11.2.27 Channel 0 and Channel 1 user
configuration #5 register (CH0_CFG_U5,
11.2.27.2 Offset cancellation test limit bits (OC_
11.2.28 Channel 0 and Channel 1 arming
configuration registers (CH0_ARM_CFG,
11.2.28.1 Arming function down sampling selection
11.2.28.3 Arming window size (ARM_WS_N[1:0], A_
11.2.29 Arming threshold registers (CHx_ARM_T_
11.2.30 Offset cancellation user configuration
11.2.30.1 Channel 0 and Channel 1 offset
cancellation final phase control bit (CH0_
11.2.31 User offset calibration registers (Chx_U_
11.2.32 Channel-specific status register (CH0_
11.2.32.2 Offset cancellation phase status
11.2.33 Device status copy register (DEVSTAT_
11.2.34 Sensor data #0 registers (CHx_
11.2.35 Sensor data #1 registers (CHx_
11.2.36 Channel-specific factory configuration
11.2.45 User data registers (USERDATA_0 -
11.2.45.1 PSI5 initialization phase 2 data
11.2.46 User data registers (USERDATA_10 -
11.3 OTP and read/write register array CRC
11.4.1 VBUF regulator capacitor and capacitor
11.4.1.3 VBUF capacitance monitor timing, PSI5
11.4.2 BUS_I, VBUF, VREG, VREGA,
11.7.2 Temperature sensor output scaling
Product data sheet Rev. 6 — 8 February 2021
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor
12.2.1 Address assignment method for parallel
12.2.2 Address assignment method for bus switch
12.2.3 DSI3 discovery mode: Address assignment
method for resistor connected daisy chain
12.3.1 DSI3 command and response mode
12.3.2 DSI3 command and response mode
12.3.4 DSI3 command and response mode
12.3.4.3 Global register write command to the
12.3.4.4 Enter periodic data collection mode
12.4 DSI3 periodic data collection mode and
12.4.1 DSI3 periodic data collection mode and
background diagnostic mode command
12.4.2 DSI3 periodic data collection mode
12.4.4 Background diagnostic mode response
12.4.6 DSI3 periodic data collection mode and
background diagnostic mode command
12.4.7.2 Synchronous sampling mode with minimum
12.6.3 Resistor connected daisy chain network
12.7.1 Daisy chain and discovery mode error
13.4.2.1 PSI5 initialization phase 2 data
13.5.3 Synchronous sampling mode with minimum
13.6 PSI5 default mode (un-programmed PSI5
13.9.4 Normal mode error handling with internal
13.9.5 Normal mode error handling with internal
13.10.2.1 PSI5 programming mode - command bit
13.10.2.2 PSI5 programming mode - command
Product data sheet Rev. 6 — 8 February 2021
NXP Semiconductors FXLS9xxxx Dual channel inertial sensor
13.10.2.5 Extra long frame command and response
13.10.3 PSI5 programming mode command and
13.10.4 Programming mode via PSI5 error
14.3.3.1 Sensor data request command message
14.3.3.2 Sensor data request response message
14.3.4.2 Reserved command response message
14.5.1.1 Basic status field for responses to register
14.5.1.2 Basic status field for responses to sensor
15.4 I2C acknowledge and not acknowledge
15.6.3 Sensor data register read wrap around
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 February 2021 Document identifier: FXLS9xxxx