FXLS8974CFR3

FXLS8974CF NXP | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 General description
• 2 Features and benefits
• 3 Applications
• 3.1 Industrial IOT
• 3.2 Medical
• 3.3 Consumer devices
• 4 Ordering information
• 4.1 Ordering options
• 5 Block diagram
• 6 Pinning information
• 6.1 Pinning
• 6.2 Pinning description
• 6.3 Orientation
• 7 Limiting values
• 8 Recommended operating conditions
• 9 Mechanical characteristics
• 10 Electrical characteristics
• 11 Temperature sensor characteristics
• 12 I2C digital interface
• 12.1 I2C interface characteristics
• 12.1.1 General I2C operation
• 12.1.2 I2C read/write operations
• 12.1.2.1 Single-byte read
• 12.1.2.2 Multiple-byte read
• 12.1.2.3 Single-byte write
• 12.1.2.4 Multiple-byte write
• 12.1.2.5 I2C data sequence diagrams
• 13 SPI interface
• 13.1 General SPI operation
• 13.2 SPI write operations with 3- or 4-wire mode
• 13.3 SPI read operations with 4-wire mode
• 13.4 SPI read operations with 3-wire mode
• 13.5 SPI timing specifications (4-wire mode and
• 13.6 SPI timing specifications (software enabled
• 14 Operating modes
• 15 Register descriptions
• 15.1 INT_STATUS register (address 00h)
• 15.2 TEMP_OUT register (address 01h)
• 15.3 VECM_LSB register (address 02h)
• 15.4 VECM_MSB register (address 03h)
• 15.5 OUT_X_LSB, OUT_X_MSB, OUT_Y_LSB,
• 15.6 BUF_STATUS register (address 0Bh)
• 15.7 BUF_X_LSB, BUF_X_MSB, BUF_Y_LSB,
• 15.8 PROD_REV register (address 12h)
• 15.9 WHO_AM_I register (address 13h)
• 15.10 SYS_MODE register (address 14h)
• 15.11 SENS_CONFIG1 register (address 15h)
• 15.12 SENS_CONFIG2 register (address 16h)
• 15.13 SENS_CONFIG3 register (address 17h)
• 15.14 SENS_CONFIG4 register (address 18h)
• 15.15 SENS_CONFIG5 register (address 19h)
• 15.16 WAKE_IDLE_LSB register (address 1Ah)
• 15.17 WAKE_IDLE_MSB register (address 1Bh)
• 15.18 SLEEP_IDLE_LSB register (address 1Ch)
• 15.19 SLEEP_IDLE_MSB register (address 1Dh)
• 15.20 ASLP_COUNT_LSB, ASLP_COUNT_MSB
• 15.21 INT_EN register (address 20h)
• 15.22 INT_PIN_SEL register (address 21h)
• 15.23 OFF_X, OFF_Y, OFF_Z registers
• 15.24 BUF_CONFIG1 register (address 26h)
• 15.25 BUF_CONFIG2 register (address 27h)
• 15.26 ORIENT_STATUS register (address 28h)
• 15.27 ORIENT_CONFIG register (address 29h)
• 15.28 ORIENT_DBCOUNT register (address
• 15.29 ORIENT_BF_ZCOMP register (address
• 15.30 ORIENT_THS register (address 2Ch)
• 15.31 Sensor Data Change Detection (SDCD)
• 15.31.1 SDCD_INT_SRC1 register (address 2Dh)
• 15.31.2 SDCD_INT_SRC2 register (address 2Eh)
• 15.31.3 SDCD_CONFIG1 register (address 2Fh)
• 15.31.4 SDCD_CONFIG2 register (address 30h)
• 15.31.5 SDCD_OT_DBCNT register (address 31h)
• 15.31.6 SDCD_WT_DBCNT register (address 32h)
• 15.31.7 SDCD_LTHS_LSB register (address 33h)
• 15.31.8 SDCD_LTHS_MSB register (address 34h)
• 15.31.9 SDCD_UTHS_LSB register (address 35h)
• 15.31.10 SDCD_UTHS_MSB register (address 36h)
• 15.32 SELF_TEST_CONFIG1 register (address
• 15.33 SELF_TEST_CONFIG2 register (address
• 16 Application information
• 16.1 System connections
• 16.2 Typical application circuits
• 16.3 Power supply considerations
• 17 Package outline
• 17.1 Package description
• 17.2 Lead dimension detail
• 18 Soldering information
• 18.1 Printed circuit board layout and device
• 18.1.1 Overview of soldering considerations
• 18.1.2 Halogen content
• 19 Mounting information
• 19.1 PCB mounting recommendations
• 20 Glossary
• 21 References
• 22 Revision history
• 23 Legal information

3-Axis Low-g Accelerometer Rev. 1 — 27 April 2021 Objective data sheet

1 General description

FXLS8974CF is a compact 3-axis MEMS accelerometer designed for use in a wide range of industrial and medical IOT applications that require ultra-low-power wake-up on motion. The part supports both high-performance and low-power operating modes, allowing maximum flexibility to meet the resolution and power needs for various unique use cases. A number of advanced, integrated digital features enable designers to reduce the overall system power consumption and simplify host data collection. FXLS8974CF is available in a 2 mm x 2 mm x 0.95 mm 10-pin DFN package with 0.4 mm pitch and wettable flanks. The device is qualified to industrial standards over the extended –40 °C to +105 °C temperature range. The combination of sensor performance, system power-saving features, and extended over-temperature-range performance makes FXLS8974CF an ideal accelerometer for motion sensing in the IOT.

2 Features and benefits

• ±2/4/8/16 g user-selectable, full-scale measurement ranges
• 12-bit acceleration data
• 8-bit temperature sensor data
• Low noise: 280 µg/√Hz in high performance mode
• Low-power capability: – ≤ 1 μA IDD for ODRs up to 6.25 Hz – < 4 µA IDD for ODRs up to 50 Hz
• Selectable ODRs up to 3200 Hz; Flexible Performance mode allows for custom ODRs with programmable decimation (resolution) and idle-time settings
• 144 byte output data buffer (FIFO/LIFO) capable of storing up to 32 12-bit X/Y/Z data triplets
• Flexible Sensor Data Change Detection (SDCD) function for realizing motion or no motion, high-g/low-g, freefall, and other inertial events
• Autonomous orientation detection function (Portrait/Landscape/Up/Down)
• Dedicated low-power motion-detection mode with one wire interface option
• 12-bit vector magnitude calculation
• Trigger input for synchronizing data collection with an external system
• I2C interface frequencies up to 1 MHz; 3- and 4-wire SPI interface with clock frequencies up to 4 MHz
• Bidirectional self-test diagnostic: Device motion or orientation does not impact the result.

3 Applications

3.1 Industrial IOT

• Asset tracking
• Equipment monitoring
• Smart metering / tamper detection
• Surveillance
• Point of sale devices
• Indoor localization

3.2 Medical

• Patient activity monitors
• Drug delivery
• Clinical care
• Smart inhalers

3.3 Consumer devices

• Connected home
• Wearables
• Portable electronics
• Mobile accessories

4 Ordering information

Table 1. Ordering information

4.1 Ordering options

Table 2. Ordering options

5 Block diagram

Figure 1. Block Diagram

6 Pinning information

6.1 Pinning

Figure 2. Pin configuration diagram

6.2 Pinning description

• SPI_MISO: In 4-wire SPI mode this pin functions as the serial data output. INTF_SEL = GND:
• SA0: This pin selects the least significant bit of the device I2C secondary address. SDA / SPI_MOSI / SPI_ DATA 4 Mode-dependent Multifunction serial interface pin.[2] INTF_SEL = VDD:
• SPI_MOSI: In 4-wire SPI mode this pin functions as the serial data input.
• SPI_DATA[3]: In 3-wire SPI mode, this pin functions as the bidirectional serial data input/output. INTF_SEL = GND:
• SDA: This pin functions as the I2C Serial Data input/output. SCL / SCLK 5 Mode-dependent Multifunction serial interface pin.[2] INTF_SEL = VDD:
• SPI serial clock input (3- and 4-wire modes) INTF_SEL = GND:
• I2C serial clock input

Table 3. Pin descriptions

unconnected if unused in the application circuit. ms to disable motion detection and enter Hibernate mode. INTF_SEL 9 Device interface mode selection pin. GND 10 Supply return connection. Table 3. Pin descriptions...continued [1] BT_MODE state is latched after POR. [2] Under Hibernate mode, pin configuration is High Impedance. the SPI_MISO and SPI_MOSI pins together on the PCB. [4] An external pull-up resistor is required on this pin when BT_MODE = VDD. push-pull output after POR, or after exiting Hibernate mode.

6.3 Orientation

Figure 3. Sensitive axes orientation and output response to ±1 g (gravity) stimulus

7 Limiting values

without damage. Functional operation at absolute maximum rating is not guaranteed. application of any voltage higher than the maximum-rated voltage. Table 4. Device absolute maximum ratings

Table 5. ESD and latch-up-protection characteristics part or cause the part to otherwise fail. electrostatic sensitive devices.

8 Recommended operating conditions

Table 6. Nominal operating conditions

9 Mechanical characteristics

VDD = 1.8 V, T = 25 °C , unless otherwise noted. Table 7. Accelerometer sensor performance parameters

VDD = 1.8 V, T = 25 °C , unless otherwise noted.

200 Hz ≤ ODR

0.781 Hz ≤

Table 7. Accelerometer sensor performance parameters...continued

mm (47 mil) overall thickness. [2] See Cross-axis sensitivity in Section 20 "Glossary". [3] In low-power mode, higher ODR settings result in a lower noise density figure. VDD = 1.8 V , T = 25 °C, unless otherwise noted. Table 8. Electrical characteristics

VDD = 1.8 V , T = 25 °C, unless otherwise noted. Table 8. Electrical characteristics...continued

VDD = 1.8 V , T = 25 °C, unless otherwise noted. command. In that case, their durations add up. independent of the selected ODR.

11 Temperature sensor characteristics

VDD = 1.8 V, T = 25 °C, unless otherwise noted. Table 9. Temperature sensor performance parameters

12 I2C digital interface

functioning normally (clamping).

• Fast-mode Plus (Fm+) at 1000 kHz
• Fast-mode (Fm) at 400 kHz
• Standard-mode (Sm) at 100 kHz Objective data sheet Rev. 1 — 27 April 2021

Table 10. I2C serial interface pin description

12.1 I2C interface characteristics

Table 11. FXLS8974CF I2C read and write addresses Table 12. I2C secondary timing values for Standard-mode (Sm), Fast-mode (Fm), and Fast-mode Plus (Fm [1] All values referred to VIH(min) and VIL(max) levels. [2] Should be backward compatible with Fast mode.

[3] tVD;DAT referred to the time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse). tVD;ACK by a transition time. [5] tVD;ACK = time for ACK signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse). specified fall time when considering bus timing. Figure 4. I2C secondary timing diagram for Standard-mode, Fast-mode and Fast-mode Plus

12.1.1 General I2C operation

SDA and SCL. When the I2C-bus is free, SCL and SDA are high. capacitance (PCB trace + parasitic device capacitances). is defined as a HIGH-to-LOW transition on SDA line while the SCL line is held HIGH.

NXP Semiconductors FXLS8974CF 3-Axis Low-g Accelerometer the data line low so that it remains stable low during the high period of the acknowledge clock period. The number of bytes per transfer is unlimited. If a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the SCL line low to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the clock line. This delay action is called clock stretching. Not all primary devices support clock stretching. This device implements clock stretching—the SCL line may be stretched (pulled low) for up to 1 µs when needed during a read operation. When applied, clock stretching occurs after the ACK issued by the I2C bus primary. A LOW-to-HIGH transition on the SDA line while the SCL line is high is defined as a stop condition (SP) signal. The primary issuing the SP signal always terminates a write or burst write. A primary should properly terminate a read by not acknowledging a byte at the appropriate time in the protocol, followed by the SP signal. A primary may also issue a repeated start signal (SR) during a transfer.

12.1.2 I2C read/write operations

12.1.2.1 Single-byte read

The primary transmits a start condition (ST) to FXLS8974CF, followed by the secondary address, with the R/W bit set to '0' for a write, and the FXLS8974CF sends an acknowledgment. Then the primary transmits the address of the register to read and the FXLS8974CF sends an acknowledgment. The primary transmits a repeated start condition (SR), followed by the secondary address with the R/W bit set to '1' for a read from the previously selected register. The FXLS8974CF then acknowledges and transmits the data from the requested register. The primary does not acknowledge (NAK) the transmitted data and then transmits a stop condition to end the data transfer.

12.1.2.2 Multiple-byte read

When performing a multi-byte or burst read, FXLS8974CF automatically increments the register read address pointer after a read command is received. Therefore, after following the steps of a single-byte read, multiple bytes of data can be read from sequential register addresses after each FXLS8974CF acknowledgment (ACK) is received. Data can be read until the primary issues a no acknowledge (NAK), followed by a stop condition (SP) signaling the end of the transfer.

12.1.2.3 Single-byte write

To start a write command, the primary transmits a start condition (ST) to the FXLS8974CF, followed by the secondary address with the R/W bit set to '0' for a write, and the FXLS8974CF sends an acknowledgment. Then the primary transmits the address of the register to write to, and the FXLS8974CF sends an acknowledgment. Then the primary transmits the 8-bit data to write to the designated register and the FXLS8974CF sends an acknowledgment signaling it has received the data. Since this transmission is complete, the primary transmits a stop condition (SP) to end the data transfer. The data sent to the FXLS8974CF is now stored in the appropriate register.

12.1.2.4 Multiple-byte write

FXLS8974CF automatically increments the register address write pointer after a write command is received. Therefore, after following the steps of a single-byte write, multiple Objective data sheet Rev. 1 — 27 April 2021

12.1.2.5 I2C data sequence diagrams

Figure 5. I2C Data Sequence Diagrams

13 SPI interface

For CPOL = 0, the idle value of the clock is zero, and the active value of the clock is 1. and data is propagated on the falling edge (high to low transition) of the clock.

13.1 General SPI operation

seven SCLK cycles are used to latch the register read or write address. to select 3-wire SPI interface mode, set the SENS_CONFIG1[SPI_M] = 1.

13.2 SPI write operations with 3- or 4-wire mode

Figure 6. SPI single-byte write protocol diagram (3- or 4-wire mode), R/W = 0 but with additional data bytes transferred over additional 8 SCLK cycle periods. bytes has been written, a rising edge on the SPI_CS_B pin terminates the transaction. Figure 7. SPI multiple-byte write protocol diagram (3- or 4-wire mode), R/W = 0

13.3 SPI read operations with 4-wire mode

Figure 8. SPI single-byte read protocol diagram (4-wire mode), R/W = 1 rising edge on SPI_CS_B terminates the transaction. Figure 9. SPI multiple-byte read protocol diagram (4-wire mode), R/W = 1

13.4 SPI read operations with 3-wire mode

an output and with bit D7 as the current output state. Figure 10. SPI single-byte read protocol diagram (3-wire mode)

Figure 11. SPI multiple-byte read protocol diagram (3-wire mode)

13.5 SPI timing specifications (4-wire mode and 3-wire hardwired modes)

present on all SPI signals, 105 °C, 1.8 V. Table 13. Secondary timing values

Figure 12. SPI timing diagram (4-wire mode)

13.6 SPI timing specifications (software enabled 3-wire mode)

present on all SPI signals, 105 °C, 1.8 V. impedance (high-z) state, with the SPI_MISO pin output driver disabled (tri-stated). Table 14. Secondary timing values

Figure 13. SPI timing diagram (3-wire mode)

14 Operating modes

floating/unconnected and not connected to GND. As soon as the supply reaches 1.71 V, the device BOOT process begins. (defaults enabled on the INT1 pin after POR). cannot be routed to INT1 pin. Table 15. FXLS8974CF operating modes descriptions

not available, and all previously written register settings are lost. up resistor; the device then exits Hibernate mode and starts the BOOT process. interfaces is possible after the BOOT process completes. I2C and SPI interfaces are available. able to respond to read and write commands. back to the EXT_TRIG state and waits for the next trigger event. be written to with any value other than 0. Table 15. FXLS8974CF operating modes descriptions...continued [1] All register contents are preserved when transitioning from Active to Standby mode. Some registers are reset when transitioning from Standby to Active. The behavior of all registers is noted in Table 20. the device state, sensor data, and host programmed register contents are lost when this mode is entered. between these modes, see Table 16. creation of custom ODRs and also realizing the optimal trade-off between resolution (noise) and power dissipation in a given application or use case. using an MCU output compare/PWM/GPIO pin.

Figure 14. Operating modes transition diagram

1 OFF BOOT Apply VDD ≥ VDDmin

2 BOOT Standby BOOT_MODE = GND:

and waits for I2C/SPI commands. automatically set, see callout 7).

3 Standby Hibernate BOOT_MODE = GND:

only by toggling the SPI_CS_B / WAKE_UP pin.

4 Hibernate BOOT BT_MODE = GND:

triggered measurement has completed. Table 16. Operating modes transition criteria

completes when the INT1/MOT_DET pin is held high. using the I2C or SPI interfaces in order to change the default device configuration. Table 16. Operating modes transition criteria...continued does not cause the device to exit Hibernate mode when BT_MODE = VDD. Figure 15. BOOT2 sequence and One-wire motion-detection protocol diagram (BT_MODE = VDD)

1 VDD supply is not present (VDD < VDDmin); MCU and FXLS8974CF are both OFF; all IO pins

2 VDD ≥ VDDmin; MCU and FXLS8974CF are turned on; FXLS8974CF performs the BOOT

functions are enabled. FXLS8974CF turns on the BOOT_OUT output for TPULSE-BOOT2 ms. BOOT_OUT pins (one pull-up resistor for both pins).

3 If the MCU has not yet asserted the MOT_DET pin, FXLS8974CF enters Hibernate mode

4 The MCU asserts the MOT_DET pin high by enabling the pull-up; FXLS8974CF exits

the default threshold value used instead. 5 Motion detection phase: FXLS8974CF continually scans for motion at the preconfigured ODR. communicate with FXLS8974CF over the I2C or SPI interfaces.

6 Hibernate mode: When motion detection is no longer needed, the host MCU drives MOT_DET

Table 17. BOOT2 sequence and One-wire motion protocol phase descriptions Table 18. One-wire motion protocol threshold selections

NXP Semiconductors FXLS8974CF 3-Axis Low-g Accelerometer 21Operating mode VDD minVDD pin level 3 4 5 6 7 BOOT TBOOT1 TBOOT1 Edge triggered wakeup on SPI_CS_B/WAKE_UP line aaa-040848 TPULSE - BOOT1 INT/MOT_DET BOOTOFF STANDBY Hibernate STANDBY SENS_CONFIG1 [ACTIVE] = 1 SENS_CONFIG5 [HIBERNATE_EN] = 1 SPI serial command SPI_CS_B /WAKE_UP ACTIVE (WAKE) TPULSE - BOOT1 Figure 16. BOOT1 sequence (BT_MODE = GND)

Description

1 VDD supply is not present (VDD < VDDmin); MCU and FXLS8974CF are both off; all IO pins are floating/high-z.

2 VDD ≥ VDDmin; MCU and FXLS8974CF are turned on; FXLS8974CF performs the BOOT sequence and

provides the BOOT_OUT output pulse for TPULSE-BOOT1 ms. 3 FXLS8974CF enters standby mode directly after the BOOT sequence.

4 When the MCU sends a serial command to set SENS_CONFIG5[HIBERNATE_EN] bit to 1, FXLS8974CF

enters Hibernate mode. NOTE: The device enters into Hibernate mode 1us (typ) after the SPI_CS_B line is de-asserted for the corresponding HIBERNATE_EN serial command.

5 To wake up the device from Hibernate mode, the MCU toggles the SPI_CS_B/WAKE UP pin (see TFLT-

WAKE_UP deglitch filter time for transition out of Hibernate mode); FXLS8974CF performs the BOOT sequence and provides the BOOT_OUT output pulse for TPULSE-BOOT1 ms. 6 FXLS8974CF enters standby mode directly after the BOOT sequence.

7 When the MCU sends a serial command to set SENS_ CONFIG1[ACTIVE] bit to 1, FXLS8974CF enters

active mode. Table 19. BOOT1 sequence description (BT_MODE = GND)

15 Register descriptions

01h Interrupt and system status event flags. increment mechanism skips this register. Table 20. Register address map

by the auto-increment mechanism. by the auto-increment mechanism. by the auto-increment mechanism. by the auto-increment mechanism. by the auto-increment mechanism. by the auto-increment mechanism. Table 20. Register address map...continued

is skipped over by the auto-increment mechanism. is skipped over by the auto-increment mechanism. WHO_AM_I[1] R 13h 14h 86h 8-bit NXP unique sensor product ID. selection, soft reset, Active mode enable. feature, the value written to this register must be ≥ 1.

selection, and data collection mode. either STANDBY, ACTIVE, OR EXT_TRIG modes. ORIENT_CONFIG [1] [5] R/W 29h 2Ah 80h Orientation detection function configuration. ORIENT_BF_ZCOMP [1] [5] R/W 2Bh 2Ch 44h Back/Front orientation state change threshold angle. (Portrait/Landscape) and hysteresis settings. thresholds event flags source register. thresholds event flags source register. value MSB - sdcd_lths[11:8].

mode or a POR/BOR event occurs. [2] Register contents are reset when a transition from STANDBY to ACTIVE or EXT_TRIG mode occurs. default mode is little-endian, right justified. The byte order and justification is controlled by SENS_CONFIG3[LE_BE]. [4] The output data buffer contents become obsolete whenever a transition from STANDBY-to-ACTIVE or STANDBY-to-EXT_TRIG modes occurs. cannot be modified while in EXT_TRIG operating mode.

15.1 INT_STATUS register (address 00h)

Table 21. INT_STATUS register (address 00h) bit allocation 0: A new set of XYZ acceleration and temperature data is not available.

• The SRC_DRDY flag is cleared whenever one or more of the VECM, and OUT_X/Y/Z registers are read.
• Whenever BUF_CONFIG1[BUF_MODE1:0]] > 00b (buffer enabled), SRC_DRDY is held at logic '0'.
• When BT_MODE=GND, SRC_DRDY bit and the signaled interrupt are cleared whenever one or more of the VECM, and OUT_X/Y/Z registers are read.
• When BT_MODE=VDD, SRC_DRDY bit is cleared whenever one or more of the VECM, and OUT_X/Y/Z registers are read. However the data ready interrupt is signaled for TPULSE-MOT seconds (5 ms typ) and it clears itself automatically. The current data ready interrupt pulse is terminated when the device transitions into STANDBY mode before its completion and therefore may not span for entire TPULSE-MOT seconds. SRC_OVF Output data overflow event flag 0: No overflow condition detected. 1: A new set of XYZ acceleration and temperature output data latches into OUT_X/Y/Z and TEMP_ OUT registers before the previous set is completely read by the host. Notes:
• SRC_OVF is not set if at least one of the OUT_X/Y/Z registers was read before the new data set arrives.
• Whenever the INT_STATUS register is read, SRC_OVF is cleared.
• Whenever BUF_CONFIG1[BUF_MODE[1:0]] > 00b (buffer enabled), SRC_OVF is held at logic '0'.

Table 22. INT_STATUS register (address 00h) bit description

information on the BUF_GATE_ERR flag status.

• The SRC_BUF flag is only active when BUF_CONFIG1[BUF_MODE[1:0]] > 00b.
• The BUF_WMRK event flag will not participate in SRC_BUF interrupt generation in triggered mode (the BUF_WMRK flag is asserted after the buffer is triggered, but it will not signal an external interrupt as with the other buffer operating modes). If it is required to know when the trigger event has taken place, the host may use the SDCD or ORIENT interrupts, as appropriate, to indicate when the buffer is triggered. When the buffer is full, the SRC_BUF flag is set and an external interrupt is signaled on the INT1 or INT2 pins, if configured. SRC_SDCD_OT SDCD outside of thresholds condition event flag (copy of SDCD_INT_SRC1[OT_EA] flag) 0: SDCD outside of thresholds event is not detected (SDCD_INT_SRC1[OT_EA] = 0). 1: SDCD outside of thresholds event is detected (SDCD_INT_SRC1[OT_EA] = 1). The SRC_SDCD_OT event flag is cleared by reading the SDCD_INT_SRC1 register when SDCD_ CONFIG1[OT_ELE] = 1, otherwise this flag is cleared automatically by the function when the event condition becomes false. SRC_SDCD_WT SDCD within thresholds condition event flag (copy of SDCD_INT_SRC2[WT_EA] flag) 0: No SDCD within thresholds event has been detected (SDCD_INT_SRC2[WT_EA] = 0). 1: An SDCD within thresholds event has been detected (SDCD_INT_SRC2[WT_EA] = 1). The SRC_SDCD_WT event flag is cleared by reading the SDCD_INT_SRC2 register when SDCD_ CONFIG1[WT_ELE] = 1, otherwise the function clears this flag automatically when the event condition becomes false. SRC_ORIENT Orientation change event flag The SRC_ORIENT flag is asserted whenever the ORIENT_STATUS[NEW_ORIENT] bit is asserted and a change in orientation has been detected. Reading the ORIENT_STATUS register clears this event flag. 0: An orientation change event has not occurred 1: An orientation change event has occurred.

Table 22. INT_STATUS register (address 00h) bit description...continued

0: A WAKE-to-SLEEP or SLEEP-to-WAKE system operating mode transition has not occurred. 1: A WAKE-to-SLEEP or a SLEEP-to-WAKE system operating mode transition has occurred.

• A WAKE-to-SLEEP transition is observed when no configured interrupt event occurs for a time period (number of ODR periods) that equals the user-specified inactivity time limit programmed in the ASLP_COUNT_LSB and ASLP_COUNT_MSB registers. On expiry of configured time period with no user specified activity, the system transitions to the user-specified SLEEP power mode (SENS_CONFIG2[sleep_pm]) and ODR (or decimation and idle time settings when Flexible Performance mode is selected).
• A SLEEP-to-WAKE transition occurs when a configured interrupt event flag becomes active. The interrupt event flag transitions to the user-specified WAKE power mode (SENS_ CONFIG2[wake_pm]) and ODR (or decimation and idle time settings when Flexible Performance mode is selected). Notes:
• The SRC_ASLP event flag is cleared by reading the SYS_MODE register.
• The SRC_ASLP event flag is enabled when ASLP_COUNT ≥ 1 which also enables the Auto- WAKE/SLEEP function. The SRC_ASLP flag is only operational when INT_EN[ALSP_EN] = 1. SRC_BOOT System boot complete event flag 0: Boot sequence in process/not complete. 1: Boot sequence completed; FXLS8974CF is now ready to accept commands over the I2C or SPI interfaces. This flag is automatically set to 1 upon completion of the boot process and remains set until a POR, soft reset, or exit from Hibernate mode event occurs. When BT_MODE = GND: Boot interrupt is generated in INT1/MOT_DET pin by default. This event flag may be configured to generate an interrupt on either the INT1 or INT2 pin depending on the mapping selected in INT_PIN_SEL. When this event flag is enabled as an interrupt output, either the INT1 or INT2 (depending on the setting made in INT_PIN_SEL register) pin is pulsed once with a width of TBOOT1 µs when the boot process completes. When BT_MODE = VDD: The INT2/BOOT_OUT pin is pulsed once with a duration of TBOOT2 ms when the boot process completes. The pulse is active low (open-drain output); an external pull-up resistor is required. Notes:
• When BT_MODE = GND, after a POR or exiting Hibernate mode, the polarity of the BOOT pulse is default Active High because any I2C write to the SENS_CONFIG4[INT_POL] fails until the boot process has completed.
• After a Soft Reset, the INT_POL, INT_PP_OD, and INT_PIN_SEL register settings are not reset and maintain their previous values. As a result, an I2C or SPI write to the SENS_ CONFIG4[(INT_PP_OD and INT_POL bits)] and INT_PIN_SEL[BOOT_INT2] bits before the Soft Reset determines the logic polarity, output driver type, and INT1/2 pin mapping of the subsequent Boot pulse.
• It is not possible to observe the state of the SRC_BOOT bit at '0' over the I2C or SPI interfaces as read and write operations fails until the boot process has completed.

15.2 TEMP_OUT register (address 01h)

Table 23. TEMP_OUT register (address 01h) bit allocation register is updated on every ODR cycle.

15.3 VECM_LSB register (address 02h)

SENS_CONFIG2[LE_BE] and defaults to little-endian mode. Table 24. VECM_LSB register (address 02h) bit allocation Table 25. VECM_LSB register (address 02h) bit description

15.4 VECM_MSB register (address 03h)

SENS_CONFIG2[LE_BE] and defaults to little-endian mode.

Table 26. VECM_MSB register (address 03h) bit allocation Table 27. VECM_MSB register (address 03h) bit description

15.5 OUT_X_LSB, OUT_X_MSB, OUT_Y_LSB, OUT_Y_MSB, OUT_Z_LSB,

bytes to 3 bytes per XYZ sample read. defaults to little-endian mode. address, regardless of the setting made in SENS_CONFIG2[LE_BE]. of the data must be done explicitly, depending on the C compiler used.

• There is a ~40 µs delay between the ADC acquisitions of the accelerometer X,Y,Z, and temperature data. The temperature data is acquired first, followed by the X, Y, and Z axes acceleration data. All data is latched into the output registers at the same time instant, coincident with the SRC_DRDY event flag being asserted. Whenever any of the OUT_X/Y/Z registers is read the SRC_DRDY event flag is cleared.
• SX means sign extension, which is the logic level of the most significant bit of the 12-bit OUT_X/Y/Z register data, also known as OUT_X/Y/Z[11]. Objective data sheet Rev. 1 — 27 April 2021

Table 28. OUT_X_LSB and OUT_X_MSB register (addresses 04h to 05h) with SEN_CONFIG2[LE_BE] = 0 bit Table 29. OUT_Y_LSB and OUT_Y_MSB register (addresses 06h to 07h) with SEN_CONFIG2[LE_BE] = 0 bit Table 30. OUT_Z_LSB and OUT_Z_MSB register (addresses 08h to 09h) with SEN_CONFIG2[LE_BE] = 0 bit

Table 31. OUT_X_LSB and OUT_X_MSB register (addresses 04h to 05h) with SEN_CONFIG2[LE_BE] = 1 bit Table 32. OUT_Y_LSB and OUT_Y_MSB register (addresses 06h to 07h) with SEN_CONFIG2[LE_BE] = 1 bit Table 33. OUT_Z_LSB and OUT_Z_MSB register (addresses 08h to 09h) with SEN_CONFIG2[LE_BE] = 1 bit

15.6 BUF_STATUS register (address 0Bh)

disabled and this register always contains the value 00h.

shown in Table 34 and Table 35. Table 34. BUF_STATUS register (address 0Bh) bit allocation

1. The host must read out enough samples from the output buffer for BUF_

STATUS[BUF_CNT[5:0]] to go below the value set in BUF_CONFIG2[BUF_WMRK[5:0]].

1. The host must flush the buffer by setting BUF_CONFIG2[BUF_FLUSH] = 1.
2. The host must set BUF_CONFIG1[BUF_MODE[1:0]] = 00b to disable the buffer, which also

SENS_CONFIG2[F_READ] = 0), or 49 bytes when SENS_CONFIG2[F_READ] = 1.

1. At least one sample must be read in order to clear the BUF_OVF flag.
2. Flush the output buffer by setting BUF_CONFIG2[BUF_FLUSH] = 1.
3. Disable the output buffer by setting BUF_CONFIG1[BUF_MODE[1:0]] = 00b, which resets

BUF_STATUS[BUF_CNT[5:0]] to zero, but does not clear the buffer contents. Table 35. BUF_STATUS register (address 0Bh) bit description

15.7 BUF_X_LSB, BUF_X_MSB, BUF_Y_LSB, BUF_Y_MSB, BUF_Z_LSB,

selected. BUF_CONFIG1[BUF_TYPE] controls the read out mode. defaults to little-endian mode. on a per sample (per axis) basis. divide the value by 16) in order to obtain the correct scaling of the acceleration data. stored at the LSB address, regardless of the setting made in SENS_CONFIG2[LE_BE]. shortening the number of bytes to be read from 6 to 4, or from 3 to 2 when F_READ = 1. Table 36. BUF_X_LSB and BUF_X_MSB registers (addresses 0Ch, 0Dh) with SENS_CONFIG2[LE_BE] = 0 bit

Table 37. BUF_Y_LSB and BUF_Y_MSB registers (addresses 0Eh, 0Fh) with SENS_CONFIG2[LE_BE] = 0 bit Table 38. BUF_Z_LSB and BUF_Z_MSB registers (addresses 10h, 11h) with SENS_CONFIG2[LE_BE] = 0 bit Table 39. BUF_X_LSB and BUF_X_MSB registers (addresses 0Ch, 0Dh) with SENS_CONFIG2[LE_BE] = 1 bit

Table 40. BUF_Y_LSB and BUF_Y_MSB registers (addresses 0Eh, 0Fh) with SENS_CONFIG2[LE_BE] = 1 bit Table 41. BUF_Z_LSB and BUF_Z_MSB registers (addresses 10h, 11h) with SENS_CONFIG2[LE_BE] = 1 bit

15.8 PROD_REV register (address 12h)

Table 42. PROD_REV register (address 12h) bit allocation Product revision info, major product revision value with range 1 to 9 in BCD format. Product revision info, minor product revision value with range 0 to 9 in BCD format. Table 43. PROD_REV register (address 12h) bit description

15.9 WHO_AM_I register (address 13h)

programmed to 86h for FXLS8974CF. Table 44. WHO_AM_I register (address 13h) bit allocation

15.10 SYS_MODE register (address 14h)

status of the buffer gate error flag and the buffer gate count. Table 45. SYS_MODE register (address 14h) bit allocation 1: A buffer gate error was detected. remains asserted as long as the output buffer remains un-emptied.

1. Reading out the entire contents of the output buffer such that BUF _STATUS[BUF_CNT[5:0]]
2. Flushing (clearing) the output buffer contents by setting BUF_CONFIG2[BUF _FLUSH] = 1.
3. Disabling the output buffer by setting BUF _CONFIG1[BUF MODE[1:0]] = 00b, which clears
4. Transitioning FXLS8974CF from Standby to Active mode.

Table 46. SYS_MODE register (address 14h) bit description

BUF _GATE_ERR flag was asserted.

1. The host reads out the entire contents of the output buffer such that BUF
2. The host flushes (clears) the output buffer by setting BUF _CONFIG2[BUF _FLUSH] = 1.
3. Disable the output buffer by setting BUF CONFIG1[BUF _MODE[1:0]] = 00b, which also
4. Transitioning FXLS8974CF from Standby to Active mode. which also clears the buffer

• When external trigger mode is enabled (with SENS_CONFIG4[INT2_FUNC] = 1), while the device is waiting for a trigger event to occur, SYS_MODE[1:0] is set to 11b. When the trigger is received, SYS_MODE[1:0] is set to 01b while the measurement is being made, and then change back to 11b and remain there until the next trigger signal is received.
• When INT_EN[WAKE_OUT_EN] = 1, and SYS_MODE[1:0] = 01b (WAKE), the device outputs either a logic '1' or '0' on either the INT1 or INT2 pins, depending on the settings made in INT_ PIN_SEL[WAKE_OUT_INT2] and SENS_CONFIG4[INT_POL].
• When entering the WAKE, SLEEP, or EXT_TRIG modes, the internal debounce counters for the ORIENT, SDCD_WT, and SDCD_OT event functions are automatically reset.

Table 46. SYS_MODE register (address 14h) bit description...continued

15.11 SENS_CONFIG1 register (address 15h)

Table 47. SENS_CONFIG1 register (address 15h) bit allocation

active edge on the TBOOT1/2 pulse event signaled on the configured INTx pin.

• The I2C and SPI interface blocks are also reset to avoid corrupted data transactions.
• The reset sequence does not start until the host I2C controller issues the SP (stop) condition, or the SPI primary releases the SPI_CS_B pin.
• The host always reads back this bit as '0'.
• There is a delay of 300 μs to 500 μs between setting the RST bit and the commencement of the reset sequence. 6 to 5 ST_AXIS_SEL[1:0] Self-test axis selection This bit field selects the transducer axis to test using the Self-Test function. The ST_POL bit allows either positive or negative self-test displacements to be applied. The host system may use the self-test function to verify the functionality of both the transducer and signal measurement chain without the need to apply an external acceleration stimulus. Notes:
• The data output from the two axes that are not selected by ST_AXIS_SEL during the self-test sequence are not meaningful and should be ignored.
• NXP recommends minimizing the communication traffic on the device serial interface during the measurement phase in order to reduce the susceptibility of the self-test response signal to induced noise. NXP strongly recommends operating the self-test in interrupt mode. 00b: (default): Self-test function is disabled 01b: Self-test function is enabled for X-axis 10b: Self-test function is enabled for Y-axis 11b: Self-test function is enabled for Z-axis ST_POL Self-test displacement polarity 0 (default): Proof mass displacement for the selected axis is in the positive direction. 1: Proof mass displacement for the selected axis is in the negative direction. SPI_M SPI interface mode selection; selects between 3- and 4-wire operating modes for the SPI interface: 0 (default): 4-wire interface mode is selected 1: 3-wire interface mode is selected Notes:
• The state of this bit is only relevant when the SPI interface mode is selected (INTF_SEL = VDD).
• When INTF_SEL = VDD and SPI_M = 1, the SDA/SPI_MOSI pin becomes the bidirectional SPI_DATA pin; the SA0/MISO pin is unused and placed in a high-impedance state.
• 4-wire mode is selected by default after a POR/BOR event or when exiting Hibernate mode.
• If INTF_SEL = VDD and the SPI_MOSI and SPI_MISO lines are directly connected together on the PCB, 3-wire SPI mode is enabled regardless of the setting of this bit

Table 48. SENS_CONFIG1 register (address 15h) bit description

This bit selects between Standby mode and Active mode.

• When INT2_FUNC = 1, the Active bit becomes read only via the I2C or SPI interface as the INT2 pin logic state directly controls the device operating mode. The INT2_FUNC may only be enabled (set to 1) when ACTIVE = 0. Similarly, the ACTIVE bit may only be set if INT2_FUNC = 0. 0: FXLS8974CF is placed in Standby mode and draws the minimum amount of current on the VDD pin (IDD-STBY). Standby mode is the default mode after a POR or soft reset event. 1: FXLS8974CF is placed in Active mode and draws an IDD corresponding to the selected ODR in HPM, the selected ODR in LPM, or the user-selected decimation and idle time settings in FPM.

Table 48. SENS_CONFIG1 register (address 15h) bit description...continued

15.12 SENS_CONFIG2 register (address 16h)

Table 49. SENS_CONFIG2 register (address 16h) bit allocation and sets the ODR and decimation factor as per Table 52. WAKE_ODR[3:0] and set the ODR and decimation factor as per Table 53. Table 54 for the selectable decimation factors. the default LPM mode should be used. Table 50. SENS_CONFIG2 register (address 16h) bit description

and sets the ODR and decimation factor as per Table 52. SLEEP_ODR[3:0] and set the ODR and decimation factor as per Table 53. measurement idle time programmed in the SLEEP_IDLE_MSB and SLEEP_IDLE_LSB registers. See Table 54 for the selectable decimation factors. the default LPM mode should be used. and the MSBs (nibbles) are right-justified. and the LSBs (nibbles) are left justified. 0 (default): TEMP_OUT register content is not included in auto-increment address range. 1: TEMP_OUT register content is included in auto-increment address range. When this bit is set, the output data format is limited to the most significant byte of the 12-bit sample. data when the F_READ bit is set. Table 50. SENS_CONFIG2 register (address 16h) bit description...continued

15.13 SENS_CONFIG3 register (address 17h)

WAKE and SLEEP modes in Flexible Power Mode.

• In motion detection mode with BT_MODE=VDD, use of HPM or FPM mode is not advised. Only the default LPM mode should be used.
• When BT_MODE=VDD, maximum recommended ODR is 100 Hz. When the data ready interrupt is enabled, the interrupt line (INT1) will pulse low for TPULSE-MOT seconds (5 ms typ) for every ODR period. Therefore, for higher ODRs, the host does not observe DRDY interrupt pulse at every ODR period. Objective data sheet Rev. 1 — 27 April 2021

Table 51. SENS_CONFIG3 register (address 17h) bit allocation time parameter determines the effective ODR. using the SLEEP_DEC[3:0] and the SLEEP_IDLE[11:0] values. depending on current operating mode. After this initial delay, all subsequent data samples are made available at the ODR rate.

• When the device transitions from WAKE to SLEEP or from SLEEP to WAKE modes there is a 500 µs (nominal) delay between the last acquisition at the WAKE/SLEEP mode ODR and the first acquisition at the SLEEP/WAKE mode ODR.
• The ODR may only be changed in Standby mode, with SENS_CONFIG1[ACTIVE] = 0 and SENS_CONFIG4[INT2_FUNC] = 0. ODR[3] ODR[2] ODR[1] ODR[0] ODR Selection (Hz) Decimation selection (samples) Noise RMS (mg)[1][2] IDD (µA) 0 0 0 0 3200 1 12.39 150 0 0 0 1 1600 1 11.77 75 0 0 1 0 800 1 11.19 38

Table 52. WAKE and SLEEP low-power mode ODR and decimation settings

Table 52. WAKE and SLEEP low-power mode ODR and decimation settings ...continued [1] Values are for ±2 g FSR only. [2] Based on post board mount characterization data. Tested on a mechanically isolated granite table to provide isolation from environmental vibration. Table 53. WAKE and SLEEP High Performance mode ODR and decimation settings

Table 53. WAKE and SLEEP High Performance mode ODR and decimation settings...continued [1] Values are for ±2 g FSR only. [2] Based on post board mount characterization data. Tested on a mechanically isolated granite table to provide isolation from environmental vibration. Table 54. WAKE and SLEEP decimation settings in Flexible Power mode

15.14 SENS_CONFIG4 register (address 18h)

Table 55. SENS_CONFIG4 register (address 18h) bit allocation

External trigger function acquisition mode. the setting made in BUF_CONFIG1[BUF_MODE[1:0]]. . buffer depending on the setting made in BUF_CONFIG1[BUF_MODE[1:0]].

• The EXT_TRIG_M setting only applies when INT2_FUNC = 1.
• The SRC_DRDY event flag is asserted after the specified number of measurements have completed and the final decimated output result is available. Note that the SRC_DRDY flag is only asserted when BUF_CONFIG1[BUF_MODE[1:0]] = 00b
• In LPM, this bit has no effect as the decimation factor is fixed at 1. WAKE_SDCD_WT SDCD within thresholds event Auto-WAKE/SLEEP transition source enable 0 (default): SDCD within thresholds event is not used to prevent entry into/trigger an exit from SLEEP mode. 1: SDCD within thresholds event is used to prevent entry into/trigger an exit from SLEEP mode. WAKE_SDCD_OT SDCD outside of thresholds event Auto-WAKE/SLEEP transition source enable 0 (default): SDCD outside of thresholds event is not used to prevent entry into/trigger an exit from SLEEP mode. 1: SDCD outside of thresholds event is used to prevent entry into/trigger an exit from SLEEP mode. WAKE_ORIENT Orientation change event Auto-WAKE/SLEEP transition source enable 0 (default): Orientation change condition is not used as an event to prevent entry into /trigger an exit from SLEEP mode. 1: Orientation change condition is used as an event to prevent entry into/trigger an exit from SLEEP mode. DRDY_PUL Pulse generation option for DRDY event 0 (default): A SRC_DRDY event is output on the INTx pin as an active high or active low signal depending on the polarity setting made in INT_POL. The INTx pin remains asserted until the host reads any of the OUT_X/Y/Z registers. 1: A 32 μs (nominal) duration pulse is output on the configured INTx pin once per ODR cycle. The output pulse is either positive or negative, depending on the INT_POL setting. Notes:
• The pulsed output signal is OR'd with all of the other interrupt events assigned to the INTx pin.
• In Motion Detection mode (BT_MODE = VDD), the state of this bit is ignored and has no effect on device operation.

Table 56. SENS_CONFIG4 register (address 18h) bit description

selectively routed to this output pin using the INT_PIN_SEL register. MCU timer output pin. When this function is enabled, it is reflected in the SYS_MODE register.

• When the EXT_TRIG function is enabled, any bits set to '1' in the INT_PIN_SEL register (mapping an event flag to the INT2 output pin) are ignored as the pin becomes a dedicated high-impedance input pin for the external trigger function.
• The INT2_FUNC bit setting is ignored when BT_MODE = VDD as the external trigger function is not available in this mode. INT_PP_OD INT1 and INT2 pins output driver selection 0 (default): INTx output pin driver is push-pull type. 1: INTx output pin driver is open-drain/open-source type. An external pull-up/pull-down resistor is required. Notes:
• If a user operation sets INT_PP_OD before issuing a soft reset command, the setting is maintained through the reset sequence (only lost when VDD supply is removed or Hibernate mode is enabled).
• The INT_PP_OD bit setting is ignored when BT_MODE = VDD as the INT1/MOT_DET and INT2/ BOOT_OUT output driver type is fixed to open-drain. INT_POL Interrupt logic polarity on INT1 and INT2 pins Selects the polarity of the interrupt output signal on the INT1 and INT2 pins. 0: Active low: interrupt events are signaled with a logical '0' level. If DRDY_PUL=1, a SRC_DRDY event pulse is negative going. The inactive state of the INTx pins is logic '1' (VDD). 1 (default): Active high: interrupt events are signaled with a logical '1' level. If DRDY_PUL=1, a SRC_ DRDY event pulse is positive going. The inactive state of the INTx pins is logic '0' (GND). Notes:
• If a user operation sets INT_POL before issuing a soft reset command, the setting is maintained through the reset sequence (only lost if VDD supply is removed or Hibernate mode is enabled).
• The INT_POL bit setting is ignored when BT_MODE = VDD as the INT1/MOT_DET and INT2/ BOOT_OUT interrupt logic polarity is fixed at active low (external pull-up resistors are required).

Table 56. SENS_CONFIG4 register (address 18h) bit description...continued [1] In order to acquire all the measurements specified by the decimation setting, only one trigger event is needed. Table 57. INTx pin behavior as a function of INT_PP_OD and INT_POL bit settings (valid only when BT_MODE =

[1] High-Z means high impedance condition, with the state of the INTx pin defined by the external pull-up or pull-down resistor. Table 58. INTx pin behavior as a function of INT_PP_OD and INT_POL bit settings (valid only when BT_MODE =

15.15 SENS_CONFIG5 register (address 19h)

Table 59. SENS_CONFIG5 register (address 19h) bit allocation VECM_MSB registers are not included in auto-increment address range. registers are included in auto-increment address range. and non-buffered modes (default). 1: X-axis measurement is excluded from the auto-increment address range. and non-buffered modes (default). 1: Y-axis measurement is excluded from the auto-increment address range. Table 60. SENS_CONFIG5 register (address 19h) bit description

and non-buffered modes (default). 1: Z-axis measurement is excluded from the auto-increment address range. 1: Commands device to enter Hibernate mode; all RAM register contents are lost.

• When BT_MODE = GND: When Hibernate Mode is selected, FXLS8974CF is completely shut down (similar to removing the VDD supply), with all register contents lost. To exit Hibernate Mode, a positive or negative going edge must be applied to the SPI_CS_B/WAKE_UP pin (logic level must toggle from the state applied at the time this bit was set). The host must then wait TBOOT1 ms for the part to re-enter Standby mode before attempting communications over the I2C or SPI interfaces.
• When BT_MODE = VDD: Hibernate mode is automatically entered/exited based on the level input to the MOT_DET pin. The part directly enters Active mode with the preconfigured motion detection settings when MOT_DET is pulled high. The host must wait TBOOT2 ms for the boot process to complete and the motion detection process to begin. When MOT_DET is brought low, the part automatically enters Hibernate mode to conserve power.

Table 60. SENS_CONFIG5 register (address 19h) bit description...continued

15.16 WAKE_IDLE_LSB register (address 1Ah)

SENS_CONFIG2[WAKE_PM[1:0]] = 1xb. Table 61. WAKE_IDLE_LSB register (address 1Ah) bit allocation

15.17 WAKE_IDLE_MSB register (address 1Bh)

meaningful when SENS_CONFIG2[WAKE_PM[1:0]] = 1xb.

Table 62. WAKE_IDLE_MSB register (address 1Bh) bit allocation

15.18 SLEEP_IDLE_LSB register (address 1Ch)

Table 63. SLEEP_IDLE_LSB register (address 1Ch) bit allocation

15.19 SLEEP_IDLE_MSB register (address 1Dh)

useful only when SENS_CONFIG2[SLEEP_PM[1:0]] = 1xb. Table 64. SLEEP_IDLE_MSB register (address 1Dh) bit allocation

15.20 ASLP_COUNT_LSB, ASLP_COUNT_MSB registers (addresses 1Eh to

mode when the internal counter reaches the ASLP_COUNT value.

the corresponding Interrupt event sources. Table 65. ASLP_COUNT_LSB register (address 1Eh) bit allocation ODR determines the counter period. Table 66. ASLP_COUNT_LSB register (address 1Eh) bit description Table 67. ASLP_COUNT_MSB register (address 1Fh) bit allocation mode ODR determines the counter period. Table 68. ASLP_COUNT_MSB register (address 1Fh) bit description Table 69. ASLP_COUNT timer period

Table 69. ASLP_COUNT timer period...continued Table 70. Auto-WAKE/SLEEP Interrupt Event Sources mode ODRs from being mixed within the buffer.

15.21 INT_EN register (address 20h)

• When BT_MODE = VDD, the INT1/MOT_DET pin signals any mapped (and enabled) interrupts with a TPULSE-MOT ms active low pulse (open-drain output with external pull- up).
• Any enabled interrupt is signaled with a TPULSE-MOT ms pulse at the ODR rate until the respective interrupt source flag is cleared. Objective data sheet Rev. 1 — 27 April 2021

• The INT2/BOOT_OUT pin only signals the boot process complete interrupt, signaled by a TPULSE-BOOT2 ms active low pulse (open-drain with external pull-up). Any other interrupt sources mapped to the INT2/BOOT_OUT pin are ignored. Bit 7 6 5 4 3 2 1 0 Name DRDY_EN BUF_EN SDCD_ OT_EN SDCD_ WT_EN ORIENT_ EN ASLP_EN BOOT_ DIS WAKE_ OUT_EN Reset (BT_MODE = GND) 0 0 0 0 0 0 0 0 Reset (BT_MODE = VDD) 0 0 1 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 71. INT_EN register (address 20h) bit allocation 0 (default): Interrupt is disabled. setting made in INT_PIN_SEL. completion and therefore may not span for entire TPULSE-MOTs.

0 Interrupt is not routed to the INTx output pins (default)

0 (default): Interrupt is disabled. 0 (default): Interrupt is disabled. 0 (default): Interrupt is disabled. setting made in INT_PIN_SEL. 0 (default): Interrupt is disabled. setting made in INT_PIN_SEL. Table 72. INT_EN register (address 20h) bit description

determined by the setting made in SENS_CONFIG4[INT_POL]. 1: Interrupt is disabled and not routed to the INTx output pins. duration of TPULSE-BOOT1 µs when the BOOT process completes. BOOT2 ms during the BOOT sequence. Hibernate mode is entered; this setting is, however, maintained across a soft reset operation. 0 (default): The device does not signal the WAKE operating mode on the INTx output pin. EXT_TRIG mode, the selected interrupt pin assumes the opposite logic state. the WAKE_OUT function in order to prevent unintended operation of the load switch or LDO. Table 72. INT_EN register (address 20h) bit description...continued

15.22 INT_PIN_SEL register (address 21h)

• When the INT2 pin is configured for the external trigger function, for example, when SENS_CONFIG4[INT2_FUNC] = 1, a logic '1' value in any of these bit fields is ignored.
• When BT_MODE = VDD, the only interrupt that may be mapped to the INT2/ BOOT_OUT pin is the SRC_BOOT interrupt; setting any of the other bits in this register to '1' effectively unroutes the respective interrupt source from both the INT1 and INT2 pins. Bit 7 6 5 4 3 2 1 0 Name DRDY_ INT2 BUF_INT2 SDCD_ OT_INT2 SDCD_ WT_INT2 ORIENT_ INT2 ASLP_INT2 BOOT_ INT2 WAKE_ OUT_INT2 Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 73. INT_PIN_SEL register (address 21h) bit allocation

0: If data-ready interrupt routing is enabled, the interrupt signal is routed to INT1 pin. 1: If data-ready interrupt routing is enabled, the interrupt signal is routed to INT2 pin. 1: If output buffer interrupt routing is enabled, the interrupt signal is routed to INT2 pin. 0: If ORIENT event interrupt routing is enabled, the interrupt signal is routed to INT1 pin. 1: If ORIENT event interrupt routing is enabled, the interrupt signal is routed to INT2 pin. 0: If Auto-WAKE/SLEEP event interrupt routing is enabled, the interrupt signal is routed to INT1 pin. 1: If Auto-WAKE/SLEEP event interrupt routing is enabled, the interrupt signal is routed to INT2 pin. through the reset sequence (the setting is lost if VDD supply is removed). 0: If BOOT event interrupt routing is enabled, the interrupt signal is routed to INT1 pin. 1: If BOOT event interrupt routing is enabled, the interrupt signal is routed to INT2 pin. INT2/BOOT_OUT pin (fixed setting). Table 74. INT_PIN_SEL register (address 21h) bit description

15.23 OFF_X, OFF_Y, OFF_Z registers (addresses 22h to 24h)

offset adjustment range of –128 to 127.

in an effective X-axis offset of 16 LSB * 2 * 1.95 mg/LSB = 62.4 mg. Table 75. OFF_X register (addresses 22h) bit allocation Table 76. OFF_Y register (addresses 23h) bit allocation Table 77. OFF_Z register (addresses 24h) bit allocation

15.24 BUF_CONFIG1 register (address 26h)

Table 78. BUF_CONFIG1 register (address 26h) bit allocation In FIFO mode, the oldest sample data is read out first, followed by the more recent sample data. 1: First In Last Out (LIFO). In LIFO mode, the newest data sample is read out first, followed by the older sample data. CONFIG1[ACTIVE] and SENS_CONFIG4[INT2_FUNC] bits. Table 79. BUF_CONFIG1 register (address 26h) bit description

sample data is replaced with new data when the buffer becomes full and a new sample arrives. 10: Stop Mode: buffer stops accepting new samples when full. CONFIG2[BUF_WMRK[5:0]] setting. SDCD_OT, and TRIG_ORIENT bits. data from two different ODRs rates becoming mixed in the output buffer. since the BUF_GATE_ERR flag was asserted. emptied of flushed by the host application.

• The BUF_GATE_ERR flag remains asserted as long as the buffer remains un-emptied.
• When triggered buffer mode (BUF_MODE = 11b) is selected and ASLP_COUNT ≥ 1, the BUF_GATE setting is ignored.
• The BUF_GATE bit in 1: Trigger source is enabled, when set, holds the last data set stored in the buffer before transitioning to the SLEEP or WAKE modes. After the buffer is flushed, FXLS8974CF will start accepting new sample data into the buffer at the current operating mode ODR. TRIG_SDCD_WT SDCD within thresholds event buffer trigger enable: 0: Trigger source is disabled (default). 1: Trigger source is enabled TRIG_SDCD_OT SDCD outside of thresholds event buffer trigger enable: 0: Trigger source is disabled (default). 1: Trigger source is enabled TRIG_ORIENT Orientation change event buffer trigger enable: 0: Trigger source is disabled (default). 1: Trigger source is enabled

Table 79. BUF_CONFIG1 register (address 26h) bit description...continued

WAKE by setting BUF_CONFIG1[BUF_GATE] = 1. when the host reads out all the content.

1. When BUF_MODE = 11b, ASLP_COUNT ≥ 1, and the ACTIVE bit is set,

event occurs (in stream mode).

1. After the trigger event, FXLS8974CF enters WAKE mode and remain there regardless

ASLP_COUNT WAKE ODR periods) before a second set of data can be collected.

1. The BUF_CONFIG1[BUF_GATE] setting is ignored and has no effect. The buffer
2. The interrupt events that prevent FXLS8974CF from entering SLEEP mode also

15.25 BUF_CONFIG2 register (address 27h)

Table 80. BUF_CONFIG2 register (address 27h) bit allocation MODE[BUF_GATE_ERR] and SYS_MODE[BUF_GATE_CNT[4:0]] fields are also cleared. logic high state through the I2C or SPI interfaces. Table 81. BUF_CONFIG2 register (address 27h) bit description

1: (BUF_WMRK | BUF_OVF) event flag condition is used by the auto-WAKE/SLEEP function. (Stream mode) or 10b (Stop mode). This field sets the minimum number of buffer samples required to trigger a watermark interrupt. STATUS[BUF_CNT] ≥ BUF_CONFIG2[BUF_WMRK[5:0]]. Setting BUF_WMRK = 0 disables the buffer watermark event flag generation. operating mode when BUF_CONFIG1[BUF_MODE] = 11b. Table 81. BUF_CONFIG2 register (address 27h) bit description...continued

15.26 ORIENT_STATUS register (address 28h)

left, landscape right, back, and front orientation states, see Section 6.3. Table 82. ORIENT_STATUS register (address 28h) bit allocation

• The NEW_ORIENT bit is set to 1 after the first orientation detection after a Standby to Active transition and whenever a change in LO, BAFRO, or LAPO status occurs. The NEW_ORIENT bit is cleared anytime the ORIENT_STATUS register is read.
• The Auto-WAKE/SLEEP timer is reset (cleared) on the rising edge of this flag.

Table 83. ORIENT_STATUS register (address 28h) bit description

0: Lockout condition has not been detected. 1: Z-tilt lockout trip angle has been exceeded. Lockout condition has been detected. 00: Portrait up: The device is oriented vertically in the upward direction. 01: Portrait down: The device is oriented vertically in the downward direction. 10: Landscape right: The device is oriented horizontally to the right. 11: Landscape left: The device is oriented horizontally to the left. 0: Front: The device is in the front-facing orientation. 1: Back: The device is in the back-facing orientation. Table 83. ORIENT_STATUS register (address 28h) bit description...continued

• The BAFRO and LAPO fields are reset to 0 after a POR or soft reset event. These bits are also automatically cleared after a transition from STANDBY to ACTIVE or STANDBY to EXT_TRIG modes.
• The current orientation is locked if the absolute value of the acceleration experienced on any of the three axes is greater than 1.25 g.

15.27 ORIENT_CONFIG register (address 29h)

the orientation transition debounce counter. Table 84. ORIENT_CONFIG register (address 29h) bit allocation Table 85. ORIENT_CONFIG register (address 29h) bit description

0 (default): Orientation detection function is disabled. 1: Orientation detection function is enabled. Table 85. ORIENT_CONFIG register (address 29h) bit description...continued

15.28 ORIENT_DBCOUNT register (address 2Ah)

internal orientation debounce counter. Table 86. ORIENT_DBCOUNT register (address 2Ah) bit allocation STATUS[NEW_ORIENT] event flag. ORIENT_CONFIG[ORIENT_DBCNTM] controls the counter behavior. held at the current value (frozen). Table 87. ORIENT_DBCOUNT register (address 2Ah) bit description

15.29 ORIENT_BF_ZCOMP register (address 2Bh)

Table 88. ORIENT_BF_ZCOMP register (address 2Bh) bit allocation

Default: 01b; Step size is ~5°/ LSB. Table 89. ORIENT_BF_ZCOMP register (address 2Bh) bit description Table 90. ORIENT_ZLOCK lockout angles

00 Z < 80° or Z > 280° Z > 100° and Z < 260°

01 Z < 75° or Z > 285° Z > 105° and Z < 255°

10 Z < 70° or Z > 290° Z > 110° and Z < 250°

11 Z < 65° or Z > 295° Z > 115° and Z < 245°

Table 91. ORIENT Back/Front orientation transition angle definitions

15.30 ORIENT_THS register (address 2Ch)

Table 92. ORIENT_THS register (address 2Ch) bit allocation

Table 93. Orientation change trip angles look-up table

Table 94. Resultant trip angle (threshold angle ± hysteresis angle) Table 95. Orientation change ideal orientation angle definitions

15.31 Sensor Data Change Detection (SDCD) registers

Figure 17. SDCD Function Block Diagram

15.31.1 SDCD_INT_SRC1 register (address 2Dh)

Table 96. SDCD_INT_SRC1 register (address 2Dh) bit allocation

defined by SDCD_UTHS and SDCD_LTHS registers.

• The axes selected for participation in the over thresholds condition evaluation are enabled via the X/Y/Z_OT_EN bits in the SDCD_CONFIG1 register. If none of the X/Y/Z_OT_EN bits are set, then the SDCD_OT function is effectively disabled.
• When SENS_CONFIG4[WAKE_SDCD_OT] = 1, the Auto-WAKE/SLEEP timer is reset on every ODR cycle when the OT_EA flag is asserted (set), which prevents the device from transitioning into SLEEP mode. This flag must be de-asserted (cleared) in order for FXLS8974CF to transition to SLEEP mode. X_OT_EF X-axis data or delta-outside-of-upper-and-lower-thresholds event flag; enabled if X_OT_EN = 1 0: X-axis data or delta is < SDCD_UTHS value and > SDCD_LTHS value. 1: X-axis data or delta is either ≥ SDCD_UTHS value or ≤ SDCD_LTHS value; the X_OT_POL flag may be used to determine which threshold has been met or crossed. X_OT_POL[1][2] X-axis outside-of-thresholds polarity flag 0: X-axis data or delta was ≤ lower threshold value 1: X-axis data or delta was ≥ upper threshold value Y_OT_EF Y-axis data or delta-outside-of-upper-and-lower-thresholds event flag; enabled if Y_OT_EN = 1 0: Y-axis data or delta is < SDCD_UTHS value and > SDCD_LTHS value. 1: Y-axis data or delta is either ≥ SDCD_UTHS value or ≤ SDCD_LTHS value; the Y_OT_POL flag may be used to determine which threshold has been met or crossed. Y_OT_POL[1][2] Y-axis outside-of-thresholds polarity flag 0: Y-axis data or delta was equal to or below lower threshold value 1: Y-axis data or delta was equal to or above upper threshold value Z_OT_EF[1][2] Z-axis data or delta-outside-of-upper-and-lower-thresholds event flag; enabled if Z_OT_EN = 1 0: Z-axis data or delta is < SDCD_UTHS value and > SDCD_LTHS value 1: Z-axis data or delta is either ≥ SDCD_UTHS value or ≤ SDCD_LTHS value; the Z_OT_POL flag may be used to determine which threshold has been met or crossed Z_OT_POL Z-axis outside-of-thresholds polarity flag 0: Z-axis data or delta was equal to or below lower threshold value 1: Z-axis data or delta was equal to or above upper threshold value

Table 97. SDCD_INT_SRC1 register (address 2Dh) bit description [2] When SDCD_CONFIG1[OT_ELE] = 0, these flags are updated when X/Y/Z_OT_EF = 1 and the SDCD_OT_DBCNT value is reached.

15.31.2 SDCD_INT_SRC2 register (address 2Eh)

Table 98. SDCD_INT_SRC2 register (address 2Eh) bit allocation is true for a number of ODR cycles ≥ SDCD_WT_DBCNT.

• The axes selected for participation in the within thresholds condition evaluation are enabled via the X/Y/Z_WT_EN bits in the SDCD_CONFIG1 register. The logic mode for the function is set in the SDCD_CONFIG2 register. If none of the X/Y/Z_WT_EN bits are set then the SDCD_WT function is effectively disabled.
• When SENS_CONFIG4[WAKE_SDCD_WT] = 1, the Auto-WAKE/SLEEP timer is reset on every ODR cycle when the WT_EA flag is asserted (set), which prevents the device from transitioning into SLEEP mode. This flag must be de-asserted (cleared) in order for FXLS8974CF to transition to SLEEP mode. X_WT_EF X-axis data or delta inside of upper and lower thresholds event flag; This flag is only valid if X_WT_ EN = 1: 0: X-axis data or delta is ≥ SDCD_UTHS value or ≤ SDCD_LTHS value. 1: X-axis data or delta is < SDCD_UTHS and > SDCD_LTHS value. Notes:
• The SDCD_CONFIG1[WT_ELE] bit determines the behavior of this bit. If WT_ELE = 1, the flag is latched when WT_EA goes high, and remains set until it is cleared by reading the SDCD_ INT_SRC2 register. If the host wishes to know the state of this event flag, it must be read prior to reading the SDCD_INT_SRC2 register.
• If WT_ELE = 0, the X/Y/Z_WT_EF flags are updated if WT_EA = 1 and the SDCD_WT_DBCNT value is reached. If WT_ELE = 0, the X/Y/Z_WT_EF flags are updated even if WT_EA = 0 when the SDCD_WT_DBCNT value is set to 0. Y_WT_EF Y-axis data or delta inside of upper and lower thresholds event flag; This flag is only valid if Y_WT_ EN = 1: 0: Y-axis data or delta is ≥ SDCD_UTHS value or ≤ SDCD_LTHS value. 1: Y-axis data or delta is < SDCD_UTHS and > SDCD_LTHS value. Notes:
• The SDCD_CONFIG1[WT_ELE] bit determines the behavior of this bit. If WT_ELE = 1, the flag is latched when WT_EA goes high, and remains set until it is cleared by reading the SDCD_ INT_SRC2 register. If the host wishes to know the state of this event flag, it must be read prior to reading the SDCD_INT_SRC2 register.
• If WT_ELE = 0, the X/Y/Z_WT_EF flags are updated if WT_EA = 1 and the SDCD_WT_DBCNT value is reached. If WT_ELE = 0, the X/Y/Z_WT_EF flags are updated even if WT_EA = 0 when the SDCD_WT_DBCNT value is set to 0.

Table 99. SDCD_INT_SRC2 register (address 2Eh) bit description

0: Z-axis data or delta is ≥ SDCD_UTHS value or ≤ SDCD_LTHS value. 1: Z-axis data or delta is < SDCD_UTHS and > SDCD_LTHS value.

• The SDCD_CONFIG1[WT_ELE] bit determines the behavior of this bit. If WT_ELE = 1, the flag is latched when WT_EA goes high, and remains set until it is cleared by reading the SDCD_ INT_SRC2 register. If the host wishes to know the state of this event flag, it must be read prior to reading the SDCD_INT_SRC2 register.
• If WT_ELE = 0, the X/Y/Z_WT_EF flags are updated if WT_EA = 1 and the SDCD_WT_DBCNT value is reached. If WT_ELE = 0, the X/Y/Z_WT_EF flags are updated even if WT_EA = 0 when the SDCD_WT_DBCNT value is set to 0.

Table 99. SDCD_INT_SRC2 register (address 2Eh) bit description...continued

15.31.3 SDCD_CONFIG1 register (address 2Fh)

Table 100. SDCD_CONFIG1 register (address 2Fh) bit allocation 0 (default): Outside of thresholds event flag latching is disabled. 1: Outside of thresholds event flag latching is enabled. INT_SRC1 if the event condition becomes false before the read occurs. 0 (default): Within thresholds event flag latching is disabled. 1: Within thresholds event flag latching is enabled. 0: X-axis data or delta is not used in the outside of thresholds condition evaluation. 1: X-axis data or delta is used in the outside of thresholds condition evaluation. Table 101. SDCD_CONFIG1 register (address 2Fh) bit description

0: Y-axis data or delta is not used in the outside of thresholds condition evaluation. 1: Y-axis data or delta is used in the outside of thresholds condition evaluation. 0: Z-axis data or delta is not used in the outside of thresholds condition evaluation. 1: Z-axis data or delta is used in the outside of thresholds condition evaluation. 0: X-axis data or delta is not used in the within thresholds condition evaluation. 1: X-axis data or delta is used in the within thresholds condition evaluation. 0: Y-axis data or delta is not used in the within thresholds condition evaluation. 1: Y-axis data or delta is used in the within thresholds condition evaluation. 0: Z-axis data or delta is not used in the within thresholds condition evaluation. 1: Z-axis data or delta is used in the within thresholds condition evaluation. Table 101. SDCD_CONFIG1 register (address 2Fh) bit description...continued

15.31.4 SDCD_CONFIG2 register (address 30h)

Table 102. SDCD_CONFIG2 register (address 30h) bit allocation clocks and power for the function are turned off. settings made in REF_UPDM[1:0]. Table 103. SDCD_CONFIG2 register (address 30h) bit description

reenabled, or asynchronously when the host sets the REF_UPD bit. detection with Data(n) to Data(n–1) always used as the input to the window comparator. function operate in absolute comparison mode. 1 consecutive ODR periods before the next event detection cycle can begin. ODR periods before the next event detection cycle can begin. 0 (default): Function uses the logical AND of the enabled axes. 1: Function uses the logical OR of the enabled axes. 0 (default): Function uses X, Y, Z acceleration data for the window comparison. other SDCD channels are disabled and ignored by the function. operate correctly when MODE is set to 1. 0: No reference update pending or reference update has completed. 1: Triggers a synchronous update of the internal X/Y/Z reference registers. delayed by up to 1 ODR period after this bit is set. See Figure 18 for further details.

• This bit is self-cleared after the REF_X/Y/Z registers are updated. The host may not be able to observe a value of '1' as the operation can complete before the next I2C or SPI read cycle occurs.
• This bit can be written at any time in either Active or Standby mode.

Table 103. SDCD_CONFIG2 register (address 30h) bit description...continued

Figure 18. SDCD REF_UPD timing diagram

15.31.5 SDCD_OT_DBCNT register (address 31h)

to the effective ODR period (measurement + idle time) in FPM. SDCD outside-of-threshold function event condition as true. change resets the internal counter. Table 104. SDCD_OT_DBCNT register (address 31h) bit allocation effective ODR period in FPM). Table 105. SDCD_OT_DBCNT register (address 31h) bit description

15.31.6 SDCD_WT_DBCNT register (address 32h)

Debounce count threshold register for SDCD within-thresholds condition event detection. to the effective ODR period (measurement + idle time) in FPM.

SDCD within-threshold condition as true. SLEEP mode change resets the internal counter. Table 106. SDCD_WT_DBCNT register (address 32h) bit allocation same as the selected ODR period (or effective ODR period in FPM). Table 107. SDCD_WT_DBCNT register (address 32h) bit description

15.31.7 SDCD_LTHS_LSB register (address 33h)

Section 9 for the sensitivity values corresponding to each of the selectable FSRs. Table 108. SDCD_LTHS_LSB register (address 33h) bit allocation LSB of the signed 12-bit 2's complement lower threshold value. Table 109. SDCD_LTHS_LSB register (address 33h) bit description

15.31.8 SDCD_LTHS_MSB register (address 34h)

Section 9 for the sensitivity values corresponding to each of the selectable FSRs. Table 110. SDCD_LTHS_MSB register (address 34h) bit allocation Table 111. SDCD_LTHS_MSB register (address 34h) bit description

15.31.9 SDCD_UTHS_LSB register (address 35h)

the sensitivity values corresponding to each of the selectable FSRs. Table 112. SDCD_UTHS_LSB register (address 35h) bit allocation Table 113. SDCD_UTHS_LSB register (address 35h) bit description

15.31.10 SDCD_UTHS_MSB register (address 36h)

Section 9 for the sensitivity values corresponding to each of the selectable FSRs. Table 114. SDCD_UTHS_MSB register (address 36h) bit allocation Table 115. SDCD_UTHS_MSB register (address 36h) bit description

15.32 SELF_TEST_CONFIG1 register (address 37h)

Table 116. SELF_TEST_CONFIG1 register (address 37h) bit allocation The value contained in ST_IDLE determines the Self-Test Idle phase duration per Equation 3. Table 117. SELF_TEST_CONFIG1 register (address 37h) bit description

15.33 SELF_TEST_CONFIG2 register (address 38h)

Table 118. SELF_TEST_CONFIG2 register (address 38h) bit allocation

This bit field selects the Self-Test measurement phase decimation factor. The decimation selection ranges from 1 to 4096 as shown in Table 120. Table 119. SELF_TEST_CONFIG2 register (address 38h) bit description Table 120. Self-Test measurement phase decimation settings

• During the self-test sequence, the accelerometer measurement period in μs (for each axis and each direction) is given by Equation 4. (4)
• The user-selected ODR and power mode settings are ignored during self-test operation. The user-selected settings for ODR and power mode are applied after self- test is disengaged, for example, SENSCONFIG1[...]ST_AXIS_SEL[1:0] = 00b. Objective data sheet Rev. 1 — 27 April 2021

16.1 System connections

Figure 24 show the recommended circuit connections.

16.2 Typical application circuits

requirements of the application. Figure 19. Typical Application Circuit #1 – I2C mode

• Resistors R1 and R2 are not needed if the interrupt output driver type is configured for push-pull operation (default).
• If either the INT1 or INT2 pins are not used in the application, leave them unconnected.
• The required pull-up resistor values for R3 and R4 are dependent on several factors including the I2C clock frequency, bus pull-up voltage, and the total parasitic trace + device capacitances. A suggested starting point is 4.7 kΩ for Standard and Fast modes.
• The external trigger function can be used to initiate a single shot measurement of the XYZ acceleration and temperature data. This mode is useful for synchronizing measurements with an external system or for creating user-specific ODRs. The measurement is triggered on the rising edge of the EXT_TRIG signal. aaa-040830 0.1 µF R1 R2 VDD VDD VDD BT_MODE GND INTF_SEL INT1/MOT_DET SPI_CS_B/WAKE_UP INT2/EXT_TRIG/BOOT_OUT INT1 WAKE_UP INT2/EXT_TRIG SA0/SPI_MISO MOSI MISO SCLK SDA/SPI_MOSI/SPI_DATA SCL/SCLK 1.0 µF

Figure 20. Typical Application Circuit #2 – SPI 4-wire mode

Figure 24. Typical Application Circuit #6 - Motion detection mode (with SPI 3-wire interface, software enabled)

• External resistor R2 is not needed if the BOOT_OUT and MOT_DET pins are tied together (wired AND configuration).
• A suggested pull-up resistance range is 1 MΩ to 2.5 MΩ for both R1 and R2 to minimize the power dissipated in the resistor when the line is pulsed low. When BT_MODE is set to VDD (enabling motion detection mode), both the MOT_DET and BOOT_OUT pins become open-drain output driver types. MOT_DET also functions as a CMOS input and is used by the host system to power-manage FXLS8974CF.
• When BT_MODE = VDD, the default motion detection parameters are automatically loaded into the device after a POR/BOR event occurs; no configuration via I2C or SPI is needed if the default parameters are used in the application.
• See Section 13.2 and Section 13.4 for more details on 3-wire SPI mode. In motion detection mode with BT_MODE=VDD, use of HPM or FPM mode is not advised. Only the default LPM mode should be used.

16.3 Power supply considerations

NXP recommends that VDD be sourced from a low noise linear supply regulator (LDO). BOR/POR event from occurring when operated on a noisy supply rail. after a soft reset command is issued by setting SENS_CONFIG1[RST] = 1. over the I2C or SPI interfaces. (BOOT_OUT) that pulses low for TPULSE-BOOT2 ms after the boot sequence completes.

NXP Semiconductors FXLS8974CF 3-Axis Low-g Accelerometer The FXLS8974CF uses a ten-pin DFN package, case number 98ASA00979D. Objective data sheet Rev. 1 — 27 April 2021

17.1 Package description

Figure 25. FXLS8974CF package outline

Figure 26. FXLS8974CF package outline detail

Figure 27. FXLS8974CF package outline notes

17.2 Lead dimension detail

package as indicated on the drawing.

0.125 MIN

Figure 28. Bottom and leaded view dimensions

18 Soldering information

18.1 Printed circuit board layout and device mounting

correct size as a base for a proper solder connection between the PCB and the package. package after board mounting. NXP application note AN1902[1] discusses the DFN package used by the FXLS8974CF.

18.1.1 Overview of soldering considerations

18.1.2 Halogen content

This package is Halogen free, exceeding most industry and customer standards. excess of 900 ppm or 0.09 % weight/weight.

19 Mounting information

19.1 PCB mounting recommendations

• No additional via, copper layer, solder mask, metal pattern underneath package on the mounted layer of the PCB. Objective data sheet Rev. 1 — 27 April 2021

• Do not place any components or vias within 2 mm of the package land area as it may cause additional package stress if placed too close to the package land area.
• Signal traces connected to pads should be as symmetric as possible. To have the same length of exposed trace for all pads, put dummy traces on NC pads .
• Use a standard pick-and-place process and equipment. Do not use a hand soldering process.
• Customers are advised to be cautious about the proximity of screw-down holes to the sensor, and the location of any press fit to the assembled PCB when in an enclosure. It is important that the assembled PCB remain flat after assembly to keep electronic operation of the device optimal.
• The PCB should be rated for the multiple lead-free reflow condition with a maximum 260 °C temperature.
• NXP sensors are compliant with Restrictions on Hazardous Substances (RoHS), having halide-free molding compound (green) and lead-free terminations. These terminations are compatible with tin-lead (Sn-Pb) as well as tin-silver-copper (Sn-Ag- Cu) solder paste soldering processes. Reflow profiles applicable to those processes can be used successfully for soldering the devices. 10X 0.25 0.15 10X 0.45 0.35 10X 0.400 Min1 2X 0.050 Typ2 2X 0.050 Typ2 2X 0.050 Typ2 2X 0.0375 Typ2 2X 0.0375 Typ2 10X 0.425 Min

0.450 Typ

0.850 Typ

0.225 Typ

will be influenced less by PCB assembly issues, such as misalignment. than or equal to PCB vendor's solder mask registration. Figure 29. PCB footprint guidelines

20 Glossary

the maximum of these six terms. default LPM mode should be used. Primary Device that initiates and drives the communication with secondary devices. Secondary Device or devices that responds to communication initiated by primary device. physical acceleration. Refer to AN5311[2] for more details on self-test. board or exposing it to extensive mechanical stress. removed using the OFF_X/Y/Z registers, or alternatively, in the host application software. Table 121. Glossary

21 References

Table 122. Revision history

NXP Semiconductors FXLS8974CF 3-Axis Low-g Accelerometer

23 Legal information

23.1 Data sheet status

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

23.2 Definitions

Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

23.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Objective data sheet Rev. 1 — 27 April 2021

NXP Semiconductors FXLS8974CF 3-Axis Low-g Accelerometer No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. AEC unqualified products — This product has not been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and should not be used in automotive applications, including but not limited to applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non- automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified or documented vulnerabilities. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products.

23.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. NXP — wordmark and logo are trademarks of NXP B.V. Objective data sheet Rev. 1 — 27 April 2021

NXP Semiconductors FXLS8974CF 3-Axis Low-g Accelerometer Tables Tab. 7. Accelerometer sensor performance Tab. 9. Temperature sensor performance Tab. 11. FXLS8974CF I2C read and write Tab. 12. I2C secondary timing values for Standard- mode (Sm), Fast-mode (Fm), and Fast- Tab. 15. FXLS8974CF operating modes Tab. 17. BOOT2 sequence and One-wire motion Tab. 18. One-wire motion protocol threshold Tab. 19. BOOT1 sequence description (BT_MODE Tab. 21. INT_STATUS register (address 00h) bit Tab. 22. INT_STATUS register (address 00h) bit Tab. 23. TEMP_OUT register (address 01h) bit Tab. 24. VECM_LSB register (address 02h) bit Tab. 25. VECM_LSB register (address 02h) bit Tab. 26. VECM_MSB register (address 03h) bit Tab. 27. VECM_MSB register (address 03h) bit Tab. 28. OUT_X_LSB and OUT_X_MSB register (addresses 04h to 05h) with SEN_ Tab. 29. OUT_Y_LSB and OUT_Y_MSB register (addresses 06h to 07h) with SEN_ Tab. 30. OUT_Z_LSB and OUT_Z_MSB register (addresses 08h to 09h) with SEN_ Tab. 31. OUT_X_LSB and OUT_X_MSB register (addresses 04h to 05h) with SEN_ Tab. 32. OUT_Y_LSB and OUT_Y_MSB register (addresses 06h to 07h) with SEN_ Tab. 33. OUT_Z_LSB and OUT_Z_MSB register (addresses 08h to 09h) with SEN_ Tab. 34. BUF_STATUS register (address 0Bh) bit Tab. 35. BUF_STATUS register (address 0Bh) bit Tab. 36. BUF_X_LSB and BUF_X_MSB registers (addresses 0Ch, 0Dh) with SENS_ Tab. 37. BUF_Y_LSB and BUF_Y_MSB registers (addresses 0Eh, 0Fh) with SENS_ Tab. 38. BUF_Z_LSB and BUF_Z_MSB registers (addresses 10h, 11h) with SENS_ Tab. 39. BUF_X_LSB and BUF_X_MSB registers (addresses 0Ch, 0Dh) with SENS_ Tab. 40. BUF_Y_LSB and BUF_Y_MSB registers (addresses 0Eh, 0Fh) with SENS_ Tab. 41. BUF_Z_LSB and BUF_Z_MSB registers (addresses 10h, 11h) with SENS_ Tab. 42. PROD_REV register (address 12h) bit Tab. 43. PROD_REV register (address 12h) bit Tab. 44. WHO_AM_I register (address 13h) bit Tab. 45. SYS_MODE register (address 14h) bit Tab. 46. SYS_MODE register (address 14h) bit Tab. 47. SENS_CONFIG1 register (address 15h) bit Tab. 48. SENS_CONFIG1 register (address 15h) bit Tab. 49. SENS_CONFIG2 register (address 16h) bit Tab. 50. SENS_CONFIG2 register (address 16h) bit Tab. 51. SENS_CONFIG3 register (address 17h) bit Tab. 52. WAKE and SLEEP low-power mode ODR Tab. 53. WAKE and SLEEP High Performance Tab. 54. WAKE and SLEEP decimation settings in Tab. 55. SENS_CONFIG4 register (address 18h) bit Objective data sheet Rev. 1 — 27 April 2021

NXP Semiconductors FXLS8974CF 3-Axis Low-g Accelerometer Tab. 56. SENS_CONFIG4 register (address 18h) bit Tab. 57. INTx pin behavior as a function of INT_PP_ OD and INT_POL bit settings (valid only Tab. 58. INTx pin behavior as a function of INT_PP_ OD and INT_POL bit settings (valid only Tab. 59. SENS_CONFIG5 register (address 19h) bit Tab. 60. SENS_CONFIG5 register (address 19h) bit Tab. 61. WAKE_IDLE_LSB register (address 1Ah) Tab. 62. WAKE_IDLE_MSB register (address 1Bh) Tab. 63. SLEEP_IDLE_LSB register (address 1Ch) Tab. 64. SLEEP_IDLE_MSB register (address 1Dh) Tab. 65. ASLP_COUNT_LSB register (address 1Eh) Tab. 66. ASLP_COUNT_LSB register (address 1Eh) Tab. 67. ASLP_COUNT_MSB register (address Tab. 68. ASLP_COUNT_MSB register (address Tab. 70. Auto-WAKE/SLEEP Interrupt Event Tab. 71. INT_EN register (address 20h) bit Tab. 72. INT_EN register (address 20h) bit Tab. 73. INT_PIN_SEL register (address 21h) bit Tab. 74. INT_PIN_SEL register (address 21h) bit Tab. 75. OFF_X register (addresses 22h) bit Tab. 76. OFF_Y register (addresses 23h) bit Tab. 77. OFF_Z register (addresses 24h) bit Tab. 78. BUF_CONFIG1 register (address 26h) bit Tab. 79. BUF_CONFIG1 register (address 26h) bit Tab. 80. BUF_CONFIG2 register (address 27h) bit Tab. 81. BUF_CONFIG2 register (address 27h) bit Tab. 82. ORIENT_STATUS register (address 28h) Tab. 83. ORIENT_STATUS register (address 28h) Tab. 84. ORIENT_CONFIG register (address 29h) Tab. 85. ORIENT_CONFIG register (address 29h) Tab. 86. ORIENT_DBCOUNT register (address Tab. 87. ORIENT_DBCOUNT register (address Tab. 88. ORIENT_BF_ZCOMP register (address Tab. 89. ORIENT_BF_ZCOMP register (address Tab. 91. ORIENT Back/Front orientation transition Tab. 92. ORIENT_THS register (address 2Ch) bit Tab. 93. Orientation change trip angles look-up Tab. 94. Resultant trip angle (threshold angle ± Tab. 95. Orientation change ideal orientation angle Tab. 96. SDCD_INT_SRC1 register (address 2Dh) Tab. 97. SDCD_INT_SRC1 register (address 2Dh) Tab. 98. SDCD_INT_SRC2 register (address 2Eh) Tab. 99. SDCD_INT_SRC2 register (address 2Eh) Tab. 100. SDCD_CONFIG1 register (address 2Fh) bit Tab. 101. SDCD_CONFIG1 register (address 2Fh) bit Tab. 102. SDCD_CONFIG2 register (address 30h) bit Tab. 103. SDCD_CONFIG2 register (address 30h) bit Tab. 104. SDCD_OT_DBCNT register (address 31h) Tab. 105. SDCD_OT_DBCNT register (address 31h) Tab. 106. SDCD_WT_DBCNT register (address 32h) Tab. 107. SDCD_WT_DBCNT register (address 32h) Tab. 108. SDCD_LTHS_LSB register (address 33h) Tab. 109. SDCD_LTHS_LSB register (address 33h) Tab. 110. SDCD_LTHS_MSB register (address 34h) Tab. 111. SDCD_LTHS_MSB register (address 34h) Tab. 112. SDCD_UTHS_LSB register (address 35h) Tab. 113. SDCD_UTHS_LSB register (address 35h) Tab. 114. SDCD_UTHS_MSB register (address 36h) Objective data sheet Rev. 1 — 27 April 2021

NXP Semiconductors FXLS8974CF 3-Axis Low-g Accelerometer Tab. 115. SDCD_UTHS_MSB register (address 36h) Tab. 116. SELF_TEST_CONFIG1 register (address Tab. 117. SELF_TEST_CONFIG1 register (address Tab. 118. SELF_TEST_CONFIG2 register (address Tab. 119. SELF_TEST_CONFIG2 register (address Tab. 120. Self-Test measurement phase decimation Figures Fig. 3. Sensitive axes orientation and output Fig. 4. I2C secondary timing diagram for Standard-mode, Fast-mode and Fast-mode Fig. 6. SPI single-byte write protocol diagram (3- Fig. 7. SPI multiple-byte write protocol diagram (3- Fig. 8. SPI single-byte read protocol diagram (4- Fig. 9. SPI multiple-byte read protocol diagram (4- Fig. 10. SPI single-byte read protocol diagram (3- Fig. 11. SPI multiple-byte read protocol diagram (3- Fig. 15. BOOT2 sequence and One-wire motion- detection protocol diagram (BT_MODE = Fig. 20. Typical Application Circuit #2 – SPI 4-wire Fig. 21. Typical Application Circuit #3 – SPI 3- wire mode (software enabled; SENS_ Fig. 22. Typical Application Circuit #4 – SPI 3-wire mode (hardwired; SENS_CONFIG1[SPI_ Fig. 23. Typical Application Circuit #5 – Motion Fig. 24. Typical Application Circuit #6 - Motion detection mode (with SPI 3-wire interface, Objective data sheet Rev. 1 — 27 April 2021

NXP Semiconductors FXLS8974CF 3-Axis Low-g Accelerometer Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 April 2021 Document identifier: FXLS8974CF