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Document overview
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- PDF pages: 75
Technical content
Datasheet sections
- 1 Block Diagram
- 2 Pin Description
- 2.1 Soldering information
- 2.2 Orientation
- 3 Example FXLS8471Q Driver Code
- 3.1 Introduction
- 3.2 FXLS8471Q Addresses
- 3.3 Sensor data structure
- 3.4 FXLS8471Q Configuration function
- 3.5 FXLS8471Q Data Read function
- 4 Terminology
- 4.1 Sensitivity
- 4.2 Zero-g Offset
- 4.3 Self-Test
- 5 Device Characteristics
- 5.1 Mechanical characteristics
- 5.2 Electrical characteristics
- 5.3 Absolute maximum ratings
- 6 Digital Interfaces
- 6.1 I 2C interface characteristics
- 6.1.1 General I 2C operation
- 6.1.2 I 2C Read/Write operations
- 6.2 SPI Interface characteristics
- 6.2.1 General SPI operation
- 6.2.2 SPI READ/WRITE operations
- 6.2.3 I 2C/SPI auto detection
- 6.2.4 Power supply sequencing and I 2C/SPI mode auto-detection
- 7 Modes of Operation
- 8 Embedded Functionality
- 8.1 Factory calibration
- 8.3 Low-power modes versus high-resolution modes
- 8.4 Auto-Wake/Sleep mode
- 8.5 Freefall and Motion event detection
- 8.5.1 Freefall detection
- 8.5.2 Motion detection
- 8.6 Transient detection
- 8.7 Pulse detection
- 8.8 Orientation detection
- 8.9 Acceleration Vector-Magnitude detection
- 9 Register Map
- 10 Registers by Functional Blocks
- 10.1 Device configuration
- 10.1.1 STATUS (0x00) register
- 10.1.2 DR_STATUS (0x00) register
- 10.1.3 F_STATUS (0x00) register
- 10.1.4 TRIG_CFG (0x0A) register
- 10.1.5 SYSMOD (0x0B) register
- 10.1.6 INT_SOURCE (0x0C) register
- 10.1.7 WHO_AM_I (0x0D) register
- 10.1.8 CTRL_REG1 (0x2A) register
- 10.1.9 CTRL_REG2 (0x2B) register
- 10.1.10 CTRL_REG3 [Interrupt Contro l Register] (0x2C) register
- 10.1.11 CTRL_REG4 [Interrupt Enable Register ] (0x2D) register
- 10.1.12 CTRL_REG5 [Interrupt Rout ing Configuration Register] (0x2E) register
- 10.2 Auto-Sleep trigger
- 10.2.1 ASLP_COUNT (0x29) register
- 10.3 Output data registers
- 10.3.1 OUT_X_MSB (0x01), OUT_X_LSB (0x02), OUT_Y_MSB (0x03), OUT_Y_LSB (0x04),
- 10.4 FIFO
- 10.4.1 F_SETUP (0x09) register
- 10.5 Sensor data configuration
Features
- 1.95 V to 3.6 V VDD supply voltage, 1.62 V to 3.6 V VDDIO voltage
- ± 2 g/±4 g/±8 g dynamically selectable acceleration full-scale ranges
- Output Data Rates (ODR) from 1.563 Hz to 800 Hz
- Low noise: typically 99 μg/Hz in low-noise mode @ 200-Hz bandwidth
- 14-bit ADC resolution: 0.244 mg/LSB in ±2 g, full-scale range
- Embedded programmable acceleration event functions: — Freefall and Motion Detection — Transient Detection — Vector-Magnitude Change Detection — Pulse and Tap Detection (Single and Double) — Orientation Detection (Portrait/Landscape)
- Programmable automatic ODR change using Auto-Wake and return to Sleep functions to save power.
- 192-byte FIFO buffer, capable of storing up to 32 samples of X/Y/Z data
- Supports 4-wire SPI interface at up to 1 MHz; I 2C Normal (100 kHz) and Fast Modes (400 kHz)
- Integrated accelerome ter self-test function Target Markets
- Industrial applications: vibration analysis, machine health monitoring, and platform stabilization
- Smartphones, tablets, digital cameras, and personal navigation devices
- Medical applications: patient monitoring, fall detection, and rehabilitation
Applications
- Shock and vibration monitoring (mechatronic compensation, shipping, and warranty usage logging)
- User interface (menu scrolling by orientatio n change, tap detection for button replacement)
- Orientation detection (portrait/landscape: up/dow n, left/right, back/front position identification)
- Gaming and real-time activity analysis (pedometry, freefall and drop detection for hard disk drives and other devices)
- Power management for mobile devic es using inertial event detection 1VDDIO 16 15 14 BYP Reserved SCL/SCLK GND Reserved GND INT1 SA1/CS_B INT2 SDA/MOSI SA0/MISO RST N/C VDD
16 LEAD QFN
2 Freescale Semiconductor, Inc. Related Documentation The FXLS8471Q device features and operations are described in a variety of reference manuals, user guides, and application notes. To find the most-current versions of these documents: 1. Go to the Freescale homepage at: http://www.freescale.com/ 2. In the Keyword search box at the top of the page, enter the device number FXLS8471Q. In the Refine Your Result pane on the left, click on the Documentation link.
ORDERING INFORMATION
Part Number Temperature Range Package Description Shipping FXLS8471QR1 -40°C to +85°C QFN-16 Tape and Reel (1 k)
4 Freescale Semiconductor, Inc.
10.8.3 A_FFMT_THS (0x17), A_FFMT_ THS_X_ MSB (0x73), A_FFMT_THS_X_LSB (0x74),
A_FFMT_THS_Y_MSB (0x75), A_FFMT_THS_Y_LSB (0x76), A_FFMT_THS_Z_MSB (0x77), 10.11.
1 Block Diagram
Figure 1. Block diagram
6 Freescale Semiconductor, Inc.
2 Pin Description
Figure 2. Pinout diagram decoupled with a 100 nF ceramic capacitor placed as close as possible to pin 1 of the device. removed, these pins will clamp any logic signals through their internal ESD protection diodes. Table 1. Pin Description
1 VDDIO Interface power supply
2 BYP Internal regulator output bypass capacitor connection
3 Reserved Test reserved, connect to GND
5 GND Ground
7 SA0/MISO (1)
- The SA0 pin is also used to select the desired serial inte rface mode during POR and also after a hard/soft reset event. Please see
8 N/C Internally not connected
9 INT2 Interrupt 2
10 SA1/CS_B I
- See Table 8 for I2C address options selectable using the SA0 and SA1 pins.
11 INT1 Interrupt 1
12 GND Ground
13 Reserved Test reserved, connect to GND
14 VDD Power supply
15 N/C Internally not connected
16 Lead QFN-COL
and SCL I2C connections are open drain and therefore require a pullup resistor as shown in the application diagram in Figure 3. Figure 3. Electrical connection
2.1 Soldering information
pins are configured for push/pull (default) operation. required if the device is operated in SPI Interface mode.
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2.2 Orientation
Figure 4. Component axes orientation and response to gravity stimulus
Freescale Semiconductor, Inc. 9
3 Example FXLS8 471Q Driver Code
3.1 Introduction
It is very straightforward to configure the FXLS8471Q and start receiving data from the three accelerometerchannels. Unfortunately, since every hardware platform will be different, it is not possible to provide completely portable software drivers. This section therefore provides real FXLS8471Q driver code for a Kinetis uC board running under the MQX operating system. The I 2C functions s_i2c_read_regs and s_i2c_write_regs are not provided here and should be replaced with the corresponding low level I2C driver code on the development platform.
3.2 FXLS8471Q Addresses
This section lists the I2C address of the FXLS8471Q. The I2C address depends on the logic level of FXLS8471Q pins SA0 and SA1 so the I2C address may be 0x1C, 0x1D, 0x1E or 0x1F. Example 1. // FXLS8471Q I2C address #define FXLS8471Q_SLAVE_ADDR 0x1E // with pins SA0=0, SA1=0 Some of the key FXLS8471Q internal register addresses are listed below. Example 2. // FXLS8471Q internal register addresses #define FXLS8471Q_STATUS 0x00 #define FXLS8471Q_WHOAMI 0x0D #define FXLS8471Q_XYZ_DATA_CFG 0x0E #define FXLS8471Q_CTRL_REG1 0x2A #define FXLS8471Q_WHOAMI_VAL 0x6A The reference driver here does a block read of the FXLS8471Q status byte plus three 16-bit accelerometer channels. Example 3. // number of bytes to be read from FXLS8471Q #define FXLS8471Q_READ_LEN 7// status plus 3 accelerometer channels
3.3 Sensor data structure
The high and low bytes of the three accelerometer are placed into a structure of type SRAWDATA containing three signed short integers. Example 4. typedef struct int16_t x; int16_t y; int16_t z; } SRAWDATA;
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3.4 FXLS8471Q Confi guration function
This function configures the FXLS8471Q for a 200-Hz ODR. The code is self-explanatory and can be easily customized for different settings. Example 5. // function configures FXLS8471Q accelerometer sensor static _mqx_int s_FXLS8471Q_start(MQX_FILE_PTR aFP) uint8_t databyte; // read and check the FXLS8471Q WHOAMI register if (s_i2c_read_regs(aFP, FXLS8471Q_SLAVE_ADDR, FXLS8471Q_WHOAMI, &databyte, (uint8_t) 1) != 1) return (I2C_ERROR); if (databyte != FXLS8471Q_WHOAMI_VAL) return (I2C_ERROR); // write 0000 0000 = 0x00 to accelerometer control register 1 to place FXLS8471Q into // standby // [0]: active=0 databyte = 0x00; if (s_i2c_write_regs(aFP, FXLS8471Q_SLAVE_ADDR, FXLS8471Q_CTRL_REG1, &databyte, (uint8_t) 1) != 1) return (I2C_ERROR); // write 0000 0001= 0x01 to XYZ_DATA_CFG register // [7]: reserved // [6]: reserved // [5]: reserved // [4]: hpf_out=0 // [3]: reserved // [2]: reserved // [1-0]: fs=01 for accelerometer range of +/-4g with 0.488mg/LSB databyte = 0x01; if (s_i2c_write_regs(aFP, FXLS8471Q_SLAVE_ADDR, FXLS8471Q_XYZ_DATA_CFG, &databyte, (uint8_t) 1) != 1) return (I2C_ERROR); // write 0001 0101b = 0x15 to accelerometer control register 1 // [7-6]: aslp_rate=00 // [5-3]: dr=010 for 200Hz data rate // [2]: lnoise=1 for low noise mode // [1]: f_read=0 for normal 16 bit reads // [0]: active=1 to take the part out of standby and enable sampling databyte = 0x15; if (s_i2c_write_regs(aFP, FXLS8471Q_SLAVE_ADDR, FXLS8471Q_CTRL_REG1, &databyte, (uint8_t) 1) != 1)
Freescale Semiconductor, Inc. 11 return (I2C_ERROR); // normal return return (I2C_OK);
3.5 FXLS8471Q Data Read function
This function performs a block read of the status and acceleration data and places the bytes read into the structures of type SRAWDATA as signed short integers. Example 6. // read status and the three channels of accelerometer data from // FXLS8471Q (7 bytes) int16_t ReadAccel(SRAWDATA *pAccelData) MQX_FILE_PTR fp; // I2C file pointer uint8_t Buffer[FXLS8471Q_READ_LEN]; // read buffer // read FXLS8471Q_READ_LEN=7 bytes (status byte and the three channels of data) if (s_i2c_read_regs(fp, FXLS8471Q_SLAVE_ADDR, FXLS8471Q_STATUS, Buffer, FXLS8471Q_READ_LEN) == FXLS8471Q_READ_LEN) // copy the 14 bit accelerometer byte data into 16 bit words pAccelData->x = ((Buffer[1] << 8) | Buffer[2])>> 2; pAccelData->y = ((Buffer[3] << 8) | Buffer[4])>> 2; pAccelData->z = ((Buffer[5] << 8) | Buffer[6])>> 2; else // return with error return (I2C_ERROR); // normal return return (I2C_OK);
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4 Terminology
4.1 Sensitivity
The sensitivity is represented in LSB/g. In 2-g mode the sensitivity is 4096 LSB/g. In 4-g mode the sensitivity is 2048 LSB/ g and in 8-g mode the sensitivity is 1024 LSB/g.
4.2 Zero-g Offset
Zero-g Offset describes the deviation of an actual output signal from the ideal output signal if the sensor is stationary. A sensor stationary on a horizontal surface will measure 0g in X-axis and 0g in Y -axis whereas the Z-axis will measure 1g. A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress on the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress.
4.3 Self-Test
Self-T est can be used to verify the transducer functionality without applying an external mechanical stimulus. When Self-T est is activated, an electrostatic actuation force is applied to the sensor, simulating a small acceleration. In this case, the sensor outputs will exhibit a change in their DC levels which are related to the selected full scale through the device sensitivity . When Self-T est is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic self-test force.
5 Device Characteristics
5.1 Mechanical characteristics
Table 2. Mechanical characteristics @ VDD = 2.5 V, VDDIO = 1.8 V T = 25°C unless otherwise noted.
- Dynamic range is limited to ±4 g when in the low-noise mode.
4096 LSB/g
2048 LSB/g
1024 LSB/g
- Post-board mount offset specificat ions are based on a 2-layer PCB design.
- After post-board mount corrections for sensitivity, cro ss axis and offset. Refer to AN4399 for more information.
- Self-test is only exercised along one direction for each sensitive axis.
- Measured using earth's gravitational field (1 g) with the device oriented horizontally (+Z axis up) and stationary.
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5.2 Electrical characteristics
Table 3. Electrical characteristics @ VDD = 2.5 V, VDDIO = 1.8 V T = 25°C unless otherwise noted.
- Time from VDDIO on and VDD > VDD min until I 2C/SPI interface ready for operation.
- Time to obtain valid data from power-down mode to Active mode.
- Time to obtain valid data from Standby mode to Active mode.
5.3 Absolute maximum ratings
extended periods may affect device reliability. Table 5. Maximum ratings Table 6. ESD and latchup protection characteristics cause the part to otherwise fail. This device is sensitive to ESD, improper handling can cause permanent damage to the part.
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6 Digital Interfaces
6.1 I 2C interface characteristics
Figure 5. I2C slave timing diagram Table 7. I2C slave timing values(1)
- All values referred to VIH (min) and VIL (max) levels.
- This device does not stretch the LOW period (t LOW) of the SCL signal.
- t VD;DAT = time for Data signal from SCL LOW to SDA output.
- t VD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
- C b = total capacitance of one bus line in pF.
6.1.1 General I 2C operation
data line while the SCL line is held HIGH. After the ST signal has been transmitted by the master, the bus is considered busy. remains stable low during the high period of the acknowledge clock period. support clock stretching. Not all master devices recognize clock stretching. This part does not use clock stretching. the logic level of the SA1 and SA0 inputs.
6.1.2 I 2C Read/Write operations
but transmits a stop condition to end the data transfer. master followed by a stop condition (SP) signaling an end of transmission. is now stored in the appropriate register. Table 8. I2C slave address
18 Freescale Semiconductor, Inc. acknowledgment (ACK) is received. Figure 6. I2C timing diagram
6.2 SPI Interface characteristics
Table 9 and Figure 7 describe the timing requirements for the SPI system. Figure 7. SPI Timing Diagram
6.2.1 General SPI operation
transaction is complete. During a transaction the master toggles the SPI clock (SCLK) and transmits data on the MOSI pin. Byte 2: DATA[7],DATA[6],DATA[5],DATA[4],DATA[3],DATA[2],DATA[1],DATA[0].
- Polarity: rising/falling
- Phase: sample/setup
- Order: MSB first Data is sampled during the rising edge of SCLK and set up during the falling edge of SCLK.
Table 9. SPI timing
20 Freescale Semiconductor, Inc.
6.2.2 SPI READ/WRITE operations
first and second serialized bytes. Subsequent bits are ignored by the part. The read data is deserialized from the MISO pin. data bytes can be transmitted into consecutive registers, starting from the indicated register address in ADDR[7:0]. Figure 8. SPI single-burst READ/WRITE transaction diagram
6.2.3 I 2C/SPI auto detection
after a hard or soft reset or powerup event.
6.2.4 Power supply sequencing and I 2C/SPI mode auto-detection
already low prior to the reset event, it will only go high. Table 10. Serial interface pin descriptions Table 11. I2C/SPI auto detection
7 Modes of Operation
Figure 9. FXLS8471Q power mode transition diagram transition between them, please refer to Section 8, “Embedded Functionality” or Freescale application note AN4074. Table 12. Mode of operation description are shutdown. I2C bus inhibited. Only digital blocks are enabled. Analog subsystem is disabled. Internal clocks disabled. All blocks are enabled (digital and analog).
22 Freescale Semiconductor, Inc.
8 Embedded Functionality
FXLS8471Q is a low-power, digital output 3-axis acceleration sensor with both I2C and SPI interface options. Extensive embedded functionality is provided to detect inertial events at low power, with the ability to notify the host processor via either of the two programmable interrupt pins. The embedded functionality includes:
- 8-bit or 14-bit accelerometer data with an option for high-pass filtered output data
- Four different oversampling options for the output data. The oversampling settings allow the end user to optimize the resolution versus power consumption trade-off in a given application.
- A low-noise accelerometer mode that functions independent ly of the oversampling modes for even higher resolution
- Low-power auto-wake/sleep function for conser ving power in portable battery powered applications
- Accelerometer pulse detection circuit which can be used to detect directional single and double taps
- Accelerometer directional motion and freefall event detection with programmable threshold and debounce time
- Acceleration transient detection with programmable threshold and debounce time. Transient detection can employ either a high-pass filter or use the difference between reference and current sample values.
- Orientation detection with programmable hysteresis for smoot h transitions between portrait and landscape orientations
- Accelerometer vector-magnitude change event detection with programmable reference, threshold, and debounce time values Many different configurations of the above functions are possible to suit the needs of the end application. Separate application notes are available to further explain the different configuration settings and potential use cases.
8.1 Factory calibration
FXLS8471Q is factory calibrated for sensitivity and offset on each axis. The trim values are stored in Non-Volatile Memory (NVM). On startup, the trim parameters are read from NVM and applied to the internal compensation circuitry. After mounting the device to the PCB, the user may further adjust the accelerometer offsets through the OFF_X/Y/Z registers. For more information on accelerometer calibration, refer to Freescale application note AN4069. 8.2 8-bit or 14-bit data The measured acceleration data is stored in the OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB registers as 2’s complement 14-bit numbers. The most significant 8-bits of each axis are stored in the OUT_X, Y, Z_MSB registers, so applications needing only 8-bit results simply read these three registers and ignore the OUT_X,Y, Z_LSB registers. To do this, the f_read mode bit in CTRL_REG1 must be set. When the full-scale range is set to 2 g, the measurement range is -2 g to +1.999 g, and each count corresponds to 0.244 mg at ±14-bits resolution. When the full-scale is set to 8g, the measurement range is -8 g to +7.996 g, and each count corresponds to 0.976 mg. The resolution is reduced by a factor of 64 if only the 8-bit results are used (CTRL_REG1[f_read] = 1). For further information on the different data formats and modes, please refer to Freescale application note AN4076.
8.3 Low-power modes vers us high-resolution modes
FXLS8471Q can be optimized for lower power or higher resolution of the accelerometer output data. High resolution is achieved by setting the lnoise bit in register 0x2A. This improves the resolution (by lowering the noise), but be aware that the dynamic range becomes fixed at ±4 g when this bit is set. This will affect all internal embedded functions (scaling of thresholds, etc.) and reduce noise. Another method for improving the resolution of the data is through oversampling. One of the oversampling schemes of the output data can be activated when CTRL_REG2[mods] = 2’b10 which will improve the resolution of the output data without affecting the internal embedded functions or fixing the dynamic range. There is a trade-off between low power and high resolution. Low power can be achieved when the oversampling rate is reduced. When CTRL_REG2[mods] = 2’b10, the lowest power is achieved, at the expense of higher noise. In general, the lower the selected ODR and OSR, the lower the power consumption. For more information on how to configure the device in low-power or high-resolution modes and understand the benefits and trade-offs, please refer to Freescale application note AN4075.
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8.4 Auto-Wake/Sleep mode
FXLS8471Q can be configured to transition between sample rates (with their respective current consumptions) based on the status of the embedded interrupt event generators in the device. The advantage of using the Auto-Wake/Sleep is that the system can automatically transition to a higher sample rate (higher current consumption) when needed but spends the majority of the time in the Sleep mode (lower current) when the device does not require higher sampling rates. Auto-Wake refers to the device being triggered by one of the interrupt event functions to transition to a higher sample rate. This may also interrupt the processor to transition from a sleep mode to a higher power mode. Sleep mode occurs when none of the enabled interrupt event functions has detected an interrupt within the user-defined, time- out period. The device will then transition to the specified lower sample rate. It may also alert the processor to go into a lower power mode to save power during this period of inactivity . Please refer to AN4074 for more detailed information on configuring the Auto- Wake/Sleep function.
8.5 Freefall and Motion event detection
FXLS8471Q integrates a programmable threshold based acceleration detection function capable of detecting either motion or freefall events depending upon the configuration. For further details and examples on using the embedded freefall and motion detection functions, please refer to Freescale application note AN4070.
8.5.1 Freefall detection
The detection of “Freefall” involves the monitoring of the X, Y, and Z axes for the condition where the acceleration magnitude is below a user-specified threshold for a user-definable amount of time. Typically, the usable threshold ranges are between ±100 mg and ±500 mg.
8.5.2 Motion detection
Motion detection is often used to alert the main processor that the device is currently in use. When the acceleration exceeds a set threshold for a set amount of time, the motion interrupt is asserted. A motion can be a fast moving shake or a slow moving tilt. This will depend on the threshold and timing values configured for the event. The motion detection function can analyze static acceleration changes or faster jolts. The timing value is set by a configurable debounce counter. The debounce counter acts like a filter to indicate whether the condition exists for longer than a set amount of time (that is, 100 ms or longer). There is also directional data available in the source register to detect the direction of the motion that generated the interrupt. This is useful for applications such as directional shake or flick detection, and can also assist gesture detection algorithms by indicating that a motion gesture has started.
8.6 Transient detection
FXLS8471Q integrates an acceleration transient detection function that incorporates a high-pass filter. Acceleration data goes through the high-pass filter, eliminating the DC tilt offset and low frequency acceleration changes. The high-pass filter cutoff can be set by the user to four different frequencies which are dependent on the selected Output Data Rate (ODR). A higher cutoff frequency ensures that DC and slowly changing acceleration data will be filtered out, allowing only the higher frequencies to pass. The transient detection feature can be used in the same manner as the motion detection by bypassing the high-pass filter. There is an option in the configuration register to do this. This adds more flexibility to cover the various customer use cases. Many applications use the accelerometer’s static acceleration readings (that is, tilt) which measure the change in acceleration due to gravity only. These functions benefit from acceleration data being filtered with a low-pass filter where high-frequency data is considered noise. However, there are many functions where the accelerometer must analyze dynamic acceleration. Functions such as tap, flick, shake and step counting are based on the analysis of the change in the dynamic acceleration. The transient detection function can be routed to either interrupt pin through bit 5 in CTRL_REG5 register (0x2E). Registers 0x1D – 0x20 are used for configuring the transient detection function. The source register contains directional data to determine the direction of the transient acceleration, either positive or negative. For further information of the embedded transient detection function along with specific application examples and recommended configuration settings, refer to Freescale application note AN4461.
8.7 Pulse detection
FXLS8471Q has embedded single/double and directional pulse detection. This function employs several timers for programming the pulse width time and the latency between pulses. The detection thresholds are independently programmable for each axis. The acceleration data input to the pulse detection circuit can be put through both high and low-pass filters, allowing for greater flexibility in discriminating between pulse and tap events. The PULSE_SRC register provides information on the axis, direction (polarity), and single/double event status for the detected pulse or tap. For more information on how to configure the device for pulse detection, please refer to Freescale application note AN4072.
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8.8 Orientation detection
FXLS8471Q has an embedded orientation detection algorithm with the ability to detect all six orientations. The transition angles and hysteresis are programmable, allowing for a smooth transition between portrait and landscape orientations. The angle at which the device no longer detects the orientation change is referred to as the “Z-lockout angle”. The device operates down to 29° from the flat position. All angles are accurate to ±2°. For further information on the orientation detection function refer to Freescale application note, AN4068.
8.9 Acceleration Vector-Magnitude detection
FXLS8471Q incorporates an acceleration vector-magnitude change detection block that can be configured to generate an interrupt when the acceleration magnitude exceeds a preset threshold for a programmed debounce time. The function can be configured to operate in absolute or relative modes, and can also act as a wake to sleep/sleep to wake source. This function is useful for detecting acceleration transients when operated in absolute mode, or for detecting changes in orientation when operated in relative mode, refer to Freescale application note AN4692.
9 Register Map
Table 13. Register Address Map
26 Freescale Semiconductor, Inc. Table 13. Register Address Map (Continued)
there is no stop condition and the auto-increment address is not automatically reset to 0x00.
- Register contents are preserved when transitioning from Active to Standby mode.
- Register contents are reset when trans itioning from Standby to Active mode.
- Register contents can be modified anytime in Standby or Active mode. A write to this register will cause a reset of the corresponding internal
- Modification of this register’s contents can only occur when device is in Standby mode, except the FS[1:0] bit fields in CTRL_REG1 register.
28 Freescale Semiconductor, Inc.
10 Registers by Functional Blocks
10.1 Device configuration
10.1.1 STATUS (0x00) register
the auto-increment addressing mechanism in both 8- and 14-bit modes.
10.1.2 DR_STATUS (0x00) register
OUT_X, OUT_Y, and OUT_Z registers. time status information of the accelerometer X, Y, and Z axes sample data. Table 14. STATUS register Table 15. STATUS Description Table 16. DR_STATUS register Table 17. DR_STATUS description cleared when the high-bytes of the acceleration data (OUT_X_MSB, OUT_Y_MSB, and OUT_Z_MSB) are read. X, Y , Z-axis data overwrite. previous data is overwritten. zow is cleared anytime OUT_Z_MSB register is read. previous data is overwritten. yow is cleared anytime OUT_Y_MSB register is read. previous data is overwritten. xow is cleared anytime OUT_X_MSB register is read.
10.1.3 F_STATUS (0x00) register
FIFO Status when F_SETUP[f_mode] = 0x00 > 0x00. bit will be set again when the next data sample enters the FIFO. f_cnt value is equal to or greater than then f_wmrk value. acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) are read. X, Y , Z-axis new data ready. zdr is set to 1 whenever a new Z-axis data acquisition is completed. zdr is cleared anytime the OUT_Z_MSB register is read. ydr is set to 1 whenever a new Y-axis data acquisition is completed. ydr is cleared anytime the OUT_Y_MSB register is read. xdr is set to 1 whenever a new X-axis data acquisition is completed. xdr is cleared anytime the OUT_X_MSB register is read. Table 18. F_STATUS register Table 19. FIFO flag event descriptions 0 X No FIFO overflow events detected. 1 X FIFO overflow event detected. X 0 No FIFO watermark event detected. Table 20. FIFO sample count bit description FIFO sample counter. Default value 6’b000000. Table 17. DR_STATUS description (Continued)
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10.1.4 TRIG_CFG (0x0A) register
FIFO and the various trigger events, please see AN4073 available on the Freescale website.
10.1.5 SYSMOD (0x0B) register
also indicates the status of the FIFO gate error flag and the time elapsed since the FIFO gate error flag was asserted. Table 21. TRIG_CFG register Table 22. TRIG_CFG bit descriptions trig_trans Transient interrupt FIFO trigger enable. trig_lndprt Landscape/Portrait orientation interrupt FIFO trigger enable. trig_a_vecm Acceleration vector -magnitude FIFO trigger enable. Table 23. SYSMOD register Table 24. SYSMOD bit description FIFO gate error. Default value: 0. 0: No FIFO gate error detected. 1: FIFO gate error was detected. Emptying the FIFO buffer clears the fgerr bit in the SYSMOD register. See CTRL_REG3 [Interrupt CTRL register] (0x2C) for more information on configuring the FIFO Gate function. System mode. Default value: 0.
10.1.6 INT_SOURCE (0x0C) register
are cleared (logic ‘0’) indicate which function has not asserted its interrupt. interrupt flag bits are reset by reading the appropriate source register for the function that generated the interrupt. Table 25. INT_SOURCE register Table 26. INT_SOURCE bit descriptions transition interrupt event has occurred. (ASLP_COUNT) has been detected, thus causing the system to transition to a user-specified low ODR setting. system to transition to the user-specified higher ODR setting. Reading the SYSMOD register will clear the src_aslp bit. = F_STATUS[f_wmrk]) event has occurred and logic ‘0’ indicates that no FIFO interrupt event has occurred. This bit is cleared by reading the F_STATUS register. has occurred. and logic ‘0’ indicates that no transient event has occurred. This bit is asserted whenever TRANSIENT_SRC[ea] is asserted and the functional block interrupt has been enabled. This bit is cleared by reading the TRANSIENT_SRC register. device orientation status and logic ‘0’ indicates that no change in orientation status was detected. This bit is asserted whenever PL_STATUS[newlp] is asserted and the functional block interrupt has been enabled. This bit is cleared by reading the PL_STATUS register. logic ‘0’ indicates that no pulse event was detected. This bit is asserted whenever PULSE_SRC[ea] is asserted and the functional block interrupt has been enabled. This bit is cleared by reading the PULSE_SRC register. indicates that no freefall or motion event was detected. This bit is asserted whenever PULSE_SRC[ea] is asserted and the functional block interrupt has been enabled. This bit is cleared by reading the A_FFMT_SRC register. Data-ready interrupt status bit. In acceleration only mode this bit indicates that new accelerometer data is available to read. The src_drdy interrupt flag is cleared by reading out the acceleration data from the OUT_X, OUT_Y, and OUT_Z registers. This data can be burst read using a 6-byte burst read starting from the address 0x01 (OUT_X_MSB).
32 Freescale Semiconductor, Inc.
10.1.7 WHO_AM_I (0x0D) register
Device identification register. This register contains the device identifier which is set to 0x6A.
10.1.8 CTRL_REG1 (0x2A) register
the fields within CTRL_REG1 (0x2A). blocks is overridden by the sleep data rate set by the aslp_rate field.. Table 31 shows the various system output data rates (ODR) that may be selected using the dr[2:0] bits. Table 27. WHO_AM_I register Table 28. CTRL_REG1 register Table 29. CTRL_REG1 bit descriptions aslp_rate[1:0] Configures the auto-wake sample frequency when the device is in Sleep mode. See Table 30 for more information. dr[2:0] Output Data Rate (ODR) selection. See Table 31 for more information. Reduced noise and full-scale range mode (analog gain times 2). 1: Reduced noise mode; Note that the FSR setting is restricted to a ±4 g in this mode (lnoise = 1). the LSB addresses for each axes sample data when performing a burst read operation. Table 30. Sleep mode poll rate description
The active bit selects between Standby mode and Active mode. The default value is 0 (Standby mode) on reset. maximum signal that can be measured is ±4 g. Note: Any thresholds set above 4 g will not be reached. OUT_X_MSB register when f_read = 1. The f_read bit can only be changed while F_SETUP[f_mode] = 0.
10.1.9 CTRL_REG2 (0x2B) register
Table 31. System Output Data Rate selection Table 32. CTRL_REG2 register Table 33. CTRL_REG2 bit descriptions each axis, allowing the host application to check the functionality of the transducer and measurement signal chain. information and a suggested work-around. After setting the rst bit, the system will automatically transition to Standby mode. process begin. A system reset can also be initiated by pulsing the external RST pin high. inadvertently enter I2C mode. See Section 6.2.3 for further information about the interface mode auto-detection circuit. At the end of the boot process, the rst bit is hardware cleared. smods[1:0] Sleep mode power scheme selection. See Table 34 for more information.
- When SLPE = 1, a transition between Sleep mode and Wake mode result s in a FIFO flush and a reset of internal functional block counters.
description (fifo_gate bit). acceleration measurements. See Table 34 for more information.
34 Freescale Semiconductor, Inc. Table 34. CTRL_REG2[mods] oversampling modes
00 N ormal
Table 35. Oversampling Ratio versus oversampling mode
10.1.10 CTRL_REG3 [Interrupt Control Register] (0x2C) register
Table 36. CTRL_REG3 register Table 37. CTRL_REG3 bit descriptions FIFO buffer are preserved, new data samples are ignored until the FIFO is emptied by the host application. Emptying the FIFO buffer clears the SYS_MOD[fgerr] register.
- The FIFO contents are flushed whenever the system ODR changes in order to prevent the mixing of FIFO data from different ODR periods.
wake_lndprt 0: Orientation function is disabled Sleep mode. The ipol The bit selects the logic polarity of the interrupt signals output on the INT1 and INT2 pins. multiple interrupt signals on the same interrupt line but will require an external pullup resistor to function correctly.
36 Freescale Semiconductor, Inc.
10.1.11 CTRL_REG4 [Interrupt Enable Register] (0x2D) register
Table 38. CTRL_REG4 register Table 39. Interrupt Enable Register bit descriptions
10.1.12 CTRL_REG5 [Interrupt Routing Configuration Register] (0x2E) register
Table 40. CTRL_REG5 register Table 41. Interrupt Routing Configuration bit descriptions 1: Interrupt is routed to INT1 pin. 1: Interrupt is routed to INT1 pin.
10.2 Auto-Sleep trigger
10.2.1 ASLP_COUNT (0x29) register
provided that CTRL_REG2[slpe] = 1. See Table 45 for functional blocks that may be monitored for inactivity in order to trigger the return-to-sleep event. it prevents the FIFO buffer from accepting new sample data until the host application flushes the FIFO buffer. system will transition to the Sleep mode and use the ODR value specified in CTRL_REG1[aslp_rate]. Table 42. ASLP_COUNT register Table 43. ASLP_COUNT bit description Table 44. ASLP_COUNT relationship with ODR Table 45. Sleep/Wake mode gates and triggers
40 Freescale Semiconductor, Inc. enabled in register CTRL_REG3. If the Auto-Sleep interrupt is enabled, a transition from Active mode to Sleep mode and vice-versa will generate an interrupt. Figure 12. Auto-Sleep state transition diagram
10.3 Output data registers
10.3.1 OUT_X_MSB (0x01), OUT_X_LSB (0x02), OUT_Y_MSB (0x03), OUT_Y_LSB (0x04),
These registers contain the X-axis, Y-axis, and Z-axis 14-bit left-justified sample data expressed as 2's complement numbers. 32 X, Y, and Z data samples. CTRL_REG1[f_read] register setting. while registers 0x02, 0x03, 0x04, 0x05, 0x06 return a value of zero when read directly. read of 6 bytes starting at the OUT_X_MSB register. Table 46. OUT_X_MSB register Table 47. OUT_X_LSB register Table 48. OUT_Y_MSB register Table 49. OUT_Y_LSB register Table 50. OUT_Z_MSB register Table 51. OUT_Z_LSB register
42 Freescale Semiconductor, Inc.
10.4 FIFO
10.4.1 F_SETUP (0x09) register
A FIFO sample count exceeding the watermark event does not stop the FIFO from accepting new data. Auto-Sleep is active, the ODR is set by CTRL_REG1[aslp_rate] bit fields. the X-axis data, it will be lost. In Trigger mode, the FIFO is operated as a circular buffer and will contain up to the 32 most recent acceleration data samples. information on using the FIFO buffer and the various FIFO operating modes, please refer to Freescale application note AN4073. Table 52. F_SETUP register Table 53. F_SETUP bit descriptions
- This bit field can be written in Active mode.
- This bit field can be written in Standby mode.
- The FIFO mode ( f_mode) cannot be switched between operational modes (01, 10 and 11).
10: FIFO stops accepting new samples when overflowed. transition from Standby mode to Active mode. A FIFO overflow event (that is, F_STATUS[f_cnt] = 32) will assert the F_STATUS[f_ovf] flag. FIFO sample count watermark. Setting the f_wmrk to 6’b000000 will disable the FIFO watermark event flag generation. This field is also used to set the number of pre-trigger samples in trigger mode (f_mode = 2’b11).
10.5 Sensor data configuration
10.5.1 XYZ_DATA_CFG (0x0E) register
data is passed through the high-pass filter.
10.6 High-Pass filter
10.6.1 HP_FILTER_CUTOFF (0x0F) register
High-pass filter cutoff frequency setting register. Table 54. XYZ_DATA_CFG register Table 55. XYZ_DATA_CFG bit descriptions 0: High-pass filter is disabled.
11 R eserved
Table 57. HP_FILTER_CUTOFF register Table 58. HP_FILTER_CUTOFF bit descriptions
44 Freescale Semiconductor, Inc. Table 59. HP_FILTER_CUTOFF
10.7 Portrait/Landscape Detection
meaning of the different user-configurable settings and for example code, please refer to Freescale application note AN4068. Figure 13. Illustration of Z-tilt angle lockout transition Figure 14. Illustration of landscape to portrait transition Figure 15. Illustration of portrait to landscape transition
46 Freescale Semiconductor, Inc.
10.7.1 PL_STATUS (0x10) register
Back and Front orientations please refer to Figure 15. The interrupt is cleared when reading the PL_STATUS register. Table 60. PL_STATUS register Table 61. PL_STATUS bit descriptions Landscape/Portrait status change flag. 0: Lockout condition has not been detected. 1: Z-tilt lockout trip angle has been exceeded. Lockout condition has been detected.
- The default powerup state is bafro(Undefined), lapo(Undefined), and no lockout for orientation function.
Landscape/Portrait orientation. 11: Landscape left: equipment is in landscape mode to the left. 0: Front: equipment is in the front facing orientation. 1: Back: equipment is in the back facing orientation.
10.7.2 PL_CFG (0x11) register
This register enables the Portrait/Landscape function and sets the behavior of the debounce counter.
10.7.3 PL_COUNT (0x12) register
Standby (or vice-versa) resets the internal landscape/portrait internal debounce counters. Table 62. PL_CFG register Table 63. PL_CFG bit descriptions Debounce counter mode selection. 0: Decrements debounce whenever condition of interest is no longer valid. 1: Clears counter whenever condition of interest is no longer valid. Portrait/Landscape detection enable. 0: Portrait/Landscape detection is disabled. 1: Portrait/Landscape detection is enabled. Table 64. PL_COUNT register Table 65. PL_Count Relationship with the ODR
48 Freescale Semiconductor, Inc.
10.7.4 PL_BF_ZCOMP (0x13) register
Table 66. PL_BF_ZCOMP register Table 67. PL_BF_ZCOMP bit descriptions Z-lock angle threshold. range is from approximately 13° to 44°. Step size is approximately 4°. See Table 68 for more information. Back/front trip angle threshold. See Table 69 for more information. Default: 2’b10 → ±70°. Step size is 5°. Table 68. Z-lockout angle definitions Table 69. Back/Front orientation definitions
00 Z < 80° or Z > 280° Z > 100° and Z < 260°
01 Z < 75° or Z > 285° Z > 105° and Z < 255°
10 Z < 70° or Z > 290° Z > 110° and Z < 250°
11 Z < 65° or Z > 295° Z > 115° and Z < 245°
10.7.5 PL_THS_REG (0x14) register
Portrait to landscape trip threshold registers.
10.8 Freefall and Motion detection
condition occurring in any of the enabled axes (ex. X, Y or Z) will suffice to affect the A_FFMT_SRC[a_ffmt_ea] bit. (A_FFMT_THS_X/Y/Z) for individual axis threshold operation. Table 70. PL_THS_REG register Table 71. Threshold angle lookup table Table 72. Trip angles versus hysteresis settings Table 73. Portrait/Landscape ideal orientation definitions
50 Freescale Semiconductor, Inc. freefall or motion events are not latched, and the A_FFMT_SRC[a_ffmt_ea] bit reflects the real-time status of the event detection. A_FFMT_SRC[a_ffmt_ea] bit. See Figure 17 for details. A_FFMT_CFG[a_ffmt_xefe], A_FFMT_CFG[a_ffmt_yefe], and A_FFMT_CFG[a_ffmt_zefe]. axis may be programmed with an individual 13-bit threshold (stored in the A_FFMT_X/Y/Z MSB and LSB registers).
10.8.1 A_FFMT_CFG (0x15) register
Freefall/motion configuration register. Table 74. A_FFMT_CFG register Table 75. A_FFMT_CFG bit descriptions when the a_ffmt_ea bit gets set, and are cleared by reading the A_FFMT_SRC source register. (logical AND combination of low-g X, Y, Z-axis event flags) detection. Motion detect/freefall detect logic selection. flags are blocked from updating the A_FFMT_SRC register. 1: Raise event flag on measured Z-axis acceleration above/below threshold. flags are blocked from updating the A_FFMT_SRC register. 1: Raise event flag on measured Y-axis acceleration above/below threshold. flags are blocked from updating the A_FFMT_SRC register. 1: Raise event flag on measured X-axis acceleration above/below threshold.
10.8.2 A_FFMT_SRC (0x16) register
Freefall/motion source register. Read-only register. CTRL_REG5[int_cfg_ffmt] register bits to generate the freefall/motion interrupts. Table 76. A_FFMT_SRC register Table 77. A_FFMT_SRC bit descriptions effect of the 3-axis event flags on the a_ffmt_ea bit.
52 Freescale Semiconductor, Inc.
10.8.3 A_FFMT_THS (0x17), A_FFMT_ THS_X_MSB (0x73), A_FFMT_THS_X_LSB (0x74),
Freefall/motion detection threshold registers. Table 78. A_FFMT_THS (0x17) register Table 79. A_FFMT_THS (0x17) bit descriptions (part c, Figure 17) until the debounce counter reaches 0 or the inertial event of interest become active. detection of inertial events. ths[6:0] Freefall/motion detection threshold: default value: 7’b0000000. Resolution is fixed at 63 mg/LSB. Table 80. A_FFMT_THS_X_MSB (0x73) register Table 81. A_FFMT_THS_X_MSB (0x73) bit descriptions resolution of 63 mg/LSB, with a range of 0-127 counts. A_FFMT_THS_Z_MSB and A_FFMT_THS_Z_LSB for the Z-axis acceleration threshold. Table 82. A_FFMT_THS_X_LSB (0x74) register Table 83. A_FFMT_THS_Y_MSB (0x75) register Table 84. A_FFMT_THS_Y_LSB (0x76) register
Figure 16. A_FFMT_THS high and low-g level
10.8.4 A_FFMT_COUNT (0x18) register
either a freefall or motion detection event required before the interrupt is triggered. the ODR chosen (see Table 89). Table 85. A_FFMT_THS_Z_MSB (0x77) register Table 86. A_FFMT_THS_Z_LSB (0x78) register Table 87. A_FFMT_COUNT register Table 88. A_FFMT_COUNT bit description
54 Freescale Semiconductor, Inc. Figure 17. Behavior of the A_FFMT debounce counter in relation to the a_ffmt_dbcntm setting Table 89. A_FFMT_COUNT relationship with the ODR
10.9 Accelerometer vecto r-magnitude function
value stored in A_VECM_CNT, the vector-magnitude change event flag is triggered. values stored internally in the ASIC for each axis or in A_VECM_INIT_X/Y/Z registers if A_VECM_CFG[a_vecm_initm] is set. Please note that the x_ref, y_ref, and z_ref values are not directly visible to the host application through the register interface. Please refer to Freescale application note 4458.
10.9.1 A_VECM_CFG (0x5F) register
Table 90. A_VECM_CFG register Table 91. A_VECM_CFG bit descriptions Control bit a_vecm_initm defines how the initial reference values (x_ref, y_ref, and z_ref) are chosen. magnitude function is enabled. For a_vecm_initm = 1 the function uses the data from A_VECM_INIT_X/Y/Z registers as the initial reference values. writing to the A_VECM_INITX,Y,Z registers. A_VECM_INIT_X/Y/Z registers, depending on the state of the a_vecm_initm bit. Note: The vector-magnitude function will only perform correctly up to a maximum ODR of 400 Hz.
56 Freescale Semiconductor, Inc.
10.9.2 A_VECM_THS_MSB (0x60) register
10.9.3 A_VECM_THS_LSB (0x61) register
10.9.4 A_VECM_CNT (0x62) register
Table 92. A_VECM_THS_MSB register Table 93. A_VECM_THS_MSB bit descriptions Table 94. A_VECM_THS_LSB register Table 95. A_VECM_CNT register Table 96. A_VECM_CNT bit description a_vecm_cnt[7:0] Vector-magnit ude function debounce count value.
10.9.5 A_VECM_INITX_MSB (0x63) register
10.9.6 A_VECM_INITX_LSB (0x64) register
10.9.7 A_VECM_INITY_MSB (0x65) register
10.9.8 A_VECM_INITY_LSB (0x66) register
10.9.9 A_VECM_INITZ_MSB (0x67) register
Table 97. A_VECM_INITX_MSB register Table 98. A_VECM_INITX_MSB bit description a_vecm_initx[13:8] Most significant 6 bits of the signed 14-bit initial X-axis value to be used as ref_x when A_VECM_CFG[a_vecm_initm]=1 . The resolution is determined by the settings made in XYZ_DATA_CFG[fs], and is equal to the accelerometer resolution. Table 99. A_VECM_INITX_LSB register Table 100. A_VECM_INITX_LSB bit description resolution is determined by the settings made in XYZ_DATA_CFG[fs], and is equal to the accelerometer resolution. Table 101. A_VECM_INITY_MSB register Table 102. A_VECM_INITY_MSB bit description Table 103. A_VECM_INITY_LSB register Table 104. A_VECM_INITY_LSB bit description is determined by the settings made in XYZ_DATA_CFG[fs], and is equal to the accelerometer resolution. Table 105. A_VECM_INITZ_MSB register
58 Freescale Semiconductor, Inc.
10.9.10 A_VECM_INITZ_LSB (0x68) register
10.10 Transient (AC) a cceleration detection
transient detection function to work in a similar manner to the motion detection function. Freescale application note AN4461.
10.10.1 TRANSIENT_CFG (0x1D) register
Table 106. A_VECM_INITZ_MSB bit description Table 107. A_VECM_INITZ_LSB register Table 108. A_VECM_INITZ_LSB bit description resolution is determined by the settings made in XYZ_DATA_CFG[fs], and is equal to the accelerometer resolution. Table 109. TRANSIENT_ CFG register Table 110. TRANSIENT_ CFG bit descriptions 0: Event flag latch disabled: the transient interrupt flag reflects the real-time status of the function. required to clear the event flag. 1: Z-axis event detection enabled. Raise event flag on Z-axis acceleration value greater than threshold. 1: Y-axis event detection enabled. Raise event flag on Y-axis acceleration value greater than threshold. 1: X-axis event detection enabled. Raise event flag on X-axis acceleration value greater than threshold. 0: High-pass filter is applied to accelerometer data input to the transient function. 1: High-pass filter is not applied to accelerometer data input to the transient function.
10.10.2 TRANSIENT_SRC (0x1E) register
polarity bits, but once set, the flags can only be cleared by reading the TRANSIENT_SRC register. Table 111. TRANSIENT_ CFG register Table 112. TRANSIENT_SRC bit descriptions 0: No transient event active flag has been asserted. 1: One or more transient event active flags has been asserted. 0: Z-axis event flag is not active. 0: Z-axis event was above positive threshold value. 1: Z-axis event was below negative threshold value. 0: Y-axis event flag is not active. 0: Y-axis event was above positive threshold value. 1: Y-axis event was below negative threshold value. 0: X-axis event flag is not active. 0: X-axis event was above positive threshold value. 1: X-axis event was below negative threshold value.
60 Freescale Semiconductor, Inc.
10.10.3 TRANSIENT_THS (0x1F) register
axes using the a_ffmt_trans_ths_en bit in A_FFMT_THS_Y_MSB register. the measurement range is fixed at ±4 g, regardless of the settings made in XYZ_DATA_CFG.
10.10.4 TRANSIENT_COUNT (0x20) register
flag when the measured acceleration value exceeds the threshold set in TRANSIENT_THS for any of the enabled axes. would result in minimum debounce response time of 150 ms. Table 113. TRANSIENT_THS register Table 114. TRANSIENT_THS bit descriptions Debounce counter mode selection. 0: Decrements debounce counter when the transient event condition is not true during the current ODR period. 1: Clears debounce counter when the transient event condition is not true during the current ODR period. XYZ_DATA_CFG[fs]. If CTRL_REG1[lnoise] = 1, the maximum acceleration measurement range is ±4 g. Table 115. TRANSIENT_COUNT register Table 116. TRANSIENT_COUNT bit description tr_count[7:0) Transient function debounce count value. Table 117. TRANSIENT_COUNT relationship with the ODR
10.11 Pulse detection
10.11.1 PULSE_CFG (0x21) register
This register configures the pulse event detection function. Table 118. PULSE_CFG register Table 119. PULSE_CFG bit descriptions Pulse event flag latch enable. When enabled, a read of the PULSE_SRC register is needed to clear the event flag. Event flag enable on double-pulse event on Z-axis. Event flag enable on single-pulse event on Z-axis. Event flag enable on double-pulse event on Y-axis. Event flag enable on single-pulse event on Y-axis. 1: Raise event flag on detection of single-pulse event on Z-axis. Event flag enable on double-pulse event on X-axis. 1: Raise event flag on detection of double-pulse event on X-axis. Event flag enable on single-pulse event on X-axis. 1: Raise event flag on detection of single-pulse event on X-axis.
62 Freescale Semiconductor, Inc.
10.11.2 PULSE_SRC (0x22) register
This register indicates the status bits for the pulse detection function.
10.11.3 PULSE_THSX (0x23) register
regardless of the settings made in XYZ_DATA_CFG[fs]. Table 120. PULSE_SRC register Table 121. PULSE_SRC bit descriptions 1: X-axis event has occurred. Double pulse on first event. 0: Single-pulse event triggered interrupt. 1: Double-pulse event triggered interrupt. Pulse polarity of Z-axis event. 0: Pulse event that triggered interrupt was positive. 1: Pulse event that triggered interrupt was negative. Pulse polarity of Y-axis event. 0: Pulse event that triggered interrupt was positive. 1: Pulse event that triggered interrupt was negative. Pulse polarity of X-axis event. 0: Pulse event that triggered interrupt was positive. 1: Pulse event that triggered interrupt was negative. Table 122. PULSE_THSX register Table 123. PULSE_THSX bit description pls_thsx[6:0] Pulse threshold for X-axis.
10.11.4 PULSE_THSY (0x24) register
10.11.5 PULSE_THSZ (0x25) register
10.11.6 PULSE_TMLT (0x26) register
Table 124. PULSE_THSY register Table 125. PULSE_THSY bit description pls_thsy[6:0] Pulse threshold for Y-axis. Table 126. PULSE_THSZ register Table 127. PULSE_THSZ bit description pls_thsz[6:0] Pulse threshold for Z-axis. Table 128. PULSE_TMLT register Table 129. PULSE_TMLT bit description Table 130. Time step for PULSE_TMLT with HP_FILTER_CUTOFF[pls_hpf_en] = 1
64 Freescale Semiconductor, Inc.
10.11.7 PULSE_LTCY (0x27) register
Table 131. Time step for PULSE_TMLT with HP_FILTER_CUTOFF[pls_hpf_en] = 0 Table 132. PULSE_LTCY register Table 133. PULSE_LTCY bit description Table 134. Time step for PULSE_LTCY with HP_FILTER_CUTOFF[pls_hpf_en] = 1
10.11.8 PULSE_WIND (0x28) register
The time step for the pulse-window counter varies with the selected ODR and power modes as defined in Tables 138 and 139. The maximum time value is equal to (time step @ ODR and power mode) x 255. Table 135. Time step for PULSE_LTCY with HP_FILTER_CUTOFF[pls_hpf_en] = 0 Table 136. PULSE_WIND register Table 137. PULSE_WIND bit description specified by the PULSE_WIND register. Table 138. Time step for PULSE_WIND with HP_FILTER_CUTOFF[pls_hpf_en] = 1
66 Freescale Semiconductor, Inc.
10.12 Offset correction
For more information on how to calibrate the 0 g offset, please refer to Freescale application note AN4069.
10.12.1 OFF_X (0x2F) register
10.12.2 OFF_Y (0x30) register
10.12.3 OFF_Z (0x31) register
Table 139. Time step for PULSE_WIND with HP_FILTER_CUTOFF[pls_hpf_en] = 0 Table 140. OFF_X register Table 141. OFF_X bit description off_x[7:0] X-axis offset correction value ex pressed as an 8-bit 2's complement number. Table 142. OFF_Y register Table 143. OFF_Y bit description off_y[7:0] Y-axis offset correction value expressed as an 8-bit 2's complement number. Table 144. OFF_Z register Table 145. OFF_Z bit description off_z[7:0] Z-axis offset correction value ex pressed as an 8-bit 2's complement number.
Freescale Semiconductor, Inc. 67
11 Mounting Guidelines for the Quad Flat No-Lead (QFN) Package
Printed Circuit Board (PCB) layout is a critical portion of the total design. The footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the PCB and the package. With the correct footprint, the packages will self-align when subjected to a solder reflow process. These guidelines are for soldering and mounting the Quad Flat No-Lead (QFN) package inertial sensors to PCBs. The purpose is to minimize the stress on the package after board mounting. The FXLS8471Q uses the QFN package platform. This section describes suggested methods of soldering these devices to the PCB for consumer applications. Freescale application note AN1902, “Quad Flat Pack No-Lead (QFN) Micro Dual Flat Pack No-Lead (DFN)” discusses the QFN package used by the FXLS8471Q, PCB design guidelines for using QFN packages and temperature profiles for reflow soldering.
11.1 Overview of soldering considerations
Information provided here is based on experiments executed on QFN devices. As they cannot represent exact conditions present at a customer site, the information provided herein should be used for guidance only and further process and design optimizations are recommended to develop an application specific solution. It should be noted that with the proper PCB footprint and solder stencil designs, the package will self-align during the solder reflow process.
11.2 Halogen content
This package is designed to be Halogen Free, exceeding most industry and customer standards. Halogen Free means that no homogeneous material within the assembled package will contain chlorine (Cl) in excess of 700 ppm or 0.07% weight/weight or bromine (Br) in excess of 900 ppm or 0.09% weight/weight.
11.3 PCB mounting recommendations
- The PCB land should be designed with Non-Solder Mask Defined (NSMD) as shown in Figure 18 and Figure 19. 2. No additional via pattern underneath package. 3. PCB land pad is 0.8 mm by 0.3 mm as shown in Figure 18 and Figure 19. 4. Solder mask opening = PCB land pad edge + 0.113 mm larger all around. 6. Stencil thickness is 100 or 125 μm. 7. Do not place any components or vias at a distance le ss than 2 mm from the package land area. This may cause additional package stress if it is too close to the package land area. 8. Signal traces connected to pads should be as symmetric as possible. Put dummy traces on the NC pads in order to have same length of exposed trace for all pads. 9. Use a standard pick and place process and equipment. Do not use a hand soldering process. 10. Do not use a screw down or stacking to fix the PCB into an enclosure as this could bend the PCB, putting stress on the package. 11. The PCB should be rated for the multiple lead- free reflow condition with max 260°C temperature. 12. No copper traces on top layer of PCB under the package. This will cause planarity issues with board mount. Freescale QFN sensors are compliant with Restrictions on Hazardous Substances (RoHS), having halide-free molding compound (green) and lead-free terminations. These terminations are compatible with tin-lead (Sn-Pb) as well as tin- silver-copper (Sn-Ag-Cu) solder paste soldering processes. Reflow profiles applicable to those processes can be used successfully for soldering the devices.
Table 146. Thermal resistance data
- Junction temperature is a function of di e size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature,
ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
- Per JEDEC JESD51-2 with the singl e-layer board (JESD51-3) horizontal.
- Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
- Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface
of the board near the package.
- Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
- Thermal characterization parameter indicating the temperatur e difference between package top and the junction temperature per JEDEC
JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
70 Freescale Semiconductor, Inc. This drawing is located at http://cache.freescale.com/files/shared/doc/package_info/98ASA00063D.pdf. CASE 2077-02 ISSUE A 16-LEAD QFN A B D E F G
Freescale Semiconductor, Inc. 71 CASE 2077-02 ISSUE A 16-LEAD QFN C
72 Freescale Semiconductor, Inc. Table 147. Package dimensions (mm)
Freescale Semiconductor, Inc. 73 Appendix A A.1 Errata A.1.1 SPI Mode Soft-reset using CTRL_REG2 (0x2B), bit 6 Description: Following a soft-reset command, issued by setting CTRL_REG2[rst] = 1, certain device-specific parameters do not get updated correctly from NVM, causing inaccurate data output and incorrect WHOAMI (0x0D) register content. This behavior happens only in SPI mode. In I2C mode the device works as advertised. Workaround: Avoid using soft-reset in SPI mode by alternately utilizing the hardware RESET pin.
74 Freescale Semiconductor, Inc. Table 148. Revision history 1.0 8/2013 • Initial data sheet.
- Global update: “counts/g” changed to “LSB/g” throughout document.
- Table 2: Updated Min values for Self-Test output change, X, Y, and Z from +249, +335, and +1680 to +192, +270, and +1275 respectively.
- Appendix A.1.1: Corrected register name in Description paragraph. 1.2 11/2014 • Added Ordering Information table on page 2. 1.3 01/2015 • Added callouts to the package drawing and dimension table following package drawing. 1.4 03/2015 • Table 147: Added Typ dimensions for Symbol C and E. 1.5 06/2015 • Added G callout to package drawing and dimension table following package drawing.
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