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Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform The FXLC95000CL Intelligent, Motion-Sensing Platform is a breakthrough device with the integration of a 3-axis MEMS accelerometer and a 32-bit ColdFire MCU that enables autonomous, high-precision sensing solutions with local computing and sensors management capability in an open, easy to use, architecture. The FXLC95000CL hardware is user-programmable to create an intelligent high-precision, flexible, motion-sensing platform. The user's firmware, together with the hardware device, can make system-level decisions required for sophisticated applications, such as gesture recognition, pedometer, and e-compass tilt compensation and calibration. The FXLC95000 platform can act as an intelligent sensing hub and a highly configurable decision engine. Using the Master I2C or SPI module, the FXLC95000 platform can manage secondary sensors such as pressure sensors, magnetometers, and gyroscopes. The embedded microcontroller allows sensor integration, initialization, calibration, data compensation, and computation functions to be added to the platform, thereby off- loading those functions from the host processor. Total system power consumption is significantly reduced because the application processor stays powered down for longer periods of time. The FXLC95000CL device is programmed and configured with CodeWarrior Development Studio for Microcontroller (Eclipse IDE). This standard, integrated development environment (IDE) enables customers to quickly implement custom embedded algorithms and features to exactly match their application needs. Hardware Features 3-axis low noise accelerometer
- ±2 g, ±4 g, ±8 g configurable dynamic ranges available
- Up to 16-bit resolution
- 32-bit MCU
- Coldfire V1 CPU with MAC hardware unit
- 128K Flash, 16K RAM, 16K ROM
- 10-, 12-, 14-, and 16-bit, trimmed analog-to-digital converter (ADC) data formats available
- Master and slave, I 2C and SPI serial connectivity modules
- Sleep and low power modes to enable local power FXLC95000CL 24-LEAD LGA 3 mm by 5 mm by 1 mm Case 2208-01 Top View RGPIO14 / SCL1 RGPIO15 / SDA1 VSSIO VDDIO VDD BKGD-MS / RGPIO9 RESETB RGPIO11 / MOSI1 RGPIO10 / SCLK1 RGPIO7 / AN1+ / TPMCH1 RGPIO6 / AN0- / TPMCH0 RGPIO5 / PDB_A / INT_O VSS RGPIO4 / INT_I VSSA RGPIO8 / PDB_B VDDA RGPIO13 / SSB1 RGPIO12 / MISO1 SCL0 / RGPIO0 / SCLK VSS SDA0 / RGPIO1 / MOSI RGPIO2 / SCL1 / MISO RGPIO3 / SDA1 / SSB Pin Connections Freescale Semiconductor, Inc. FXLC95000CL Data Sheet: Technical Data Rev 1.2, 8/2013 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012–2013 Freescale Semiconductor, Inc. All rights reserved.
- Wide operating voltage and temperature range 1.71 to 3.6 V I/O supply voltage
- –40ºC to +85ºC operating temperature range
- Small package footprint
- 3 mm x 5 mm x 1 mm 24-pin LGA package
Ordering Information
Part number Temperature range Package description Shipping FXLC95000CLR1 –40°C to +85°C LGA-24 Tape and reel 2 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
4.3.2 General connections and layout
5.6 Accelerometer transducer mechanical characteristics 24
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 3 Freescale Semiconductor, Inc.
1 Typical Applications
This low-power intelligent sensor platform is optimized for a variety of applications. Mobile phones/PMP/PDA/Digital cameras
- E-Compass applications with tilt compensation
- Smartbooks/e-readers/netbooks/laptops
- Pedometers
- Gaming and toys
- Virtual-reality, 3D position feedback
- Personal navigation devices (PNDs)
- Activity monitoring in medical and fitness applications
- Security
- Fleet monitoring and tracking
- Power tools and small appliances
2 Software Support
The Xtrinsic Intelligent Sensing Framework (ISF) is a software framework built on top of Freescale’s MQX real time operating system (RTOS). ISF offers an open programming model with library support for FXLC95000CL devices. The flexibility of this open programming model allows the FXLC95000CL to be delivered ready to accept a customer’s choice of firmware images. A number of pre-built firmware images are available for download from the Freescale website, or, using CodeWarrior and ISF, a customer may create their own custom firmware image incorporating sensor processing algorithms of their own design. Sensor Adapter libraries for a number of additional Freescale sensors are also available for download enabling the FXLC95000CL to become a sensor hub. Typical Applications 4 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
3 Related Documentation
The FXLC95000CL device's features and operations are described in a variety of reference manuals, user guides, and application notes. To find the most-current versions of these documents: Go to the Freescale homepage at freescale.com. 2. In the Keyword search box at the top of the page, enter the device number FXLC95000CL. 3. In the Refine Your Result pane on the left, click on the Documentation link.
4 General Description
4.1 Functional overview
The FXLC95000CL platform consists of a three-axis, MEMS accelerometer and a mixed-signal ASIC with an integrated, 32-bit CPU. The mixed-signal ASIC can be utilized to measure and condition the outputs of the MEMS accelerometer, internal temperature sensor, or a differential analog signal from an external device. These measured values can be read at different sample rates through a subscription mechanism in the Intelligent Sensing Framework (ISF) and/or utilized internally by firmware for the FXLC95000CL device (Freescale supplied or user-written). Related Documentation Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 5 Freescale Semiconductor, Inc.
16 MHz)
Figure 1. Block diagram of the FXLC95000CL
- An Analog Front End (AFE) with:
- A capacitance-to-voltage converter
- An analog-to-digital converter
- A temperature sensor The digital sub-system is composed of:
- A 32-bit, ColdFire V1 CPU with Background Debug Module (BDM)
- Memory: RAM, ROM, and flash
- Rapid General Purpose Input/Output (RGPIO) port control logic
- Timer functions:
- Modulo Timer Module (MTIM16)
- Programmable Delay Timer (PDB)
- General-Purpose Timer/Pulse-Width Modulation Module (TPM) General Description 6 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
- I 2C master interface Queued SPI master interface (This interface has both send and receive FIFOs of size 16 bit wordlength and 4 words depth each. No DMA.)
- I 2C or SPI slave interface
- System Integration Module (SIM)
- Clock-generation module The slave interfaces (either SPI or I2C) operate independently of the ColdFire CPU subsystem. This allows the host processor to access the slave interface at any time, including while the FXLC95000CL's CPU is in low-power, deep-sleep mode. Host access can be set to trigger a FXLC95000CL CPU wakeup.
4.1.1 ROM content and usage
There are several classes of functions stored in ROM: A Boot program, including ROM-based slave port command interpreter.
- A collection of utilities which can be invoked via the ROM-based slave port command interpreter.
- ROM functions which are callable from user code using the call_trap() function. For a detailed description of these items, refer to the FXLC95000CL Hardware Reference Manual ROM chapter. The FXLC95000CL device boots from a standard routine in ROM. This boot function is responsible for a number of initialization steps (in particular the state of GPIO8 pin is checked in order to select either I2C or SPI interface as serial communication Slave port), before transferring control if desired to user code in flash memory (when the Boot from Flash bit-field has been set). The ROM contains a simple command interpreter capable of running a number of ROM-based utility and test functions. These ROM-based functions support flash memory programming and erasing, the protection of flash, the device Reset, and the reading of device information. They also provide useful error codes. The FXLC95000CL platform is supplied with a fully erased flash memory. Users can take advantage of the ROM-based flash controller and slave port command-line interpreter to communicate with a virgin device and program custom firmware into the flash array. General Description Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 7 Freescale Semiconductor, Inc.
4.2 Pinout
RGPIO5 / PDB_A / INT_O VSS RGPIO4 / INT_I VSSA RGPIO8 / PDB_B VDDA RGPIO13 / SSB1 RGPIO12 / MISO1 SCL0 / RGPIO0 / SCLK VSS SDA0 / RGPIO1 / MOSI RGPIO2 / SCL1 / MISO RGPIO3 / SDA1 / SSB Figure 2. Device pinout (top view) Table 1. Pin functions
Description
1 SCL12 RGPIO14 Master I2C Clock / RGPIO14
2 SDA13 RGPIO15 Master I2C Data / RGPIO15
3 VSSIO I/O ground
4 VDDIO I/O power supply
5 VDD Digital power supply
6 BKGD/MS RGPIO9 Background debug - Mode select / RGPIO9
7 RESETB4 Active low reset with internal, pullup resistor
8 SCL0 RGPIO0 SCLK Serial clock for slave I2C / RGPIO0 / Serial clock for slave
9 VSS Digital ground
10 SDA0 RGPIO1 MOSI Serial data for slave I2C / RGPIO1 / SPI Master Output Slave
11 RGPIO2 SCL1 MISO RGPIO2 / Serial clock for master I2C / SPI Master Input
12 RGPIO3 SDA1 SSB RGPIO3 / Serial data for master I2C / SPI slave select
13 RGPIO4 INT_I RGPIO4 / Interrupt input
14 VSS Must be connected to GND externally
15 RGPIO5 PDB_A INT_O RGPIO5 / PDB_A / Interrupt output
Table continues on the next page... General Description 8 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
Table 1. Pin functions (continued)
16 RGPIO6 AN0- TPMCH0 RGPIO6 / ADC Input 0 / TPM Channel 0
17 RGPIO7 AN1+ TPMCH1 RGPIO7 / ADC Input 1 / TPM Channel 1
18 SCLK1 RGPIO10 master queued SPI clock / RGPIO10
19 MOSI1 RGPIO11 master queued SPI Master Output Slave Input / RGPIO11
20 MISO1 RGPIO12 master queued SPI Master Input Slave Output / RGPIO12
21 SSB1 RGPIO13 master queued SPI slave select / RGPIO13
22 VDDA Analog power
235 RGPIO8 PDB_B RGPIO8 / PDB_B
24 VSSA Analog ground
- Default Pin Function 1 represents the reset state of the device. Pin functions may be changed via the SIM pin mux- control registers. Drive strength and pullup controls are programmed by the port control registers. 2. SCL1 is available for use on pin (RGPIO14) only when SIM_PMCR1[A2] is not equal to "01". That setting would enable it for pin 11 (RGPIO2). 3. SDA1 is available for use on pin (RGPIO15) only when SIM_PMCR1[A3] is not equal to "01". That setting would enable it for pin 12 (RGPIO3). 4. RESETB defaults to input only, but can be configured as an open-drain, bidirectional pin. 5. GPIO8/PDB_B = LOW at startup indicates that SPI should be used as slave instead of the I 2C module.
4.2.1 Pin function description
Descriptions of the pin functions available on this device are provided in this section. Sixteen of the device pins are multiplexed with Rapid GPIO (RGPIO) functions. The Default Pin Function column of Table 1 lists which function is active when the device exits the reset state. User firmware can use the Pin Mux Control registers in the System Integration Module (SIM) to change pin assignments for these pins after reset. VDDIO and VSSIO I/O power and ground. VDDIO ranges from 1.71V to 3.6V for this device. The device will not load the I2C bus if VDDIO is not connected. Parasitic paths to supply this power domain from other pins is not recommended. VDD and VSS Digital power and ground. VDD is nominally 1.8V for this device. Parasitic paths to supply this power domain from other pins is not recommended. VDDA and VSSA General Description Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 9 Freescale Semiconductor, Inc.
Analog power and ground. VDDA is nominally 1.8V for this device. It is recommended that this supply voltage be filtered to remove any digital noise that may be present on the supply. RESETB The RESETB pin is an open-drain, bidirectional pin. At power up, it is configured strictly as an input pin. Setting RCSR[DR] (Reset Control & Status Register “Drive Reset” bit) to one will cause the RESET function to become bidirectional. Using this feature, FXLC95000CL can reset external devices whenever it is reset for any purpose other than power-on-reset. Slave I2C: SDA0, SCL0 Slave I2C data and clock signals. FXLC95000CL may be controlled via this serial port or via the slave SPI interface. At reset, SDA0 and SCL0 are open-drain, bidirectional in input mode, with the pullup resistor disabled. Master I2C: SDA1, SCL1 Master I2C data and clock signals. Because the FXLC95000CL contains a 32-bit ColdFire V1 CPU, it is fully capable of mastering other devices in the system via this serial port. State at reset: active. SCL1 and SDA1 are configured on pins 1 and 2, respectively. The alternate functionality on these pins is RGPIO14 and RGPIO15. Analog-to-Digital Conversion: AN0, AN1 The on-chip ADC can be used to perform a differential analog-to-digital conversion based upon the voltage present across pins AN0(-) and AN1(+). Conversions for these pins are at the same Sample Data Rate (SDR) as the MEMS transducer signals. State at reset: Inactive. AN[1:0] are secondary functions on RGPIO[7:6], which own the pins at reset. Rapid General Purpose I/O: RGPIO[15:0] The ColdFire V1 CPU has a feature called “Rapid GPIO” or RGPIO. This is a 16-bit input/output port with single-cycle write, set, clear, and toggle functions available to the CPU. The FXLC95000CL brings out all 16 bits of that port as pins of the device. State at reset: RGPIO[15:14]: inactive. SDA1 and SCL1 own the pin at reset. General Description 10 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
- RGPIO[13:10, 8:2]: Pin mux registers for these bits are configured as RGPIO. Pullups are disabled. RGPIO functionality can be enabled via RGPIO_ENB[13:10, 8:2]. RGPIO[9]: Inactive. BKGD/MS owns the pin at reset
- RGPIO[1:0]: inactive. SDA0 and SCL0 own the pin at reset. Configuration details:
- RGPIO[15:14] are configured as Master I 2C port at reset when RGPIO_ENB[15:14]=00 and PMCR[A3]=PMCR[A2]=00 or 10. They can only be configured as RGPIO when PMCR[A3]=PMCR[A2]=01. RGPIO_ENB[15:14] must also be set to 11 for them to assume RGPIO functionality.
- RGPIO_ENB[13:10] are used to configure RGPIO[13:10].
- Pin function selections are made via the SIM pin mux registers for RGPIO[9:0]. Interrupts: INT_I This input pin may be used to wake the CPU from a deep-sleep mode. It can be programmed to trigger on either rising or falling edge or high or low level. This pin operates as a level 7 (high priority) interrupt. Interrupts: INT_O RGPIO5 (pin 11) can be configured to function as an interrupt output pin. This interrupt can be asserted via software when a command response packet has been stored on the slave port mailboxes and is ready for the host to read. The host will see the interrupt and can read the data from the FXLC95000CL platform. The FXLC95000CL will automatically clear the interrupt once it recognizes that the response packet is being transmitted. This clearing action occurs while the packet is being read and prevents the host from falsely recognizing the same interrupt after the packet read is complete. State at reset: Pin muxing is set to RGPIO5 mode. Debug/Mode Control: BKGD/MS At power-up, this pin operates as Mode Select. If low during power-up, the CPU will boot into debug halt mode. If high, the CPU will boot normally and run code. After power-on reset, this pin operates as a bidirectional, single-wire Background Debug port. CodeWarrior uses the Background Debug port to download code into on-chip RAM and flash, and for debugging that code using breakpoints and single stepping. State at reset: Mode Select (MS). MS = 1'b0, at exit from reset → boot to debug halt mode. General Description Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 11 Freescale Semiconductor, Inc.
MS = 1'b1, at exit from reset → boot to run mode. State after reset: BKGD. The BKGD pin is a bidirectional, pseudo-open-drain pin used for communications with a debug environment. Programmable Delay Block: PDB_A, PDB_B These are the two outputs of the programmable delay block (PDB). Normally, the PDB is used to schedule internal events at some fixed interval(s) relative to start of either the analog or digital phase. By bringing the PDB outputs to these pins, it becomes possible for the FXLC95000CL to initiate some external event, also relative to start of analog or digital phase. For more information, refer to the FXLC95000CL Hardware Reference Manual. Timer: TPMCH0 and TPMCH1 These pins are the outputs for a general modulo 16 timer and general input/output capture (TPM) and pulse width modulation (PWM) functions. Slave SPI Interface: SCLK, MOSI, MISO, SSB Slave SPI clock, master-output slave-input, master-input slave-output, and slave-select signals. The FXLC95000CL may be controlled via this serial port or via the slave I2C interface. State at reset: In reset, these pins are configured according to I2C and RGPIO[3:2] functions listed above. The pin may be reconfigured for SPI use as part of the boot process. Master SPI Interface: SCLK1, MOSI1, MISO1, SSB1 Master SPI clock, master-output slave-input, master-input slave-output, and slave-select signals. State at reset: In reset, these pins are configured as RGPIO[13:10] functions listed above.
4.3 System connections
The FXLC95000CL platform offers the choice of connecting to a host processor through either an I2C or SPI interface. It can also act as a master controller for I2C or SPI peripherals and analog sensors. General Description 12 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
4.3.1 Power supply considerations
- An internal circuit powered by V DDA provides the FXLC95000CL with a power- on-reset signal. For this signal to be properly recognized, it is important that VDD is powered up before or simultaneously with VDDA. The voltage potential difference between VDD and VDDA must not exceed ±0.1 V. The simplest way to accomplish this is to power both pins from the same voltage source.
- When using the same voltage source, some digital noise might reach the analog section. To prevent this, connect a small inductor or ferrite bead in serial with both the VDDA and VSSA traces. Additionally, two ceramic capacitors (of approximately 1 µF, and 100 nF, respectively) can be used to efficiently bypass the power and ground of both digital and analog supply rails.
- V DDIO must rise up before or simultaneously with VDDA/VDD.
4.3.2 General connections and layout recommendations
- Provide a low-impedance path from the board power supply to each power pin (VDD, VDDA, and VDDIO) on the device and from the board ground to each ground pin (VSS, VSSA, and VSSIO). The minimum bypass requirement is to place 0.01 – 0.1 μF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/ VSSA. Ceramic and tantalum capacitors tend to provide better tolerances.
- Ensure that capacitor leads, associated printed circuit traces, and vias that connect to the chip VDD and VSS (GND) pins are as short as possible.
- Bypass the power and ground. It is suggested that a high-frequency bypass capacitor be placed close to and on each power pin. Bulk capacitance also is suggested, with it evenly distributed around the power and ground planes of the board.
- Take special care to minimize noise levels on the VDDA and VSSA pins. An isolation circuit consisting of a Ferrite Bead and capacitors is suggested, to ensure that the voltage supplying the analog input is noise free.
- Use separate power planes for VDD and VDDA and separate ground planes for VSS and VSSA. Connect the separate analog and digital power and ground planes as close as possible to power supply outputs. If both analog circuit and digital circuit are powered by the same power supply, it is advisable to connect a small inductor or ferrite bead in serial with both VDDA and VSSA traces. General Description Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 13 Freescale Semiconductor, Inc.
- It is highly desirable to physically separate analog components from noisy digital components by ground planes. Do not place an analog trace in parallel with digital traces. It is also desirable to place an analog ground trace around an analog signal trace to isolate it from digital traces. If in-circuit debug capability is desired, provide an interface to the BKGD/MS pin.
- Select resistors R2 and R3 in Figure 3 to match requirements stated in the I 2C standard. An example value of 4.7kΩ is appropriate for the configuration shown.
- Use the PCB footprint, solder mask, and solder stencil shown in Footprint and pattern information.
4.3.3 I 2C reset considerations
If there is a reset during a slave I2C read transaction, then the slave device state machine will hang the bus, because it is waiting for the master clock. The host-driven reset signal provides an external way to reset the I2C state machine.
4.3.4 FXLC95000CL as an intelligent slave
I2C pullup resistors, a ferrite bead, and a few bypass capacitors are all that are required to attach this device to a host platform. The basic configuration of the I2C interface is shown in Figure 3. The voltage level on pin 23 (RGPIO8) selects the slave-port format: I2C or SPI. The RGPIO pins can also be programmed to generate interrupts to the host platform, in response to the occurrence of application events. In this case, the pins should be routed to the external interrupt pins of the host processor. General Description 14 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
Quiet VDDA for best performance. Figure 3. FXLC95000CL as a slave (I2C interface) interrupt pins of the host processor. Freescale Semiconductor, Inc.
1.8 VVDDIO VDDIO
Quiet VDDA for best performance . Figure 4. FXLC95000CL as a slave (SPI interface)
4.3.5 FXLC95000CL as a sensor hub
16 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
Intelligent Sensing Platform can interface and manage almost any type of sensor, digital or analog, such as pressure sensors, magnetometers, gyroscopes, and humidity sensors. The system supports external sensors interfacing to FXLC95000CL concurrently, via a combination of master SPI and master I2C interfaces, and external differential analog inputs. Besides FXLC95000CL rich connectivity, the 32-bit core and hardware Multiply Accumulator (MAC) provide the processing power to collect, manipulate and fuse all sensors measurement locally and make appropriate decisions to optimize overall system power consumption. For example, FXLC95000CL can be programmed to operate effectively as a power controller for handheld units by enabling the host platform to put itself to sleep, with confidence that the FXLC95000CL will issue a wake-up request when an external event requires the host's attention. Figure 5 shows the FXLC95000CL being used in this sensor hub configuration. Note the simple connections. Only a few bypass capacitors, a ferrite bead, and pullup resistors for the I2C buses are required. Slave I2C interface is dedicated to communication with the host processor. Interrupt output line INT_O can be involved as well.
- Master SPI, Master I 2C, AN0/AN1 and interrupt input line INT_I are available to interface a variety of external sensors General Description Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 17 Freescale Semiconductor, Inc.
1.8 V Slave interface select
Quiet VDDA for best performance.
1.8 V VDDIO
Figure 5. FXLC95000CL as a sensor hub (I2C interface) 18 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
Quiet VDDA for best performance . Figure 6. FXLC95000CL as a sensor hub (SPI interface) Freescale Semiconductor, Inc.
4.4 Sensing direction and output response
Figure 7. Sensing direction and output response Table 2. ± 1 g field-measured results
- Measured data in counts (16-bit word) after trimming.
5 Mechanical and Electrical Specifications
DC/AC electrical characteristics, and AC timing specifications. 20 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
5.1 Definitions
cross-axis sensitivity The proportionality constant that relates a variation of accelerometer output to cross acceleration. This sensitivity varies with the direction of cross acceleration and is primarily due to misalignment. deep-sleep mode The device’s lowest power state, when the system clock is stopped and the device performs no functions. In this mode, only a few exception events can wake the device. full range The maximum level of acceleration supported by the accelerometer's output signal, typically specified in ±g. For example, the output of an accelerometer program in ±2 g mode will be linear when subjected to accelerations within ±2 g. If the acceleration is larger than ±2 g, the output will not be linear and may rail. hardware compensated Sensor modules on this device include hardware correction factors for gain and offset errors which are calibrated during factory test using a least-squares fit of the raw sensor data. nonlinearity A measurement of deviation from perfect sensitivity. Ideally, the relationship between input and output is linear and described by the sensitivity of the device. pin group Device pins are clustered into a number of logical pin groupings in order to simplify and standardize electrical data sheet parameters. Pin groups are defined in Table 6. sensitivity Describes the gain of the sensor and can be determined by applying a 1 g acceleration to it, such as the earth's gravitational field. The sensitivity of the sensor can be determined by subtracting the -1 g acceleration value from the +1 g acceleration value and dividing by two. software compensated In addition to the first-order hardware gain and offset calibration features, Freescale implements advanced, nonlinear calibration functions to improve sensor performance. warm-up time The time—from the initial application of power—for a sensor to reach specified performance under specified operating conditions. zero-g offset Describes the deviation of an actual output signal from the ideal output signal, if no acceleration is present. The expected ideal output signal, in this case, would be zero. A deviation from ideal value is called zero-g offset. Offset is, to some extent, a result of stress on the MEMS sensor and, therefore, the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress.
5.2 Absolute maximum ratings
Absolute maximum ratings are stress ratings only and functional operation at the maximum ratings is not guaranteed. Stress beyond the limits specified here may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. Mechanical and Electrical Specifications Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 21 Freescale Semiconductor, Inc.
logic voltage level (for instance, either VSS or VDD). Table 3. Absolute maximum ratings Table 4. ESD and latch-up protection characteristics This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. This is an ESD sensitive device, improper handling can cause permanent damage to the part. 22 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
5.3 Operating conditions
Table 5. Nominal operating conditions
5.4 General DC characteristics
Table 6. DC characteristics
- All conditions at nominal supply: V DD = VDDA = 1.8 V and VDDIO = 3.3 V.
Freescale Semiconductor, Inc.
5.5 Supply current characteristics
Table 7. Supply current characteristics
- All conditions at nominal supply: V DD = VDDA = 1.8 V and VDDIO = 3.3 V.
- STOP NC: Stop mode, no clock.
- STOP SC: Stop mode, slow clock.
- RUN: Normal fast mode. Total current with the analog section active, 16 bits ADC resolution selected, MAC unit used,
and all peripheral clocks enabled.
5.6 Accelerometer transducer mechanical characteristics
Table 8. Accelerometer characteristics Table continues on the next page... 24 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
Table 8. Accelerometer characteristics (continued)
- All conditions at nominal supply: V DD = VDDA = 1.8V and VDDIO = 3.3V.
- ODR: Output Data Rate or the sampled data rate of the system.
- Performance specification is with CPU being inactive during sensor data acquisition
5.7 Temperature sensor characteristics
Table 9. Temperature sensor characteristics
- All conditions at nominal supply: V DD = VDDA = 1.8 V and VDDIO = 3.3 V.
5.8 ADC characteristics
Table 10. ADC characteristics
- All conditions at nominal supply: V DD = VDDA = 1.8 V, VDDIO = 3.3 V, and RES = 14 unless otherwise noted.
- The external ADC input pins go through a buffer line that is powered by V DDIO. Noise on the VDDIO line degrades the
Freescale Semiconductor, Inc.
5.8.1 ADC Sample Rates
The system clock is 16 MHz with the first sample rate generated by dividing the system clock by 4096 (16 MHz / 4096 = 3906.25 Hz). Subsequent sample rates are all a sequence of divide-by-two. The FXLC95000CL platform's internal frame timer supports the following sample rates (frames per second (fps)): 3906.25 fps 1953.13 fps 976.56 fps 488.28 fps 244.14 fps 122.07 fps 61.04 fps 30.52 fps 15.26 fps 7.63 fps 3.81 fps 1.91 fps 0.95 fps 0.48 fps 0.24 fps Notes At the fastest sampling rate of 3906.25 Hz, there is not enough time to complete the ADC conversions’ highest- bit resolution, so only 10-,12-,and 14-bit resolutions are available at that rate. All of the ADC resolutions (10-,12-, 14-, and 16-bit) are available at all other sample rates.
- Freescale's Intelligent Sensor Framework (ISF) uses the software-triggered sample mode, using the MTIM16 timer to set the sample period. This allows the specification of sample periods to microsecond resolution. Mechanical and Electrical Specifications 26 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
5.9 AC electrical characteristics
Figure 8. Input signal measurement references
- Data Tri-stated, when a bus or signal is placed in a high impedance state
- Data Valid state, when a signal level has reached V OL or VOH
- Data Invalid state, when a signal level is in transition between V OL and VOH
Figure 9. Signal states
5.10 General timing control
Table 11. General timing characteristics Table continues on the next page... Freescale Semiconductor, Inc.
Table 11. General timing characteristics (continued)
- All conditions at nominal supply: V DD = VDDA = 1.8 V and VDDIO = 3.3 V.
- Time measured from V DD = VPOR until the internal reset signal is released.
- T = Period of one system clock cycle. In full-speed mode, T is nominally 62.5 ns. In slow-speed mode, T is
5.11 Interfaces
intended to be used to communicate with other, external sensors. Figure 10. I2C standard and fast-mode timing 28 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
5.11.1 Slave I 2C
Table 12. I 2C speed ranges
- The maximum t HD;DAT must be at least a transmission time less than tVD;DAT or tVD;ACK. For details, see the I2C
- Timing met with IFE = 0, DS = 1, and SE = 1. For more information, refer to Port Control Registers in the
FXLC95000CL Hardware Reference Manual.
5.11.2 Master I 2C Timing
The master I2C should only be used when the system clock is running at full speed. Table 13. Master I 2C timing this period, the first clock pulse is generated.
- The master mode I 2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
- The maximum t HD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
Freescale Semiconductor, Inc.
- Set-up time in slave-transmitter mode is 1 system-clock period (16 MHz = 62.5 ns). There is no FIFO on the I 2C.
- A fast-mode, I 2C bus device can be used in a standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns before the SCL line is released.
5.11.3 SPI interfaces (slave and master)
Figure 11 and Table 14 describe the timing requirements for the SPI system. Not defined—normally the MSB of the character just received. Figure 11. Slave and master SPI timing Table 14. Slave and master SPI timing
1 SCLK period tSCLK 4 — tCYCH
4 Clock (SCLK) high or low time tWSCLK 200 — ns
Table continues on the next page... 30 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
Table 14. Slave and master SPI timing (continued)
5 Data set-up time (inputs) tSU 15 — ns
6 Data hold time (inputs) tHI 25 — ns
7 Access time ta — 25 ns
8 MISO Disable Time tdis — 25 ns
9 Data valid (after SCLK edge) tv — 25 ns
10 Data hold time (outputs) tHO 0 — ns
11 Rise time
12 Fall time
5.12 Flash parameters
voltage of 1.8 V is sufficient for the flash programming voltage. programmed is 256 bytes and the block must start at a 256-byte boundary. Table 15. Flash parameters Freescale Semiconductor, Inc.
6 Package Information
The FXLC95000CL is contained in a 24 pin, 3 mm by 5 mm by 1 mm LGA package.
6.1 Product Identification Markings
Package Information
32 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
6.2 Footprint and pattern information
Notes: 1. All measurements are in millimeters . . There is a 0.015 mm shrink on each direction from Copper footprint . 2.2256 8 9 10 11 12 20 21 23 24 + + 0.350 0.250 0.100 0.100 0.250 0.500 0.375 Package footprint 0.500 1.225 PCB Copper pattern 0.650 0.250 0.250 + + 1.375 2.375 PCB solder-mask pattern 0.850 3.450 0.850 0.225 2.450 1.375 2.375 PCB stencil pattern(2) 0.220 0.620 2.375 1.375 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 33 Freescale Semiconductor, Inc.
3.000 5.600 ++ + + + 5.000 3.600 + ++ + + 0.015 Zoom-in drawing ++ + + + 0.200 0.100 0.225 0.250 0.100 Note: All measurements are in millimeters . 34 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
6.3 Tape and reel information
6.3.1 Tape dimensions
Notes : 1. Measured from center line of sprocket hole to center line of pocket. . Cumulative tolerance of 10 sprocket holes is +0.20. 3. Other material available. 4. All dimensions in millimeters , unless otherwise stated. (1) (2) (1)
6.3.2 Device orientation
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 35 Freescale Semiconductor, Inc.
6.4 Package dimensions
Case 2208-01, Issue O, 24-lead LGA 36 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc.
7 Revision History
1.0 May 2013 Initial Public Release
1.1 August
- Changed Zero-g level change versus temperature (TC Off) specification in Table 8 Added RMS noise specification for ±2 g and ±8 g in Table 8
- Removed footnote in Table 9
- Restated non-linearity in different units (% FSR) in Table 9
1.2 August
- Changed Zero-g level change versus temperature (TC Off) specification in Table 8. Changed Sensitivity TSENS specification in Table 9.
Revision History
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 37 Freescale Semiconductor, Inc.
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