FXLA2203 ONSEMI | Alldatasheet
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© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FXLA2203 Rev. 1.0.5 FXLA2203 — Dual-Mode, Dual-SIM-Card Level Translator FXLA2203 Dual-Mode, Dual-SIM-Card Level Translator
Features
Easy-to-Use “Single Pin” SIM Card Swap Control Channel Swap Time: 130ns (Typical) Simultaneous Dual-Mode, Dual-SIM Communication Host Ports: 1.65V to 3.6V Voltage Translation Card Ports: 1.65V to 3.6V Voltage Translation Leverages the Presence of Existing PMIC LDOs ISO7816 Compliant Power Switch RON: 0.5Ω (Typical) Supports Class B 3V SIM / UIM Cards Supports Class C: 1.8V SIM / UIM Cards Non-Preferential Host VCC Power-Up Sequencing Activation / Deactivation Timing Compliant per ISO7816-03 Internal Pull up Resistors for Bi-Directional I/O Pin Outputs Switch to 3-State if Host VCC at GND Power-Off Protection Packaged in 24-Terminal UMLP (2.5mm x 3.5mm) Direction Control Not Needed
Applications
Dual-Mode Dual-SIM Applications GSM, CDMA, WCDMA, TDSCDMA CDMA2000, 3G Cellular Phones Mobile TV: OMA BCAST
Description
The FXLA2203 allows either two hosts to simultaneously communicate with two Subscriber Identity Modules (SIM), or two User Identity Modules (UIM). Dual Mode refers to the mobile phones that are compatible with more than one form of data transmission or network (such as GSM, CDMA, WCDMA, TDSCDMA, or CDMA2000), resulting in a dual-baseband processor configuration. In a dual-mode application, the FXLA2203 host ports interface directly with the baseband processors (see Figure 9). The bi-directional I/O open-drain channel features auto- direction and internal 10KΩ pull-up resistors. RST and CLK provide unidirectional translation from host to card only. Either host can swap SIM slot s with the assertion of a single control pin: CH_Swap. The typical channel swap time is 130ns. The FXLA2203 does not contain internal Low Dropout Regulator (LDOs). Instead, the FXLA2203 architecture incorporates two low-R ON internal power switches for routing existing PMIC (Power Management Integrated Circuit) LDOs to individual SIM slots. This reduces overall system power, leverages existing LDO system resources, and aligns with the philosophy that centralizing LDOs in the PMIC facilitates power management. Since the FXLA2203 does not block the LDO function to the SIM ca rd, existing activation / deactivation timing transparency is maintained between Hosts, PMICs, and SIM cards. The device allows voltage translation from as high as 3.6V to as low as 1.65V. Each port tracks its own port power supply.
Ordering Information
Temperature Range Package Packing Method FXLA2203UMX -40 to 85°C 24-Terminal, 2.5mm x 3.4mm Ultrathin Molded Leadless Package (UMLP), 0.4mm Pitch Tape and Reel
Figure 1. Block Diagram
- V CC must always be greater than or equal to (≥ ) VCC1 and VCC2.
- Hybrid driver explained in detail in Figure 12 - I/O Pin Functional Diagram.
- See Table 2 for CH_Swap truth table.
Figure 2. Top Through View Figure 3. Bottom View
1 NC NC No Connection
2 VCC1 I Power Supply 1 Input: Coming from PMIC 1 LDO
3 VCC_Card1 O Power Output for Card Slot 1
4 GND GND Ground
5 VCC_Card2 O Power Output for Card Slot 2
6 VCC2 I Power Supply 2 Input: Coming from PMIC 2 LDO
7 RST_2 O Reset Output to Card Slot 2
8 I/O_2 I/O Data I/O for Card Slot 2; Open Drain
9 CLK_2 O Clock Output to Card Slot 2
10 CLK_H_2 I Clock Input of Host Interface 2
11 RST_H_2 I Reset Input of Host Interface 2
12 I/O_H_2 I Data I/O of Host Interface 2; Open Drain
13 VCC_H_2 Supply Power Supply of Host Interface 2
14 GND GND Ground
15 V CC Supply Power Supply of Control Pins: EN and CH_Swap
card slots. Connect to VCC if not used. Default level after power up is LOW.
17 Ch_Swap I
18 VCC_H_1 Supply Power Supply of Host Interface 1
19 I/O_H_1 I/O Data I/O of Ho st Interface 1; Open Drain
20 RST_H_1 I Reset Input of Host Interface 1
21 CLK_H_1 I Clock Input of Host Interface 1
22 CLK_1 O Clock Output to Card Slot 1
23 I/O_1 I/O Data I/O for Card Slot 1; Open Drain
24 RST_1 O Reset Output to Card Slot 1
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FXLA2203 Rev. 1.0.5 4 FXLA2203 — Dual-Mode, Dual-SIM-Card Level Translator Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may dam age the device. The device may not function or be operable above the recommended operating conditions and st ressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Conditions Min. Max. Unit VCC Supply Voltage VCC -0.5 5.0 V VCC_H_n, VCCn -0.5 4.6 V VIN DC Input Voltage Host Ports and Card Ports -0.5 4.6 V Control Input (EN and CH_Swap) -0.5 5.0 VO Output Voltage(4) Output 3-State -0.5 4.6 V Output Active (Host Port) -0.5 V CC +0.5 Output Active (Card Port) -0.5 V CC +0.5 IIK DC Input Diode Current V I<0V -50 mA IOK DC Output Diode Current VO<0V -50 mA VO>VCC +50 IOH/IOL DC Output Source / Sink Current (4) -50 +50 mA ICC DC VCC or Ground Current (per Supply Pin) ±100 mA TSTG Storage Temperature Range -65 +150 °C PDISS Power Dissipation at 5MHz 0.57 W ESD Electrostatic Discharge Capability Human Body Model, JESD22-A114(5) Card Side Pins 3-5, 7-9, 14, 22-24 9 kV All Other Pins 3 Charged Device Model, JESD22-C101 Card Side Pins 3-5, 7-9, 14, 22-24 2 All Other Pins 2 Notes: 4. I O absolute maximum ratings must be observed. 5. Human Body Model (HBM): R=1500 Ω , C=100pF. Recommended Operating Conditions The Recommended Operating Conditions table defines th e conditions for actual device operation. Recommended operating conditions are specified to en sure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Conditions Min. Max. Unit VCC Power Supply (6) VCC 1.65 4.35 V VCC_H_n, VCCn 1.65 3.60 V VIN Input Voltage(7) Host Port 0 3.6 V Card Port 0 3.6 V VOUT Output Voltage (7) Host Port 0 3.6 V Card Port 0 3.6 V Host Port I/O Pin 0 VCC_H_n +0.3V V Card Port I/O Pin 0 VCCn +0.3V V TA Operating Temperature, Free Air -40 +85 °C dt/dV Input Edge Rate RST and CLK 10 ns/V Θ JA Junction-to-Ambient Thermal Resistance 52.1 C/W Notes: 6. V CC must always be equal to, or greater than, VCC1 and VCC2. 7. All unused inputs and input/outputs must be held at their respective V CC or GND.
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FXLA2203 Rev. 1.0.5 5 FXLA2203 — Dual-Mode, Dual-SIM-Card Level Translator TA=-40°C to +85°C; pins I/O_1, I/O_2, I/O_H_1, I/O_H_2 (open drain). Symbol Parameter Conditions V CC_H_n (V) V CCn (V) Min. Typ. Max. Unit VIH_host High-Level Input Voltage Data Inputs of VCC_H_n V VIH_card Data Inputs of VIL_host Low-Level Input Voltage Data Inputs of VIL_card Data Input of VCCn V VOH_host High-Level Output Voltage VCC_H_n V VOL_host Low-Level Output Voltage VOL_host Low-Level Output Voltage IOL=1mA, VOL_card IOL=1mA, VOL_host Low-Level Output Voltage IOL=1mA, VOL_card IOL=1mA, IOFF Power-Off Leakage Current VO=0V to 3.6V Host and Card Sides 3.60 0 ±1.0 µA IOZ 3-State Output Leakage VO=0V or 3.6V, EN=GND, Host and Card Sides 3.60 3.60 ±1.0 µA IOZ 3-State Output Leakage VO=0V or 3.6V, EN=1, Host and Card Sides 0 3.60 ±1.0 µA Rpull_up Internal Pull-Up Resistor 1.65 – 3.60 1.65 - 3.60 9 10 11 KΩ
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FXLA2203 Rev. 1.0.5 6 FXLA2203 — Dual-Mode, Dual-SIM-Card Level Translator TA=-40°C to +85°C; pins EN, CH_Swap. Symbol Parameter Conditions V CC (V) Min. Max. Unit VIL Low-Level Input Voltage 3.60 0.65 V 1.80 0.45 V VIH High-Level Input Voltage 3.60 1.2 V 1.80 0.9 V IL Input Leakage Current VI=VCC or GND, I/O Floating 1.65 – 3.60 ±1 µA ICCT Increase in ICC per Pin VIN=1.8V 3.60 12 µA VIN=0.9V 1.80 10 µA TA=-40°C to +85°C; pins RST_1, RST_2, RST_H_1, RST_H_2, CLK_1, CLK_2, CLK_H_1, CLK_H_2. Symbol Parameter Conditions V CC_H_n (V) V CCn (V) Min. Typ. Max. Unit VIL Low-Level Input VCC_H_n V VIH High-Level Input VCC_H_n V VOL Low-Level Output VCCn V VOH High-Level Output VCCn V II Input Leakage Current VI=VCC or GND 1.65 – 3.60 3.60 ±1 µA IOFF Power-Off Leakage Current VO=0V to 3.6V 3.60 0 ±1 µA IOZ 3-State Output Leakage VO=0V or 3.6V, EN=GND 3.60 3.60 ±1 µA VO=0V or 3.6V, EN=1 0 3.60 ±1 ICC Quiescent Supply Current VI=VCC or GND; IO=0, EN=VCC, I/O Floating 1.65 – 3.60 1.65 – 3.60 3 µA ICCZ Power-Down Supply Current VI=VCC or GND; IO=0, EN=GND 1.65 – 3.60 1.65 – 3.60 3 µA RONPS Power Switch On Resistance, EN=1 ION=50mA, VCCn to VCC_Cardn ROFPS Power Switch OFF Resistance, EN=0 CH_Swap=0 and
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FXLA2203 Rev. 1.0.5 7 FXLA2203 — Dual-Mode, Dual-SIM-Card Level Translator AC Characteristics Card Port (RST, CLK) Unless otherwise specified, output load: CL=30pF, RL ≥ 1MΩ; TA=-40°C to +85°C; VCCn=1.65V to 3.60V. Symbol Parameter Typ. Max. Unit tr Output Rise Time Card Port (8,10) 1 5 ns tf Output Fall Time Card Port (9,10) 1 5 ns Notes: 8. See Figure 6. 9. See Figure 7. 10. t r, tf guaranteed by characterization; not production tested. Host and Card Port (I/O Only) Unless otherwise specified, output load: CL=30pF, RL≥1MΩ, and open-drain outputs; TA=-40°C to +85°C; VCCn=1.65V to 3.60V; and VCC_H_n=1.65V to 3.60V. Symbol Conditions Parameter Typ. Max. Unit tr (11,13) Open Drain Inputs with 500µA ISINK (13) Output Rise Time Card Port (10% - 90%) 200 500 ns tf (12,13) Output Fall Time Card Port (90% - 10%) 2.5 4.0 ns tr (11,13) Output Rise Time Host Port (10% - 90%) 200 500 ns tf (12,13) Output Fall Time Host Port (90% - 10%) 2 3 ns Notes: 11. See Figure 6. 12. See Figure 7. 13. t r, tf guaranteed by characterization; not production tested. VCC_H_n=1.65V to 3.60V(16) Unless otherwise specified, TA=-40°C to +85°C and VCCn=1.65V to 3.60V. Symbol CH_Swap Direction Path Typ. Max. Unit tswap HL, LH Host Card RST, CLK, I/O and Power Switches 130 400 ns Notes: 14. 15. 16. The power switch swap time assumes no decoupling capacitors on the VCC_Card pins. 17. t swap is the time required for the CH_Swap pin to swap host to SIM slot connections. 18. The I/O pin swap time assumes a push / pull driver; other wise, the rise time (RC time constant) of an open-drain driver masks the actual I/O pin switch time. Maximum Frequency(19) Unless otherwise specified, CLK (Host to Card), TA=-40°C to +85°C, and card port VCCn=1.65V to 3.60V. Host Port: VCC_H_n CH_Swap Minimum Unit 1.6V to 3.6V 1 30 MHz 0 30 Note: 19. Maximum frequency is guaranteed but not tested. Power Dissipation Capacitance TA=+25°C. Symbol Parameter Conditions Typical Unit Cpd Power Dissipation Capacitance VCC_H_n=VCCn=VCC=3.3V, VI=0V or VCC, CH_Swap=1, CLK1 and CLK2 Switching at 5MHz 23 pF
Table 2. Dual-Mode, Dual-SIM Truth Table voltage translation across all four VCC domains. Figure 11. Voltage Translation Table 3. Translation Truth Table
- V CC must always be greater than or equal to (≥ ) VCC1 and VCC2.
Table 4. Power Supply Pins
1 VCC EN and CH_Swap Supply
2 VCC_H_1 Host 1 Supply
3 VCC_H_2 Host 2 Supply
4 VCC1 Power Switch 1 Input
5 VCC2 Power Switch 2 Input
however, VCC must be higher or equal to V CC1 and VCC2. up to valid supply voltages or ramp down to 0V.
- Assert EN LOW (FXLA2203 disabled).
- Apply power to VCC1, VCC2, VCC_H_1, and
- Assert EN HIGH (FXLA2203 enabled).
- Begin activation timing (see Figure 14).
- Complete deactivation timing (see Figure 15).
- Assert EN LOW (FXLA2203 disabled).
- Ramp down power to VCC1, VCC2, VCC_H_1,
- Once VCC1 and VCC2 ar e OFF, ramp down VCC.
Figure 16. Power-Up Sequencing Figure 17. Power-Down Sequencing
- A=VCC becomes a valid voltage, EN=LOW.
- B=VCC1, VCC2, and VCC_H_n become valid
- C=FXLA2203 enabled (EN goes HIGH), ready for
- A=Disable FXLA2203, bring EN LOW.
- B=Ramp down VCC1, VCC2, and VCC_H_n.
- C=Ramp down VCC once VCC1 and VCC2 are off.
Table 5. Power Supply Pins
6 VCC EN and CH_Swap Supply
7 VCC_H_1 Host 1 Supply
8 VCC_H_2 Host 2 Supply
9 VCC1 Power Switch 1 Input
10 VCC2 Power Switch 2 Input
higher or equal to VCC1 and VCC2. LDO voltage assigned to that SIM slot. SIM slot direction. I/O is a bi -directional, open drain pin. Internal 10KΩ pull-up resistors are provided. equal to or greater than VCC1 and VCC2. drivers on the host sides and the card sides. Table 7. Note that VCC must be > voltage levels of CLK_2, RST_2 and I/O_2. voltage levels of CLK_1, RST_1, and I/O_1. Table 6. Power Switch Truth Table Table 7. Signal Truth Table
supplies are active (1.65V – 3.6V). VCC1 and VCC_H_1 are both active (1.65V – 3.6V). voltage levels of CLK_2, RST_2, and I/O_2. and signal combinations, see Table 8. Table 8. Complete Power Switch and Signal Truth Table
1 OFF X X X X OFF OFF Z Z OFF OFF
2 ON L X X X X X Z Z Z Z
3 ON H 1 OFF OFF OFF OFF Z Z OFF OFF
4 ON H 1 OFF OFF ON OFF Z Z ON OFF
5 ON H 1 OFF OFF OFF ON Z Z OFF ON
6 ON H 1 OFF OFF ON ON Z Z ON ON
7 ON H 1 OFF ON OFF OFF Z Z OFF OFF
8 ON H 1 OFF ON ON OFF Z Z ON OFF
9 ON H 1 OFF ON OFF ON Z A OFF ON
10 ON H 1 OFF ON ON ON Z A ON ON
11 ON H 1 ON OFF OFF OFF Z Z OFF OFF
12 ON H 1 ON OFF ON OFF A Z ON OFF
13 ON H 1 ON OFF OFF ON Z Z OFF ON
14 ON H 1 ON OFF ON ON A Z ON ON
15 ON H 1 ON ON OFF OFF Z Z OFF OFF
16 ON H 1 ON ON ON OFF A Z ON OFF
17 ON H 1 ON ON OFF ON Z A OFF ON
18 ON H 1 ON ON ON ON A A ON ON
19 ON H 0 OFF OFF OFF OFF Z Z OFF OFF
20 ON H 0 OFF OFF ON OFF Z Z OFF ON
21 ON H 0 OFF OFF OFF ON Z Z ON OFF
22 ON H 0 OFF OFF ON ON Z Z ON ON
23 ON H 0 OFF ON OFF OFF Z Z OFF OFF
24 ON H 0 OFF ON ON OFF Z Z OFF ON
25 ON H 0 OFF ON OFF ON A Z ON OFF
26 ON H 0 OFF ON ON ON A Z ON ON
27 ON H 0 ON OFF OFF OFF Z Z OFF OFF
28 ON H 0 ON OFF ON OFF Z A OFF ON
29 ON H 0 ON OFF OFF ON Z Z ON OFF
30 ON H 0 ON OFF ON ON Z A ON ON
31 ON H 0 ON ON OFF OFF Z Z OFF OFF
32 ON H 0 ON ON ON OFF Z A OFF ON
33 ON H 0 ON ON OFF ON A Z ON OFF
34 ON H 0 ON ON ON ON A A ON ON
Product-Specific Dimensions
2.225 3.700 0.400 0.225 0.663 2.225 2.800 0.563 0.50±0.05 0.025±0.025 SEATING PLANE C 3.40±0.10 2.50±0.10 PIN#1 IDENT A B (0.15) 4X 0.40 0.40±0.05 (23X) 0.05 PIN#1 IDENT DETAIL A 0.50±0.05 45° 0.20±0.05 0.50±0.05 0.10±0.05 0.025±0.025 SEATING PLANE C TOP VIEW BOTTOM VIEW SIDE VIEW - OPTION A LAND PATTERN RECOMMENDATION NOTES: A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC STANDARD B. ALL DIMENSIONS ARE IN MILLIMETERS C. LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN D. DRAWING FILENAME: MKT-UMLP24ArevE POTENTIAL PULL BACK SIDE VIEW - OPTION B DETAIL A SCALE 2:1 7 12 1924 7 12
0.10 C A B
0.05 C
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