FXLA108 ONSEMI | Alldatasheet
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© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FXLA108 • Rev. 1.0.5 FXLA108 — Low-Voltage Dual-Supply 8-Bit Voltage Translator FXLA108 Low-Voltage Dual-Supply 8-Bit Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing
Features
Bi-Directional Interface between Two Levels: from 1.1V to 3.6V Fully Configurable: Inputs and Outputs Track VCC Non-Preferential Power-Up; Either VCC May Be Powered Up First Outputs Switch to 3-State if Either VCC is at GND Power-Off Protection Bus-Hold on Data Inputs Eliminates the Need for Pull-Up Resistors; Do Not Use Pull-Up Resistors on A or B Ports Control Input (/OE) Referenced to VCCA Voltage Packaged in 20-Terminal DQFN (2.5mm x 4.5mm) Direction Control Not Necessary 100Mbps Throughput when Translating Between 1.8V and 2.5V ESD Protection Exceeds: - 8kV HBM (per JESD22-A114 &Mil Std 883e 3015.7) - 2kV CDM (per ESD STM 5.3)
Applications
Laptops, Notebooks, Routers, Switches
Description
The FXLA108 is a configurable dual-voltage supply translator for both uni-directional and bi-directional voltage translation between two logic levels. The device allows translation between volt ages as high as 3.6V to as low as 1.1V. The A port tracks the V CCA level and the B port tracks the VCCB level. This allows for bi-directional voltage translation over a variety of voltage levels: 1.2V, The device remains in three- state as long as either VCC=0V, allowing either V CC to be powered up first. Internal power-down control ci rcuits place the device in 3-state if either VCC is removed. The /OE input, when HIGH, disables both the A and B ports by placing them in a 3-state condition. The /OE input is supplied by VCCA. The FXLA108 supports bi-direc tional translation without the need for a direction control pin. The two ports of the device have auto-direction s ense capability. Either port may sense an input signal and transfer it as an output signal to the other port.
Ordering Information
Temperature Range Package Packing Method FXLA108BQX -40 to 85°C 20-Terminal DQFN 2. 5mm x 4.5mm Package 3K Units Tape and Reel
Figure 1. Pin Configuration (Top Through View)
1 V CCA A-Side Power Supply
2 A 0 A-Side Inputs or 3-State Outputs
3 A 1 A-Side Inputs or 3-State Outputs
4 A 2 A-Side Inputs or 3-State Outputs
5 A 3 A-Side Inputs or 3-State Outputs
6 A 4 A-Side Inputs or 3-State Outputs
7 A 5 A-Side Inputs or 3-State Outputs
8 A 6 A-Side Inputs or 3-State Outputs
9 A 7 A-Side Inputs or 3-State Outputs
10 GND Ground
12 B 7 B-Side Inputs or 3-State Outputs
13 B 6 B-Side Inputs or 3-State Outputs
14 B 5 B-Side Inputs or 3-State Outputs
15 B 4 B-Side Inputs or 3-State Outputs
16 B 3 B-Side Inputs or 3-State Outputs
17 B 2 B-Side Inputs or 3-State Outputs
18 B 1 B-Side Inputs or 3-State Outputs
19 B 0 B-Side Inputs or 3-State Outputs
20 V CCB B-Side Power Supply
Figure 2. Functional Diagram
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FXLA108 • Rev. 1.0.5 4 FXLA108 — Low-Voltage Dual-Supply 8-Bit Voltage Translator Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Conditions Min. Max. Unit VCC Supply Voltage VCCA -0.5 4.6 V VCCB -0.5 4.6 VI DC Input Voltage I/O Ports A and B -0.5 4.6 V Control Input (/OE) -0.5 4.6 VO Output Voltage(2) Output 3-State -0.5 4.6 V Output Active (An) -0.5 VCCA +0.5 Output Active (Bn) -0.5 VCCB +0.5 IIK DC Input Diode Current V I<0V -50 mA IOK DC Output Diode Current VO<0V -50 mA VO>VCC +50 IOH/IOL DC Output Source/Sink Current -50 +50 mA ICC DC VCC or Ground Current (per Supply Pin) ±100 mA TSTG Storage Temperature Range -65 +150 °C PD Power Dissipation 35 mW ESD Human Body Model, JESD22-A114 8 kV Charged Device Model, JESD22-C101 2 Notes: 1. I O absolute maximum ratings must be observed. 2. All unused inputs and input/ outputs must be held at VCCi or GND. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device oper ation. Recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Conditions Min. Max. Unit VCC Power Supply Operating V CCA or VCCB 1.1 3.6 V VIN Input Voltage Ports A and B 0 3.6 V Control Input (/OE) 0 V CCA V TA Operating Temperature, Free Air -40 +85 °C dt/dV Minimum Input Edge Rate V CCA/B = 1.1 to 3.6V 10 ns/V ΘJA Thermal Resistance: Junction-to-Ambient 50 °C/W ΘJC Thermal Resistance: Junction-to-Case 23 °C/W
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FXLA108 • Rev. 1.0.5 5 FXLA108 — Low-Voltage Dual-Supply 8-Bit Voltage Translator Power-Up/Power-Down Sequence FXL translators offer an adv antage in that either V CC may be powered up first. This benefit derives from the chip design. When either V CC is at 0V, outputs are in a high-impedance state. The c ontrol input (/OE) is designed to track the V CCA supply. A pull-up resistor tying /OE to V CCA should be used to ensure that bus contention, excessive current s, or oscillations do not occur during power-up or power-down. The size of the pull-up resistor is bas ed upon the current-sinking capability of the device driving the /OE pin. The recommended power-up sequence is: 1. Apply power to the first V CC. 2. Apply power to the second V CC. 3. Drive the /OE input LOW to enable the device. The recommended power-down sequence is: 1. Drive /OE input HIGH to disable the device. 2. Remove power from either V CC. 3. Remove power from other V CC. Pull-Up/Pull-Down Resistors Do not use pull-up or pull-down resistors. This device has bus-hold circuits: pull-up or pull-down resistors are not recommended because they interfere with the output state. The current through these resistors may exceed the hold drive, II(HOLD) and/or II(OD) bus-hold currents. The bus-hold feature eliminates the need for extra resistors.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FXLA108 • Rev. 1.0.5 6 FXLA108 — Low-Voltage Dual-Supply 8-Bit Voltage Translator TA=-40 to 85°C. Symbol Parameter Conditions V CCA (V) V CCB (V) Min. Typ. Max. Unit s VIHA High-Level Input Voltage Data Inputs An Control Pin /OE 2.70 to 3.60 1.10 to 3.60 2.00 V 2.30 to 2.70 1.60 1.65 to 2.30 .65xV CCA 1.40 to 1.65 .65xV CCA 1.10 to 1.40 .90xV CCA VIHB Data Inputs B n 1.10 to 3.60 2.70 to 3.60 2.00 V 2.30 to 2.70 1.60 1.65 to 2.30 .65xV CCB 1.40 to 1.65 .65xV CCB 1.10 to 1.40 .90xV CCB VILA Low-Level Input Voltage Data Inputs An Control Pin /OE 2.70 to 3.60 1.10 to 3.60 .80 V 2.30 to 2.70 .70 1.65 to 2.30 .35xV CCA 1.40 to 1.65 .35xV CCA 1.10 to 1.40 .10xV CCA VILB Data Inputs B n 1.10 to 3.60 2.70 to 3.60 .80 V 2.30 to 2.70 .70 1.65 to 2.30 .35xV CCB 1.40 to 1.65 .35xV CCB 1.10 to 1.40 .10xV CCB VOHA High-Level Output Voltage(3) V VOLA Low-Level Output Voltage(3) V II(HOLD) Bus-Hold Input Minimum Drive Current VIN=0.80V 3.00 3.00 75.0 µA VIN=2.00V 3.00 3.00 -75.0 VIN=0.7V 2.30 2.30 45.0 VIN=1.60V 2.30 2.30 -45.0 VIN=0.57V 1.65 1.65 25.0 VIN=1.07V 1.65 1.65 -25.0 VIN=0.49V 1.40 1.40 11.0 VIN=0.91V 1.40 1.40 -11.0 VIN=0.11V 1.10 1.10 4.0 VIN=0.99V 1.10 1.10 -4.0 Continued on following page…
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FXLA108 • Rev. 1.0.5 7 FXLA108 — Low-Voltage Dual-Supply 8-Bit Voltage Translator TA=-40 to 85°C. Symbol Parameter Conditions V CCA (V) V CCB (V) Min. Max. Units II(ODH) Bus-Hold Input Overdrive High Current(4) Data Inputs An, Bn 3.60 3.60 450.00 µA 2.70 2.70 300.00 1.95 1.95 200.00 1.60 1.60 120.00 1.40 1.40 80.00 II(ODL) Bus-Hold Input Overdrive Low Current(5) Data Inputs An, Bn 3.60 3.60 -450.00 µA 2.70 2.70 -300.00 1.95 1.95 -200.00 1.60 1.60 -120.00 1.40 1.40 -80.00 II Input Leakage Current Control Inputs /OE, VI=VCCA or GND 1.10 to 3.60 3.60 ±1.0 µA IOFF Power-Off Leakage Current An VO=0V to 3.6V 0 3.6 ±2.0 µA Bn VO=0V to 3.6V 3.60 0 ±2.0 IOZ 3-State Output Leakage An, Bn VO=0V or 3.6V, µA An VO=0V or 3.6V, /OE=GND 3.60 0 ±5.0 Bn VO=0V or 3.6V, /OE=GND 0 3.60 ±5.0 ICCA/B Quiescent Supply Current(6, 7) VI=VCCI or GND; IO=0, ICCZ VI=VCCI or GND; IO=0, ICCA Quiescent Supply Current VI=VCCB or GND; IO=0 B-to-A Direction, /OE=GND 0 1.10 to 3.60 -10.0 µA VI=VCCA or GND; IO=0 A-to-B Direction 1.10 to 3.60 0 10.0 ICCB VI=VCCA or GND; IO=0, A-to-B Direction, /OE=GND 1.10 to 3.60 0 -10.0 µA VI=VCCB or GND; IO=0 B-to-A Direction 0 1.10 to 3.60 10.0 Notes: 3. This is the output voltage for static conditions. Dynamic drive specific ations are given in the Dynamic Output Electrical Characteristics table. 4. An external drive must source at least the specified current to switch LOW-to-HIGH. 5. An external drive must source at least the specified current to switch HIGH-to-LOW. 6. V CCI is the VCC associated with the input side. 7. Reflects current per supply, V CCA or VCCB.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FXLA108 • Rev. 1.0.5 8 FXLA108 — Low-Voltage Dual-Supply 8-Bit Voltage Translator Dynamic Output Electrical Characteristic A Port (An) Output Load: CL=15pF, RL ≥ MΩ (CI/O=4pF), TA=-40 to 85°C Symbol Parameter VCCA=3.0V to 3.6V VCCA=2.3V to 2.7V VCCA=1.65V to 1.95V VCCA=1.4V to 1.6V VCCA=1.1V to 1.3V Units trise Output Rise tfall Output Fall Time A Port(10) IOHD Dynamic Output Current High(9) IOLD Dynamic Output Current Low(10) B Port (Bn) Output Load: CL=15pF, RL ≥ MΩ (CI/O=5pF), TA=-40 to 85°C Symbol Parameter VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units trise Output Rise tfall Output Fall Time B Port(10) IOHD Dynamic Output Current High(9) IOLD Dynamic Output Current Low(10) Notes: 8. Dynamic output characteristi cs are guaranteed, but not tested. 9. See Figure 7. 10. See Figure 8.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FXLA108 • Rev. 1.0.5 9 FXLA108 — Low-Voltage Dual-Supply 8-Bit Voltage Translator AC Characteristics VCCA = 3.0V to 3.6V, TA=-40 to 85°C Symbol Parameter VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units tPLH,tPHL tPZL,tPZH /OE to A, tSKEW A Port, VCCA = 2.3V to 2.7V, TA=-40 to 85°C Symbol Parameter VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units tPLH,tPHL tPZL,tPZH /OE to A, tSKEW A Port, VCCA = 1.65V to 1.95V, TA=-40 to 85°C Symbol Parameter VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units tPLH,tPHL tPZL,tPZH /OE to A, tSKEW A Port, Note: 11. Skew is the variation of propagat ion delay between output signals and applies only to output signals on the same port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 10). Skew is guaranteed, but not tested.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FXLA108 • Rev. 1.0.5 10 FXLA108 — Low-Voltage Dual-Supply 8-Bit Voltage Translator AC Characteristics (Continued) VCCA = 1.4V to 1.6V, TA=-40 to 85°C Symbol Parameter VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units tPLH,tPHL tPZL,tPZH /OE to A, tSKEW A Port, VCCA = 1.1V to 1.3V, TA=-40 to 85°C Symbol Parameter VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units tPLH,tPHL Note: 12. Skew is the variation of propagat ion delay between output signals and applies only to output signals on the same port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 10). Skew is guaranteed, but not tested.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FXLA108 • Rev. 1.0.5 11 FXLA108 — Low-Voltage Dual-Supply 8-Bit Voltage Translator Maximum Data Rate TA=-40 to 85°C. VCCA VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units VCCA=3.00V to 3.60V 140 120 100 80 40 Mbps VCCA=2.30V to 2.70V 120 120 100 80 40 Mbps VCCA=1.65V to 1.95V 100 100 80 60 40 Mbps VCCA=1.40V to 1.60V 80 80 60 60 40 Mbps 40 40 40 40 40 Mbps Notes: 13. Maximum data rate is guaranteed, but not tested. 14. Maximum data rate is specified in megabits per second (see Figure 9). It is equivalent to two times the F-toggle frequency, specified in megahertz. For example, 100Mbps is equivalent to 50MHz. Capacitance Symbol Parameter Conditions TA=+25°C Typical Units CIN Input Capacitance Control Pin (/OE) V CCA=VCCB=GND 3 pF CI/O Input/Output Capacitance An VCCA=VCCB=3.3V, /OE=VCCA pF Bn 5 Cpd Power Dissipation Capacitance V CCA=VCCB=3.3V, VI=0V or VCC, f=10MHz 25 pF
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FXLA108 • Rev. 1.0.5 12 FXLA108 — Low-Voltage Dual-Supply 8-Bit Voltage Translator I/O Architecture Benefit The FXLA108 I/O architecture benefits the end user, beyond level translation, in the following three ways: Auto Direction without an external direction pin. Drive Capacitive Loads . Automatically shifts to a higher current drive mode onl y during “Dynamic Mode” or HL / LH transitions. Lower Power Consumption . Automatically shifts to low-power mode during “Stati c Mode” (no transitions), lowering power consumption. The FXLA108 does not require a direction pin. Instead, the I/O architecture detects input transitions on both side and automatically transfe rs the data to the corresponding output. For example, for a given channel, if both A and B side are at a static LOW, the direction has been established as A B, and a LH transition occurs on the B port; the FXLA108 internal I/O architecture automatically changes direction from A B to B A. During HL / LH transitions, or “Dynamic Mode,” a strong output driver drives the output channel in parallel with a weak output driver. After a typical delay of approximately 10ns – 50ns, the strong driver is turned off, leaving the weak driver enabled for holdi ng the logic state of the channel. This weak driver is called the “bus hold.” “Static Mode” is when only the bus hold drives the channel. The bus hold can be over ridden in the event of a direction change. The strong driver allows the FXLA108 to quickly charge and discharge capacit ive transmission lines during dynamic mode. Stat ic mode conserves power, where ICC is typically < 5µA. Bus Hold Minimum Drive Current Specifies the minimum amount of current the bus hold driver can source/sink. The bus hold minimum drive current (IIHOLD) is V CC dependent and guaranteed in the output state in a static m ode, but that can be overridden when an input data transition occurs. Bus Hold Input Overdrive Drive Current Specifies the minimum amount of current required (by an external device) to over drive the bus hold in the event of a direction change. The bus hold overdrive (IIODH, IIODL) is VCC dependent and guaranteed in the DC Electrical tables. Dynamic Output Current The strength of t he output driver during LH / HL transitions is referenced on page 8, Dynamic Output Electrical Characteristics, IOHD, and IOLD.
Figure 11. 20-Terminal DQFN 2.5mm x 4.5mm Package warranty therein, which covers Fairchild products. http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FXLA108 • Rev. 1.0.5 17 FXLA108 — Low-Voltage Dual-Supply 8-Bit Voltage Translator
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