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Technical content
Features
Bi-Directional Interface between Two Levels: from 1.1V to 3.6V Fully Configurable: Inputs and Outputs Track VCC Non-Preferential Power-Up; Either VCC May Be Powered Up First Outputs Switch to 3-State if Either VCC is at GND Power-Off Protection Bus-Hold on Data Inputs Eliminates the Need for Pull-Up Resistors; Do Not Use Pull-Up Resistors on A or B Ports Control Input (/OE) Referenced to VCCA Voltage Available in 16-Terminal UMLP (1.8mm x 2.6mm) and 12-Terminal, Quad UMLP, 1.8 x 1.8mm Packages Direction Control Not Necessary 100Mbps Throughput when Translating Between 1.8V and 2.5V ESD Protection Exceeds: - 8kV HBM (per JESD22-A114 & Mil Std 883e 3015.7) - 2kV CDM (per ESD STM 5.3)
Applications
Cell Phone, PDA, Digital Camera, Portable GPS
Description
The FXLA104 is a configurable dual-voltage supply translator for both uni-directional and bi-directional voltage translation between two logic levels. The device allows translation between voltages as high as 3.6V to as low as 1.1V. The A port tracks the V CCA level and the B port tracks the VCCB level. This allows for bi-directional voltage translation over a variety of voltage levels: 1.2V, The device remains in three-state as long as either VCC=0V, allowing either V CC to be powered up first. Internal power-down control circuits place the device in 3-state if either V CC is removed. The /OE input, when HIGH, disables both the A and B ports by placing them in a 3-state condition. The /OE input is supplied by V CCA. The FXLA104 supports bi-directional translation without the need for a direction contro l pin. The two ports of the device have auto-direction sense capability. Either port may sense an input signal and transfer it as an output signal to the other port.
Ordering Information
-40 to 85°C XJ 16-Terminal UMLP 1.8 x 2.6mm Package 5K Units Tape and Reel FXLA104UM12X XJ 12-Terminal, Quad UMLP, 1.8 x 1.8mm Package
Figure 1. 16-Pin UMLP (Top Through View) Figure 2. 12-Pin UMLP (Top Through View)
16 Pin # 12 Pin # Name Description
5 NC No Connect
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator Functional Diagram Figure 3 . Functional Diagram Function Table Control Outputs /OE LOW Logic Level Normal Operation HIGH Logic Level 3-State www.onsemi.com
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may dam age the device. The device may not function or be operable above the recommended operating conditions and st ressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Conditions Min. Max. Unit VCC Supply Voltage VCCA -0.5 4.6 V VCCB -0.5 4.6 VI DC Input Voltage I/O Ports A and B -0.5 4.6 V Control Input (/OE) -0.5 4.6 VO Output Voltage (2) Output 3-State -0.5 4.6 V Output Active (An) -0.5 VCCA +0.5 Output Active (Bn) -0.5 VCCB +0.5 IIK DC Input Diode Current VIN<0V -50 mA IOK DC Output Diode Current VO<0V -50 mA VO>VCC +50 IOH/IOL DC Output Source/Sink Current -50 +50 mA ICC DC V CC or Ground Current (per Supply Pin) ±100 mA TSTG Storage Temperature Range -65 +150 °C PD Power Dissipation 17 mW ESD Electrostatic Discharge Capability Human Body Model (per JESD22- A114 & Mil Std 883e 3015.7) 8 kV Charged Device Model (per ESD STM 5.3) 2 Notes: 1. I O absolute maximum ratings must be observed. 2. All unused inputs and input/outputs must be held at V CCi or GND. Symbol Parameter Conditions Min. Max. Unit VCC Power Supply Operating VCCA or VCCB 1.1 3.6 V VIN Input Voltage Ports A and B 0 3.6 V Control Input (/OE) 0 V CCA V TA Operating Temperature, Free Air -40 +85 °C dt/dV Minimum Input Edge Rate V CCA/B = 1.1 to 3.6V 10 ns/V ΘJA Thermal Resistance: Junction-to-Ambient UMLP-16 315 °C/W UMLP-12 300 ΘJC Thermal Resistance: Junction-to-Case UMLP-16 155 °C/W UMLP-12 165 www.onsemi.com
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator Power-Up/Power-Down Sequence FXL translators offer an advantage in that either V CC may be powered up first. This benefit derives from the chip design. When either V CC is at 0V, outputs are in a high-impedance state. The control input (/OE) is designed to track the V CCA supply. A pull-up resistor tying /OE to V CCA should be used to ensure that bus contention, excessive currents, or oscillations do not occur during power-up or power-down. The size of the pull-up resistor is based upon the current-sinking capability of the device driving the /OE pin. The recommended power-up sequence is: 1. Apply power to the first V CC. 2. Apply power to the second V CC. 3. Drive the /OE input LOW to enable the device. The recommended power-down sequence is: 1. Drive /OE input HIGH to disable the device. 2. Remove power from either V CC. 3. Remove power from other V CC. Pull-Up/Pull-Down Resistors Do not use pull-up or pull-down resistors . This device has bus-hold circuits: pull-up or pull-down resistors are not recommended because they interfere with the output state. The current th rough these resistors may exceed the hold drive, I I(HOLD) and/or I I(OD) bus-hold currents, resulting in data transition and/or auto- direction sensing failures. The bus-hold feature eliminates the need for extra resistors. www.onsemi.com
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator TA=-40 to 85°C Symbol Parameter Conditions V CCA (V) V CCB (V) Min. Typ. Max. Units VIHA High-Level Input Voltage Data Inputs An Control Pin /OE 2.70 to 3.60 1.10 to 3.60 2.00 V 2.30 to 2.70 1.60 1.65 to 2.30 .65xVCCA 1.40 to 1.65 .65xVCCA 1.10 to 1.40 .90xVCCA VIHB Data Inputs Bn 1.10 to 3.60 2.70 to 3.60 2.00 V 2.30 to 2.70 1.60 1.65 to 2.30 .65xV CCB 1.40 to 1.65 .65xV CCB 1.10 to 1.40 .90xV CCB VILA Low-Level Input Voltage Data Inputs An Control Pin /OE 2.70 to 3.60 1.10 to 3.60 .80 V 2.30 to 2.70 .70 1.65 to 2.30 .35xVCCA 1.40 to 1.65 .35xVCCA 1.10 to 1.40 .10xVCCA VILB Data Inputs Bn 1.10 to 3.60 2.70 to 3.60 .80 V 2.30 to 2.70 .70 1.65 to 2.30 .35xVCCB 1.40 to 1.65 .35xVCCB 1.10 to 1.40 .10xVCCB VOHA High-Level Output Voltage(3) V VOLA Low-Level Output Voltage (3) V II(HOLD) Bus-Hold Input Minimum Drive Current V IN=0.8V 3.00 3.00 75.0 µA VIN=2.0V 3.00 3.00 -75.0 VIN=0.7V 2.30 2.30 45.0 VIN=1.6V 2.30 2.30 -45.0 VIN=0.57V 1.65 1.65 25.0 VIN=1.07V 1.65 1.65 -25.0 VIN=0.49V 1.40 1.40 11.0 VIN=0.91V 1.40 1.40 -11.0 VIN=0.11V 1.10 1.10 4.0 VIN=0.99V 1.10 1.10 -4.0 Note: 3. This is the output voltage for static conditions. Dynamic drive specific ations are given in the Dynamic Output Electrical Characteristics table. Continued on following page… www.onsemi.com
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator TA=-40 to 85°C. Symbol Parameter Conditions V CCA (V) V CCB (V) Min. Max. Units II(ODH) Bus-Hold Input Overdrive High Current (4) Data Inputs An, Bn 3.60 3.60 450.0 µA 2.70 2.70 300.0 1.95 1.95 200.0 1.60 1.60 120.0 1.40 1.40 80.0 II(ODL) Bus-Hold Input Overdrive Low Current (5) Data Inputs An, Bn 3.60 3.60 -450.0 µA 2.70 2.70 -300.0 1.95 1.95 -200.0 1.60 1.60 -120.0 1.40 1.40 -80.0 II Input Leakage Current Control Inputs /OE, V I=VCCA or GND 1.10 to 3.60 3.60 ±1.0 µA IOFF Power-Off Leakage Current An VO=0V to 3.6V 0 3.60 ±2.0 µA Bn VO=0V to 3.6V 3.60 0 ±2.0 IOZ 3-State Output Leakage An, Bn VO=0V or 3.6V, µA An VO=0V or 3.6V, /OE=GND 3.60 0 ±5.0 Bn VO=0V or 3.6V, /OE=GND 0 3.60 ±5.0 ICCA/B Quiescent Supply Current(6, 7) VI=VCCI or GND; IO=0, ICCZ VI=VCCI or GND; IO=0, ICCA Quiescent Supply Current V I=VCCB or GND; IO=0 B-to-A Direction, /OE=GND 0 1.10 to 3.60 -10.0 µA VI=VCCA or GND; IO=0 A-to-B Direction 1.10 to 3.60 0 10.0 ICCB VI=VCCA or GND; IO=0, A-to-B Direction, /OE=GND 1.10 to 3.60 0 -10.0 µA VI=VCCB or GND; IO=0 B-to-A Direction 0 1.10 to 3.60 10.0 Notes: 4. An external drive must source at least the specified current to switch LOW-to-HIGH. 5. An external drive must source at least the specified current to switch HIGH-to-LOW. 6. V CCI is the VCC associated with the input side. 7. Reflects current per supply, V CCA or VCCB. www.onsemi.com
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator Dynamic Output Electrical Characteristic A Port (An) Output Load: CL=15pF, RL ≥ MΩ (CI/O=4pF), TA=-40 to 85°C Symbol Parameter VCCA=3.0V to 3.6V VCCA=2.3V to 2.7V VCCA=1.65V to 1.95V VCCA=1.4V to 1.6V VCCA=1.1V to 1.3V Units trise Output Rise tfall Output Fall Time A Port (10) IOHD Dynamic Output Current High (9) IOLD Dynamic Output Current Low (10) B Port (Bn) Output Load: CL=15pF, RL ≥ MΩ (CI/O=5pF), TA=-40 to 85°C Symbol Parameter VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units trise Output Rise Time B Port tfall Output Fall Time B Port (10) IOHD Dynamic Output Current High (9) IOLD Dynamic Output Current Low (10) Notes: 8. Dynamic output characteristic s are guaranteed, but not tested. 9. See Figure 8. 10. See Figure 9. www.onsemi.com
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator AC Characteristics VCCA = 3.0V to 3.6V, TA=-40 to 85°C Symbol Parameter VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units tPLH,tPHL tPZL,tPZH /OE to A, tSKEW A Port, B Port VCCA = 2.3V to 2.7V, TA=-40 to 85°C Symbol Parameter VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units tPLH,tPHL tPZL,tPZH /OE to A, tSKEW A Port, B Port VCCA = 1.65V to 1.95V, TA=-40 to 85°C Symbol Parameter VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units tPLH,tPHL tPZL,tPZH /OE to A, tSKEW A Port, B Port Note: 11. Skew is the variation of propagat ion delay between output signals and applies only to output signals on the same port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 11). Skew is guaranteed, but not tested. www.onsemi.com
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator AC Characteristics (Continued) VCC=1.4V to 1.6V, TA=-40 to 85°C Symbol Parameter VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units tPLH,tPHL tPZL,tPZH /OE to A, tSKEW A Port, B Port VCCA=1.1V to 1.3V, TA=-40 to 85°C Symbol Parameter VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units tPLH,tPHL Note: 12. Skew is the variation of propagat ion delay between output signals and applies only to output signals on the same port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 11). Skew is guaranteed, but not tested. www.onsemi.com
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator Maximum Data Rate(13, 14) TA=-40 to 85°C VCCA VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units VCCA=3.00V to 3.60V 140 120 100 80 40 Mbps VCCA=2.30V to 2.70V 120 120 100 80 40 Mbps VCCA=1.65V to 1.95V 100 100 80 60 40 Mbps VCCA=1.40V to 1.60V 80 80 60 60 40 Mbps 40 40 40 40 40 Mbps Notes: 13. Maximum data rate is guaranteed, but not tested. 14. Maximum data rate is spec ified in megabits per second (see Figure 10). It is equivalent to two times the F-toggle frequency, specified in megahertz. For example, 100Mbps is equivalent to 50MHz. Capacitance Symbol Parameter Conditions TA=+25°C Typical Units CIN Input Capacitance Control Pin (/OE) V CCA=VCCB=GND 3 pF CI/O Input/Output Capacitance An VCCA=VCCB=3.3V, /OE=VCCA pF Bn 5 Cpd Power Dissipation Capacitance V CCA=VCCB=3.3V, VI=0V or VCC, f=10MHz 25 pF www.onsemi.com
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator I/O Architecture Benefit The FXLA104 I/O architecture benefits the end user, beyond level translation, in the following three ways: Auto Direction without an external direction pin. Drive Capacitive Loads . Automatically shifts to a higher current drive mode only during “Dynamic Mode” or HL / LH transitions. Lower Power Consumption . Automatically shifts to low-power mode during “Static Mode” (no transitions), lowering power consumption. The FXLA104 does not require a direction pin. Instead, the I/O architecture detects input transitions on both side and automatically transfers the data to the corresponding output. For example, for a given channel, if both A and B side are at a static LOW, the direction has been established as A B, and a LH transition occurs on the B port; the FXLA104 internal I/O architecture automatically changes direction from A B to B A. During HL / LH transitions, or “Dynamic Mode,” a strong output driver drives the output channel in parallel with a weak output driver. After a typical delay of approximately 10ns – 50ns, t he strong driver is turned off, leaving the weak driver enabled for holding the logic state of the channel. This weak driver is called the “bus hold.” “Static Mode” is when only the bus hold drives the channel. The bus hold can be over ridden in the event of a direction change. The strong driver allows the FXLA104 to quickly charge and discharge capacitive transmission lines during dynamic mode. Static mode conserves power, where I CC is typically < 5µA. Bus Hold Minimum Drive Current Specifies the minimum amount of current the bus hold driver can source/sink. The bus hold minimum drive current (II HOLD) is V CC dependent and guaranteed in the output state in a static mode, but that can be overridden when an input data transition occurs. Bus Hold Input Overdrive Drive Current Specifies the minimum amount of current required (by an external device) to overdrive the bus hold in the event of a direction change. The bus hold overdrive (II ODH, IIODL) is VCC dependent and guaranteed in the DC Electrical tables. Dynamic Output Current The strength of the output driver during LH / HL transitions is referenced on page 8, Dynamic Output Electrical Characteristics, IOHD, and IOLD. www.onsemi.com
Table 1. AC Test Conditions Table 2. AC Load
- Waveform for Inverting and Non-Inverting Functions
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator Physical Dimensions F igure 12. 16-Lead, UMLP, QUAD, Ultra-Thin MLP, 1.8 X 2.6mm RECOMMENDED LAND PATTERN NOTES: A. PACKAG E DOES NOT FULLY CONFORM TO J EDEC STANDARD. B. DIMENSIONS AR E IN MILLIMETERS. C. D IMENSIONS AND TOLERANCES PER ASME Y14 .5M, 1994. D. L AND PATTERN RECOMMENDATION IS BASED ON FSC DESIGN ONLY. E. D RAWING FILENAME: MKT-UMLP16Arev4. F. TE RMINAL SHAPE MAY VARY ACCORDING TO PACKAGE SUPPLIER, SEE TERMINAL S HAPE VARIANTS. SCALE : 2X LEAD OPTION 1 SCALE : 2X LEAD OPTION 2 PIN#1 IDENT PIN#1 IDENT PACKAGE EDGE TOP VIEW BOTTOM VIEW 0.10 C 0.08 C 2.60 1.80 0.10 C SIDE VIEW 0.10 C 0.05 0.00
0.10 C A B
0.05 C 0.55 MAX. 0.40 1316 2.10 2.90 0.40 0.663 0.563 0.225 (15X) (16X) 0.152 0.40 0.60 0.10 0.30 0.50 0.10 TERMINAL SHAPE VARIANTS 0.15 0.25 15X PIN 1 NON-PIN 1 0.15 0.25 15X 0.30 0.50 0.15 0.25 0.30 0.50 0.15 0.25 15X15X Supplier 1 Supplier 2 PIN 1 NON-PIN 1 A B CSEATING PLANE 0.45 0.35 0.55 0.45 0.25 0.15 R0.20 www.onsemi.com
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator Physical Dimensions F igure 13. 12-Lead, UMLP, QUAD, JEDEC MO-252 1.8 x 1.8mm Package A B CSEATING PLANE RECOMMENDED LAND PATTERN NOTES: A. PA CKAGE DOES NOT FULLY CONFORM TO JEDEC STANDARD. B. DIMENSIO NS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASM E Y14.5M, 1994. D. L AND PATTERN RECOMMENDATION IS BA SED ON FSC DESIGN ONLY. E. DRAW ING FILENAME: MKT-UMLP12Arev4. SCALE : 2X LEAD OPTION 1 SCALE : 2X LEAD OPTION 2 DETAIL A SCALE : 2X PIN#1 IDENT TOP VIEW BOTTOM VIEW 0.10 C 0.08 C 0.10 C SIDE VIEW 0.10 C 0.05 0.00 3 6
0.10 CAB
0.05 C 0.55 MAX. 1.80 1.80 0.40 0.25 0.15 (12X) 0.35 0.45 2.10 2.100.40 0.563 (11X) 0.20(12X) 0.152 0.588 DETAIL A PIN#1 IDENT (11X) PACKAGE EDGE 0.10 0.10 0.45 0.35 0.10 www.onsemi.com
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