FXL6408 ONSEMI | Alldatasheet
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© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FXL6408 Rev. 1.0.0 FXL6408 — Fully Configurable 8-Bit I2C-Controlled GPIO Expander FXL6408 Fully Configurable 8-Bit I2C-Controlled GPIO Expander
Features
4X Expansion of Connected Processor I/O Ports Fully Integrated I2C Slave 8 Independently Configurable I/O Ports Low-Power Quiescent Current: 1.5 µA Voltage Translation Capable from 1.65 V I2C Port Up to 4.0 V GPIO Pins Selectable Device Address 6 mA Output Drive Interrupt Pin to Alert Processor of Status Changes
Description
The FXL6408 is an 8-bit I 2C-controlled GPIO expander. When configured in Input Mode, the FXL6408 monitors the input ports for data transitions and signals the baseband by asserting the /INT pin. The input default values can be programmed independently, allowing customized input detection. All inputs can be configured with pull-up or pull-down resistors to pre-bias the inputs in open-drain or non-driven applications. When configured in Output Mode, the GPIO pins are capable of delivering 6 mA output drive according to the I 2C register set. The FXL6408 is designed to allow voltage translation from levels as low as 1.65 V and up to 4.0 V. The FXL6408 features an active LOW RESET input as well as Power-On Reset (POR) circuit and I 2C software reset options. Figure 1. Block Diagram
Ordering Information
Part Number Top Mark Operating Temperature Range Package Packing Method FXL6408UMX XT -40 to 85°C 16-Lead, UMLP, Quad, Ultrathin MLP, 1.8 X 2.6 mm Body
5000 Units on
Figure 2. Bottom View Figure 3. Top Through View
2 V DDIO Voltage reference for I/O-side voltage translation (if I/O translation is not needed, tie
3 GPIO7 General-purpose programmable I/O
4 GPIO6 General-purpose programmable I/O
5 GPIO5 General-purpose programmable I/O
6 GPIO4 General-purpose programmable I/O
7 GPIO3 General-purpose programmable I/O
8 GPIO2 General-purpose programmable I/O
9 ADDR Address input, GND or V CC
11 GPIO1 General-purpose programmable I/O
12 GPIO0 General-purpose programmable I/O
13 SCL I2C serial bus; requires a pull-up resistor to VCC
14 SDA I2C serial data; requires a pull-up resistor to VCC
15 V CC Supply voltage
16 GND Ground
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FXL6408 Rev. 1.0.0 3 FXL6408 — Fully Configurable 8-Bit I2C-Controlled GPIO Expander Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may dam age the device. The device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Condition Min. Max. Unit VCC, VDDIO Supply Voltages -0.5 4.6 V VIN DC Input Voltage -0.5 4.0 V VOUT Output Voltage(1) -0.5 4.0 V IIK DC Input Diode Current V IN < 0 V -50 mA IOK DC Output Diode Current V OUT < 0 V -50 mA IOL DC Output Sink Current +50 mA ICC DC VCC or Ground Current per Supply Pin 100 mA TSTG Storage Temperature Range -65 +150 C TJ Junction Temperature under Bias +150 C TL Junction Lead Temperature, Soldering 10 Seconds +260 C ΘJA Thermal Resistance, Junction-to-Ambient 115 °C/W ESD Electrostatic Discharge Capability Human Body Model, JESD22-A114 4 kV Charged Device Model, JESD22-C101 2 Note: 1. All output current absolute ma ximum ratings must be observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ens ure optimal performance to the datasheet specificatio ns. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Condition Min. Max. Unit VCC Supply Voltage Operating 1.65 3.60 V VDDIO I/O Side Reference Voltage 1.65 4.00 V VIN Input Voltage on I/O pins 0 4.0 V VOUT Output Voltage 0 V DDIO V TA Operating Temperature -40 +85 °C tr, tf Input Rise and Fall Times to I/O Pins when Configured as Inputs VDDIO at 1.8 V, 2.5 V ±0.2 V 0 200 ns/V VDDIO at 3.6 V ± 0.3 V 0 100
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FXL6408 Rev. 1.0.0 4 FXL6408 — Fully Configurable 8-Bit I2C-Controlled GPIO Expander Symbol Parameter Condition V CC (V) TA=25°C TA=-40 to 85°C Unit RST, ADDR, SDA, SCL, /INT Pins VPOR Power-On Reset Voltage V DDIO=0 to 4.0 V 1.25 1.25 V IIN Input Leakage Current 0 VIN VCC 0 to 3.6 ±1 ±10 µA IOFF Power-Off Leakage Current VIN or VOUT=3.6 V 0 1 10 µA ICC Standby Mode (SCL in Static Condition) VIN=VCC or GND 1.8 to 3.6 1.2 1.5 µA Active Mode(2) (SCL Active) 300 300 GPIO Pins VDDIO (V) VIH HIGH Level Input Voltage 1.65 to 1.95 0.65 VDDIO 0.65 VDDIO V 2.30 to 4.00 0.70 VDDIO 0.70 VDDIO VIL LOW Level Input Voltage 1.65 to 1.95 -0.3 0.35 VDDIO -0.3 0.35 VDDIO V 2.30 to 4.0 -0.3 0.30 VDDIO -0.3 0.30 VDDIO VOH HIGH Level Output Voltage VIN=VIH, IOH=100 µA 1.8 VDDIO - 0.2 VDDIO - 0.2 V
3.6 VDDIO
- 0.2 VDDIO - 0.2
4.0 VDDIO
- 0.2 VDDIO - 0.2 IOH=6 mA 1.8 VDDIO - 0.45 VDDIO - 0.45
- 0.45 VDDIO - 0.45 VOL LOW Level Output Voltage VIN=VIL, IOL= -100 µA 1.8 0.2 0.2 V 3.6 0.2 0.2 4.0 0.2 0.2 IOL=-6 mA 1.8 0.45 0.45 3.6 0.5 0.5 RPULL Pull-Up or Pull-Down Resistors 100 k Ω IOL Output Low Current 1.8 to 4.0 6.0 6.0 mA IOH Output High Current 1.8 to 4.0 -6.0 -6.0 IIN Input Low Current (3) 0 ≤ VIN ≤ VDDIO 1.8 to 4.0 ±50 ±50 µA IOFF Power-Off Leakage Current VIN=4.0 V 0 1 10 µA Notes: 2. Includes all internal circuitry consumption from the V CC supply. Does not include the I/O buffers, which are supplied by VDDIO and are load dependent. 3. I IL and IIH specifications only apply when the outputs are configured with pull-down or pull-up resistors, respectively. Specifications values assume VIN <= VDDIO.
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FXL6408 Rev. 1.0.0 6 FXL6408 — Fully Configurable 8-Bit I2C-Controlled GPIO Expander DC Characteristics (I2C Controller SDA, SCL) Symbol Parameter Fast Mode (400 kHz) Min. Max. Unit VIL Low-Level Input Voltage -0.5 0.3 V CC V VIH High-Level Input Voltage 0.7 VCC V VHYS Hysteresis of Schmitt Trigger Inputs VCC > 2 V 0.05 V CC V VCC < 2 V 0.1 V CC VOL Low-level Output Voltage at 3 mA Sink Current (Open-Drain or Open-Collector) VCC > 2 V 0 0.4 V VCC < 2 V 0.2 V CC V II Input Current of Each I/O Pin, Input Voltage 0.26 V to 2.34 V -10 10 µA CI Capacitance for Each I/O Pin 10 pF All typical value are for VCC=1.8 V at TA=25°C unless otherwise specified. Symbol Parameter Fast Mode (400 kHz) Min. Max. Unit fSCL SCL Clock Frequency 0 400 kHz tHD;STA Hold Time (Repeated) START Condition 0.6 µs tLOW LOW Period of SCL Clock 1.3(4) µs tHIGH HIGH Period of SCL Clock 0.6 µs tSU;STA Set Up Time for Repeated START Condition 0.6 µs tHD;DAT Data Hold Time ( See Figure 7) 0 0.9 µs tSU;DAT Data Set Up Time ( See Figure 7) 100 (5) ns tPS Set Up Time Required by SDA Input Buffer (When Receiving Data) 0 ns tPH Out Delay Required by SDA Output Buffer (When Transmitting Data) 300 ns tr Rise Time of SDA and SCL Signals 20+0.1C b (6,7) 300 ns tf Fall Time of SDA and SCL Signals 20+0.1C b (6,7) 300 ns tSU;STOP Set Up Time for STOP Condition 0.6 µs tBUF Bus Free Time between a STOP and START Conditions 1.3 µs tSP Pulse Width of Spikes that Must Be Suppressed by the Input Filter 0 50 ns Notes: 4. The FXL6408 can accept clock signals with LOW as lo w as 1.1 µs, provided that the received SDA signal tHD;DAT+ tr/f<=1.1 µs. The FXL6408 features a 0 ns SDA input setup time and, therefore, this parameter is not included in the above equation. 5. A Fast-Mode I 2C-Bus® device can be used in a Standard-Mode I2C-Bus system, but the requirement tSU;DAT ≥ 250 ns must be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal. It must output the next data bit to the SDA line tr_max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C bus specification) before the SCL line is released. 6. C b equals the total capacitance of one bus line in pF. If mixed with High-Speed Mode devices, faster fall times are allowed, according to the I2C specification. 7. The FXL6408 ensures that the SDA signal out mu st coincide with SCL LOW for worst-case SCL tf maximum times of 300 ns. This requirement prevents data loss by preventing SDA out transitions during the undefined region of the falling edge of SCL. Consequently, the FXL6408 fulfils the following requirement from the I2C specification, note 2 on page 77: “A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.” 8. FXL6408 I 2C slave is fully compliant the NXP (Phillips) I2C specification Rev. 0.3 UM10204 (2007).
Figure 7. Definition of Timing for Full-Speed Mode Devices on the I2C-Bus ® Trademarks are the property of their respective owners.
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FXL6408 Rev. 1.0.0 8 FXL6408 — Fully Configurable 8-Bit I2C-Controlled GPIO Expander Functional Description Overview The FXL6408 I/O expander frees up six ports of the central processor to be dedicated for more critical functions. The FXL6408 enables the addition of eight General-Purpose Input / Out put (GPIO) ports to a system processor while using two I/O ports for I 2C control (net six additional I/Os). The device can be used in multiple applications, from button monitoring to driving control pins of other ICs in the system. It also allows the system designer to add new features and functions quickly without upgrading the central processor. The FXL6408 includes eight I/O pins controlled by an integrated I2C slave and allows the central processor to control each I/O independent ly. When configured as outputs, each pin can deliver up to 6 mA drive. When configured as inputs, the default state can be independently configured. In addition, the FXL6408 has integrated pull-up and pull- down resistors that are enabled via I 2C commands in the register map. This allows the system designer to pre-bias the inputs to a known level to allow use with un-driven input signals. Interrupt Operation The /INT pin is a LOW-asserted open-drain output and requires an external pull-up resistor. The FXL6408 signals an interrupt to the processor when an event occurs, removing the need for the processor to continuously poll the FXL6408 registers. Immediately after detecting a change at an input, the FXL6408 writes the corresponding bit in the input interrupt status register (13h) and asserts the /INT pin by pulling it LOW. The interrupt status register bit remains HIGH until the processor reads the register and clears the bit. If the input pin remains in the non-default state after the interrupt has been serviced, a new interrupt is not generated until after the input state has first returned to its default state and changed back to its non-default state. The FXL6408 also c ontains an Input Status register (0F h) used to verify the cu rrent status of the given input at the time when the interrupt is serviced by the processor. These two registers allow the processor to determine the following information about any input every time the register map is read: If the input state changed from the default state since the most recent register read; and The current state of the input pin. The interrupt output /INT, once asserted, is held LOW until the interrupt is serviced by the processor. This means that the system uses level-sensitive interrupts. Interrupt signaling is asynchronous to the SCL signal. Device Reset The FXL6408 has three reset options, all of which cause the part to reset all register settings to their default states. Immediately after device reset, the RST_INT bit in the Device ID & Ctrl register (01h) is HIGH and an interrupt signal is generated by the FXL6408. After the processor reads the register, this bit is cleared and, on future register reads, the pr ocessor can verify that the FXL6408 has not been reset if this bit remains LOW. Following are descriptions of the three reset methods. Power-On Reset (POR) On device power-up, when V CC reaches V POR or if the VCC supply voltage drops below V POR during operation, the FXL6408 immediately resets. Software Reset The FXL6408 can be reset by the processor using an I2C write command to change bit 0 of register 01h to a 1. Immediately following this change, the FXL6408 resets and all register values return to their default values. In this case, the SW_RST bit returns to 0 as soon as the reset sequence is completed. Reset Pin The FXL6408 is reset when the /RST pin (C3) is pulled LOW. Translation The FXL6408 has the ability to translate between the system I 2C voltage reference and the I/O voltage reference. The V CC pin is used both as the FXL6408 power supply as well as the voltage reference for the I2C inputs, ADDR, /INT, and RESET pins. The V DDIO pin is used only for the voltage su pply reference of the I/O ports. For example, a 1.8 V-referenced I 2C Bus can be used to interface with the FXL6408 and control 3.6 V- referenced I/Os by supplying V CC = 1.8 V and V DDIO = 3.6 V. If translation is not needed, the system provides the same voltage to both the V CC and VDDIO pins. If both the I/O and I 2C interfaces are referenced to 1.8 V, the VCC supply and VDDIO pin should both be tied to 1.8 V.
Table 3. Device ID & Control RST INT flag is cleared after being read by master. For SW reset, the master writes bit 0 HIGH. 4:2 FW_rev 3 3-bit ascending value, indicating the firmware revision.
1 RST_INT 1
0 SW_RST 1
Table 4. IO Direction
7 GPIO7 1
0: GPIO configured as input. 1: GPIO configured as output.
6 GPIO6 1
5 GPIO5 1
4 GPIO4 1
3 GPIO3 1
2 GPIO2 1
1 GPIO1 1
0 GPIO0 1
Table 5. Output State If the pin is defined as input in register 03h, the corresponding bit has no effect.
7 Out 7 1
6 Out 6 1
5 Out 5 1
4 Out 4 1
3 Out 3 1
2 Out 2 1
1 Out 1 1
0 Out 0 1
Table 6. Output High-Z If the pin is defined as input in register 03h, the corresponding bit has no effect. Table 7. Input Default State If the pin is defined as output in register 03h, the corresponding bit has no effect.
7 In 7 1
goes HIGH, an interrupt is triggered. goes LOW, an interrupt is triggered.
6 In 6 1
5 In 5 1
4 In 4 1
3 In 3 1
2 In 2 1
1 In 1 1
0 In 0 1
Table 8. Pull Enable If the pin is defined as output in register 03h, the corresponding bit has no effect. 0: GPIO input pull-up/pull-down is not enabled. 1: GPIO input Pull-up/Pull-down is enabled.
Table 9. Pull-Down / Pull-Up If the pin is defined as output in register 03h, the corresponding bit has no effect. If the corresponding bit in register 0Bh=0, this register setting has no effect. 0: GPIO input pull-down is enabled. 1: GPIO input pull-up is enabled. Table 10. Input Status If the pin is defined as output in register 03h, the corresponding bit has no effect. This bit shows the real-time input pin status. Table 11. Interrupt Mask If the pin is defined as output in register 03h, the corresponding bit has no effect. This bit enables the interrupt generation from input pin state change to INT. 0: GPIO input interrupt is generated. 1: GPIO input interrupt is masked.
Table 12. Interrupt Status This bit is HIGH if input GPIO ≠ default state (register 09h). The flag is cleared after being read by the master (bit returns to 0). The input must go back to default state and change again before this flag is raised again. 0: GPIO input is in default state or the flag has been cleared. 1: GPIO input has changed state from default.
Figure 10. 16-lead, UMLP, QUAD, Ultra-Thin MLP, 1.8 x 2.6 mm warranty therein, which covers Fairchild products. http://www.fairchildsemi.com/packaging/. B. DIMENSIONS ARE IN MILLIMETERS. E. DRAWING FILENAME: MKT-UMLP16Arev4.
0.10 C A B
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FXL6408 Rev. 1.0.0 15 FXL6408 — Fully Configurable 8-Bit I2C-Controlled GPIO Expander
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