FXGL2014

FXGL2014 ONSEMI | Alldatasheet

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www.onsemi.com © 2016 Semiconductor Components Industries, LLC FXGL2014 • Rev. 2 FXGL2014 — 4-Channel LVTTL to GTL Transceiver FXGL2014 — 4-Channel LVTTL to GTL Transceiver

Features

 Operates as a 4-bit GTL−/GTL/GTL+ Sampling receiver or as a LVTTL to GTL−/GTL/GTL+ Driver  3.0 V to 3.6 V Operation with 5 V Tolerant LVTTL Input  GTL Input and Output 3.6 V Tolerant  Vref Adjustable from 0.5 V to VCC/2  Partial Power-down Permitted  Under-Voltage Lockout (UVLO)  ESD Protection exceeds 2000 V HBM per JESD22- A114 and 1000 V CDM per JESD22-CC101  Latch-up Protection Exceeds 500 mA per JESD78  Package Offered: TSSOP14  –40°C to 85°C Operating Temperature Range

Applications

 Server  Base Station  Wire-line Communication

Description

The FXGL2014 is a 4-channel translator to interface between 3.3-V LVTTL chip set I/O and Xeon processor GTL–/GTL/GTL+ I/O. The FXGL2014 integrates ESD protection cells on all terminals and is available in a TSSOP package (5.0 mm × 4.4 mm). The device is characterized over free air temperature range of –40°C to 85°C.

Ordering Information

Temperature Range Package Packing Method FXGL2014MTCX -40 to +85°C 5.0 mm × 4.4 mm, 0.65 mm Pitch, 14 Lead

Figure 1. Analog Symbols

Figure 1. Pin Assignment (Top Through View)

www.onsemi.com © 2016 Semiconductor Components Industries, LLC FXGL2014 • Rev. 2 4 FXGL2014 — 4-Channel LVTTL to GTL Transceiver Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCC Supply Voltage -0.5 4.6 V IIK Input Clamping Current, VI<0 V -50 mA VDIR Input Control Voltages DIR -0.5 6 V VI Input Voltage A Port -0.5 6.5 V B Port -0.5 4.6 ICK Control Input Clamp Current, VO < 0 V -50 mA VO Output Voltage in Off-State A Port -0.5 6.5 V B Port -0.5 4.6 IOL Current into any output in the Low State A Port 40 mA B Port 80 IOH Current into any output in the High State -40 mA Tstg Storage Temperature Range -55 150 °C VESD Human Body Model (HBM), JEDEC: JESD22-A114 All Pins 2 kV Charged Device Model, JEDEC: JESD22-C101 All Pins 1

www.onsemi.com © 2016 Semiconductor Components Industries, LLC FXGL2014 • Rev. 2 5 FXGL2014 — 4-Channel LVTTL to GTL Transceiver Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance. ON does not recommend exceeding them or designing to Absolute Maximum Ratings. Notes: 1. Over operating free-air temperature range (unless otherwise noted). 2. All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. 3. The VI (max) of LVTTL port is 3.6 V if configured as output (DIR=L). Thermal Information Thermal Metric Value Unit RθJA Junction-to-Ambient Thermal Resistance 116 °C/W RθJC(top) Junction-to-Case (top) Thermal Resistance 17 Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 3.0 3.3 3.6 V VTT Termination Voltage GTL- 0.85 0.90 0.95 V GTL 1.14 1.20 1.26 GTL+ 1.35 1.50 1.65 VREF Reference Voltage Overall 0.5 2/3VTT VCC/2 V GTL- 0.50 0.60 0.63 GTL 0.76 0.80 0.84 GTL+ 0.87 1.00 1.10 VI Input Voltage A Port 0 3.3 5.5(3) V B Port 0 VTT 3.6 VIH High-level Input Voltage A Port and DIR 2 V B Port VREF + 50 mV VIL Low-level Input Voltage A Port and DIR 0.8 V B Port VREF – 50 mV IOL Low-level Output Current A Port 20 mA B Port 50 IOH High-level Output current A Port -20 mA

www.onsemi.com © 2016 Semiconductor Components Industries, LLC FXGL2014 • Rev. 2 6 FXGL2014 — 4-Channel LVTTL to GTL Transceiver Specified at TA = –40°C to 85°C (unless otherwise noted). Symbol Parameter Conditions –40°C to 85°C Unit Min. Typ. Max. VOH A Port VCC = 3 to 3.6 V, IOH = –100 µA VCC – 0.2 V VCC = 3 V, IOH = –16 mA 2.0 VOL A Port VCC = 3 V, IOL = 8 mA 0.28 0.40 V A Port VCC = 3 V, IOL = 12 mA 0.42 0.60 A Port VCC = 3 V, IOL = 16 mA 0.55 0.80 B Port VCC = 3 V, IOL = 40 mA 0.23 0.40 II A Port VCC = 3.6 V, VI = VCC ±1 µA VCC = 3.6 V, VI = 0 V ±1 VCC = 3.6 V, VI = 5.5 V 5 B Port VCC = 3.6 V, VI = VTT or GND ±1 µA Control Pin VCC = 3.6 V, VI = VCC or 0 V ±1 µA Ioff OFF-State Output Current on A Port VCC = 0 V, VIO = 0 to 3.6 V ±10 µA OFF-State Output Current on A Port VCC = 0 V, VIO = 3.6 to 5.5 V ±100 OFF-State Output Current on B Port VCC = 0 V, VIO = 0 to 3.6 V ±10 ICC A Port VCC = 3.6 V, VI = VCC or GND, IO = 0 3 10 mA B Port VCC = 3.6 V, VI = VTT or GND, IO = 0 3 10 mA ∆ICC A Port or Control Input VCC = 3.6 V, VI = VCC – 0.6 V 500 µA VUVLO (4) Under-Voltage Lockout Threshold VCC = 0 to 3 V 1.5 V CI (4) Input Capacitance of Control Pin VCC = 3 to 3.6 V, VI = 3.0 V or 0 V 2.0 pF CIO (4) A Port VCC = 3 to 3.6 V, VO = 3.0 V or 0 V 4.0 pF B Port VCC = 3 to 3.6 V, VO = VTT or 0 V 5.46 Note: 4. Guaranteed by characterization and / or design. Not production tested.

www.onsemi.com © 2016 Semiconductor Components Industries, LLC FXGL2014 • Rev. 2 7 FXGL2014 — 4-Channel LVTTL to GTL Transceiver Over-operating range, TA = –40°C to 85°C, VCC = 3.0 to 3.6 V, GND = 0 V for GTL. Symbol Parameter GTL− GTL GTL+ Unit VCC = 3.3 V ± 0.3 V VCC = 3.3 V ± 0.3 V VCC = 3.3 V ± 0.3 V VREF = 0.6 V VREF = 0.8 V VREF = 1 V VTT = 0.9 V VTT = 1.2 V VTT = 1.5 V tPLH Low to High Propagation Delay(5) An to Bn ns tPHL High to Low Propagation Delay(5) tPLH Low to High Propagation Delay(5) Bn to An ns tPHL High to Low Propagation Delay(5) Note: 5. Guaranteed by characterization and / or design. Not production tested.

VM = 1.5 V at VCC ≥ 3.0 V; VM = VCC at VCC ≤ 2.7 V for A ports and control pins. Figure 7. Voltage Waveforms A. All control inputs are LVTTL levels. B. CL includes probe and jig capacitance. D. The outputs are measured one at a time, with one transition per measurement.

www.onsemi.com © 2016 Semiconductor Components Industries, LLC FXGL2014 • Rev. 2 11 FXGL2014 — 4-Channel LVTTL to GTL Transceiver

Application Information

The FXGL2014 is a 4-channel translating transceiver designed for 3.3-V LVTTL system interface with a GTL – /GTL/GTL+ bus, where GTL –/GTL/GTL+ refers to the reference voltage of the GTL bus and the input/output voltage thresholds associated with it. The direction pin allows the part to function as either a GTL-to-LVTTL sampling receiver or as a LVTTL-to -GTL interface. The FXGL2014 performs translation in two directions. One direction is GTL–/GTL/GTL+ to LVTTL when DIR is tied to GND. With appropriate V REF set up, the GTL input can be compliant with GTL –/GTL/GTL+. Another direction is LVTTL to GTL –/GTL/GTL+ when DIR is tied to VCC. 3.6 V tolerance on the GTL output allows the GTL outputs to pull up to any voltage level under 3.6 V. Feature Description

5 V Tolerance on LVTTL Input

The FXGL2014 LVTTL inputs (only) are tolerant up to

5.5 V and allow direct access to TTL or 5 V CMOS

inputs. The LVTTL outputs are not 5.5 V tolerant.

3.6 V Tolerance on GTL Input / Output

The FXGL2014 GTL inputs and outputs operate up to

3.6 V, allowing the device to be used in higher voltage

open-drain output applications. Ultra-Low VREF and High Bandwidth FXGL2014’s V REF tracks down to 0.5 V for low voltage CPUs with excellent propagation delay performance. This feature allows the FXGL2014 to support high data rates with the GTL– bus. Under-Voltage Lockout (UVLO) Under-voltage lockout circuit is integrated internal. This feature makes sure the data transferred effectively when power unstable. Typical Application GTL-/GTL/GTL+ to LVTTL Select appropriate V TT/VREF based upon GTL – /GTL/GTL+. The parameters in Recommended Operating Conditions are compliant to the GTL specification. The FXGL2014 requires industrial standard LVTTL and GTL inputs. The design example in the Application Information shows standard voltage level and typical resistor values. FXGL2014 DIR GND VREF VCC GND GNDchipset FPGA VTT VCC RT R2 GTL LVTTL Figure 8. Application Diagram for GTL to LVTTL Table 1. Application Table for GTL to LVTTL Figure 9. Application Diagram for LVTTL to GTL Table 2. Application Table for LVTTL to GTL

NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 2009. E. LANDPATTERN STANDARD: SOP65P640X110-14M. DRAWING FILE NAME: MKT-MTC14rev7. 0.43TYP

0.2 C B A

A B 3.2 6.4 PIN#1 IDENT

1.2 MAX

0.1 C ALL LEAD TIPS C 0.65 0.30 0.19

0.13 A B C

0.90+0.15 -0.10 0.20 0.09 SEE DETAIL A ƒ723 %27720 GAGE PLANE 0.25 SEATING PLANE

0.09 MIN

1.00 DETAIL A RECOMMENDED LAND PATTERN 6.10 0.65 1.65 0.45

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