TPS51225_15 TI1 | Alldatasheet

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TPS51225,TPS51225B,TPS51225C www.ti.com SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 DualSynchronous,Step-DownControllerwith5-Vand3.3-VLDOs Check forSamples: TPS51225 ,TPS51225B ,TPS51225C 1FEATURES APPLICATIONS 2• InputVoltageRange: 5.5V to24 V • Notebook Computers

  • Output Voltages:5 V and 3.3V (Adjustable • Netbook,TabletComputers Range ±10%) DESCRIPTION• Built-in,100-mA, 5-V and 3.3-VLDOs The TPS51225/B/C is a cost-effective,dual-• Clock Output forCharge-Pump synchronous buck controllertargetedfornotebook• ±1% ReferenceAccuracy system-powersupplysolutions.Itprovides5-V and
  • AdaptiveOn-time D-CAP ™ Mode Control 3.3-VLDOs and requiresfew externalcomponents. The 260-kHz VCLK outputcan be used to driveanArchitecturewith300kHz/355kHz Frequency externalcharge pump, generatinggate drivevoltageSetting for the load switcheswithoutreducingthe main• Auto-skipLightLoad Operation(TPS51225/C) converterefficiency.The TPS51225/B/C supports• OOA LightLoad Operation(TPS51225B) highefficiency,fasttransientresponseand providesa combined power-good signal.Adaptiveon-time,D-• Internal0.8-msVoltageServo Soft-Start CAP ™ controlprovides convenientand efficient• Low-Side R DS(on) CurrentSensing Scheme with operation.The device operates with supply input4500 ppm/ °C Temperature Coefficient voltagerangingfrom 5.5 V to 24 V and supports
  • Built-inOutput DischargeFunction output voltages of 5.0 V and 3.3 V. The TPS51225/B/C is availablein a 20-pin,3 mm × 3• SeparateEnable InputforSwitchers mm, QFN package and isspecifiedfrom –40°C to(TPS51225/B/C) 85°C.• DedicatedOC SettingTerminals
  • Power Good Indicator
  • OVP/UVP/OCP Protection
  • Non-latchUVLO/OTP Protection
  • 20-Pin,3 mm × 3 mm, QFN (RUK) ORDERING INFORMATION (1) ORDERABLE ENABLE OUTPUTSKIP MODE ALWAYS ON-LDO PACKAGE QUANTITYFUNCTION SUPPLYDEVICE NUMBER TPS51225RUKR Tape and Reel 3000 EN1/ EN2 Auto-skip VREG3 TPS51225RUKT Minireel 250 PLASTIC QuadTPS51225BRUKR Tape and Reel 3000FlatPackEN1/ EN2 OOA VREG3 TPS51225BRUKT Minireel 250(20pinQFN) TPS51225CRUKR Tape and Reel 3000 EN1/ EN2 Auto-skip VREG3 & VREG5 TPS51225CRUKT Minireel 250 (1) Forthemost currentpackage and orderinginformationsee thePackage OptionAddendum attheend ofthisdocument,orsee theTI websiteatwww.ti.com. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2D-CAP, Out-of-AudioaretrademarksofTexas Instruments. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2012,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

5.5 V to 24 V

EN 3.3 V VOUT 3.3 V PGOOD 3.3-V Always ON UDG-12001 1 /c109F 1 /c109F 5 V Always ON VIN VBST1 TPS51225 TPS51225 B DRVH1 SW1 DRVL1 VO1 VFB1 CS1 EN1EN-5V VCLK VREG5 VIN EN 3.3 V VOUT 3.3 V PGOOD 3.3-V Always ON UDG-11182 1 /c109F 5 V 1 /c109F TPS51225,TPS51225B,TPS51225C SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. TYPICAL APPLICATION DIAGRAM (TPS51225/TPS51225B) TYPICAL APPLICATION DIAGRAM (TPS51225C)

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TPS51225,TPS51225B,TPS51225C www.ti.com SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 ABSOLUTE MAXIMUM RATINGS (1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE UNIT MIN MAX VBST1, VBST2 –0.3 32 VBST1, VBST2 (3) –0.3 6 SW1, SW2 –6.0 26 Inputvoltage(2) VIN –0.3 26 V EN1, EN2 –0.3 6 VFB1, VFB2 –0.3 3.6 VO1 –0.3 6 DRVH1, DRVH2 –6.0 32 DRVH1, DRVH2 (3) –0.3 6 DRVH1, DRVH2 (3)(pulsewidth< 20 ns) –2.5 6 Outputvoltage(2) DRVL1, DRVL2 –0.3 6 V DRVL1, DRVL2 (pulsewidth< 20 ns) –2.5 6 PGOOD, VCLK, VREG5 –0.3 6 VREG3, CS1, CS2 –0.3 3.6 HBM QSS 009-105(JESD22-A114A) 2Electrostatic kVdischarge CDM QSS 009-147(JESD22-C101B.01) 1 Junctiontemperature,TJ 150 °C Storagetemperature,TST –55 150 °C (1) Stressesbeyond thoselistedunder"absolutemaximum ratings"may cause permanentdamage tothedevice.These arestressratings onlyand functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Allvoltagevaluesarewithrespecttothenetworkgroundterminalunlessotherwisenoted (3) VoltagevaluesarewithrespecttoSW terminals. THERMAL INFORMATION TPS51225 TPS51225B THERMAL METRIC (1) UNITSTPS51225C 20-PINRUK θJA Junction-to-ambientthermalresistance 94.1 θJCtop Junction-to-case(top)thermalresistance 58.1 θJB Junction-to-boardthermalresistance 64.3 °C/W ψJT Junction-to-topcharacterizationparameter 31.8 ψJB Junction-to-boardcharacterizationparameter 58.0 θJCbot Junction-to-case(bottom)thermalresistance 5.9 (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953 . Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS51225 TPS51225B TPS51225C

TPS51225,TPS51225B,TPS51225C SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN TYP MAX UNIT Supplyvoltage VIN 5.5 24 VBST1, VBST2 –0.1 30 VBST1, VBST2 (2) –0.1 5.5 SW1, SW2 –5.5 24 V Inputvoltage(1) EN1, EN2 –0.1 5.5 VFB1, VFB2 –0.1 3.5 VO1 –0.1 5.5 DRVH1, DRVH2 –5.5 30 DRVH1, DRVH2 (2) –0.1 5.5 Outputvoltage(1) DRVL1, DRVL2 –0.1 5.5 V PGOOD, VCLK, VREG5 –0.1 5.5 VREG3, CS1, CS2 –0.1 3.5 Operatingfree-airtemperature,TA –40 85 °C (1) Allvoltagevaluesarewithrespecttothenetworkgroundterminalunlessotherwisenoted. (2) VoltagevaluesarewithrespecttotheSW terminal.

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TPS51225,TPS51225B,TPS51225C www.ti.com SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012

ELECTRICAL CHARACTERISTICS

overoperatingfree-airtemperaturerange,VVIN= 12 V,VVO1 = 5 V,VVFB1 = VVFB2 = 2 V,VEN1 = VEN2 = 3.3V (unlessotherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY CURRENT IVIN1 VIN supplycurrent-1 TA = 25°C, No load,VVO1 =0 V 860 μA IVIN2 VIN supplycurrent-2 TA = 25°C, No load 30 μA IVO1 VO1 supplycurrent TA = 25°C, No load,VVFB1 = VVFB2 =2.05V 900 μA TA = 25°C, No load,VVO1 = 0 V, TPS51225IVIN(STBY) VIN stand-bycurrent 95 μATPS51225BVEN1 = VEN2 = 0 V TA = 25°C, No load,VVO1 =0 V,VEN1 =VEN2 =0VIVIN(STBY) VIN stand-bycurrent 180 μA(TPS51225C) INTERNAL REFERENCE TA = 25°C 1.99 2.00 2.01 V VFBx VFB regulationvoltage 1.98 2.00 2.02 V VREG5 OUTPUT No load,VVO1 = 0 V,TA = 25°C 4.9 5.0 5.1 VVREG5 VREG5 outputvoltage VVIN> 7 V ,VVO1 = 0 V,IVREG5 < 100 mA 4.85 5.00 5.10 V VVIN > 5.5V ,VVO1 = 0 V,IVREG5 < 35 mA 4.85 5.00 5.10 IVREG5 VREG5 currentlimit VVIN= 7 V,VVO1 = 0 V,VVREG5 = 4.5V 100 150 mA R V5SW 5-V switchresistance VVO1 = 5 V,IVREG5 = 50 mA, TA = 25°C 1.8 Ω VREG3 OUTPUT No load,VVO1 = 0 V,TA = 25°C 3.267 3.300 3.333 VVIN > 7 V ,VVO1 = 0 V,IVREG3 < 100 mA 3.217 3.300 3.383 VVREG3 VREG3 outputvoltage 5.5V < VVIN ,VVO1 = 0 V,IVREG3 < 35 mA 3.234 3.300 3.366 V VVIN > 5.5V,VVO1 = 0 V,IVREG3 < 35 mA, 0°C ≤ TA ≤ 85°C 3.267 3.300 3.333 VVIN > 5.5V,VVO1 = 5 V,IVREG3 < 35 mA, 0°C ≤ TA ≤ 85°C 3.267 3.300 3.333 IVREG3 VREG3 currentlimit VVO1 = 0 V,VVREG3 = 3.0V,VVIN= 7 V 100 150 mA DUTY CYCLE and FREQUENCY CONTROL fSW1 CH1 frequency(1) TA = 25°C, VVIN= 20 V 240 300 360 kHz fSW2 CH2 frequency(1) TA = 25°C, VVIN= 20 V 280 355 430 kHz tOFF(MIN) Minimum off-time TA = 25°C 200 300 500 ns MOSFET DRIVERS Source,(VVBST – VDRVH )= 0.25V,(VVBST – VSW )= 5 V 3.0 R DRVH DRVH resistance Ω Sink,(VDRVH – VSW )= 0.25V,(VVBST – VSW )= 5 V 1.9 Source,(VVREG5 – VDRVL )= 0.25V,VVREG5 = 5 V 3.0 R DRVL DRVL resistance Ω Sink,VDRVL = 0.25V,VVREG5 = 5 V 0.9 DRVH-offtoDRVL-on 12 tD Dead time ns DRVL-offtoDRVH-on 20 INTERNAL BOOT STRAP SWITCH R VBST (ON) Boostswitchon-resistance TA = 25°C, IVBST = 10 mA 13 Ω IVBSTLK VBST leakagecurrent TA = 25°C 1 µA CLOCK OUTPUT R VCLK (PU) VCLK on-resistance(pull-up) TA = 25°C 10 Ω R VCLK (PD) VCLK on-resistance(pull-down) TA = 25°C 10 fCLK Clockfrequency TA = 25°C 260 kHz (1) Ensuredby design.Not productiontested. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS51225 TPS51225B TPS51225C

TPS51225,TPS51225B,TPS51225C SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 www.ti.com overoperatingfree-airtemperaturerange,VVIN= 12 V,VVO1 = 5 V,VVFB1 = VVFB2 = 2 V,VEN1 = VEN2 = 3.3V (unlessotherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT OUTPUT DISCHARGE TA = 25°C, VVO1 = 0.5VR DIS1 CH1 dischargeresistance 35 ΩVEN1 = VEN2 = 0 V TA = 25°C, VSW2 = 0.5VR DIS2 CH2 dischargeresistance 75 ΩVEN1 = VEN2 = 0 V R DIS2 CH2 dischargeresistance TA = 25°C, VSW2 = 0.5V,VEN1 = VEN2 = 0 V (TPS51225C) 70 Ω SOFT START OPERATION tSS Soft-starttime From ENx= "Hi"and VVREG5 > VUVLO5 toVOUT = 95% 0.91 ms tSSRAMP Soft-starttime(ramp-up) VOUT = 0% toVOUT = 95%, VVREG5 = 5 V 0.78 ms POWER GOOD Lower (risingedge ofPG-in) 92.5% 95.0% 97.5% Hysteresis 5% VPGTH PG threshold Upper (risingedge ofPG-out) 107.5% 110.0% 112.5% Hysteresis 5% IPGMAX PG sinkcurrent VPGOOD = 0.5V 6.5 mA IPGLK PG leakcurrent VPGOOD = 5.5V 1 µA tPGDEL PG delay From PG lowerthreshold(95%=typ)toPG flaghigh 0.7 ms CURRENT SENSING ICS CS sourcecurrent TA = 25°C, VCS = 0.4V 9 10 11 μA TC CS CS currenttemperaturecoefficient(1) On thebasisof25°C 4500 ppm/°C VCS CS Currentlimitsettingrange 0.2 2 V VZC Zerocrossdetectionoffset TA = 25°C –1 1 3 mV LOGIC THRESHOLD VENX(ON) EN thresholdhigh-level SMPS on level 1.6 V VENX(OFF) EN thresholdlow-level SMPS offlevel 0.3 V IEN EN inputcurrent VENx = 3.3V –1 1 µA OUTPUT OVERVOLTAGE PROTECTION VOVP OVP tripthreshold 112.5% 115.0% 117.5% tOVPDLY OVP propagationdelay TA = 25°C 0.5 µs OUTPUT UNDERVOLTAGE PROTECTION VUVP UVP tripThreshold 55% 60% 65% tUVPDLY UVP propdelay 250 µs tUVPENDLY UVP enabledelay From ENx ="Hi",VVREG5 = 5 V 1.35 ms UVLO Wake up 4.58 V VUVL0VIN VIN UVLO Threshold Hysteresis 0.5 V Wake up 4.38 V VUVLO5 VREG5 UVLO Threshold Hysteresis 0.4 V Wake up 3.15 V VUVLO3 VREG3 UVLO Threshold Hysteresis 0.15 V OVER TEMPERATURE PROTECTION Shutdown temperature 155 TOTP OTP threshold(1) °C Hysteresis 10 (1) Ensuredby design.Not productiontested.

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TPS51225,TPS51225B,TPS51225C www.ti.com SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 DEVICE INFORMATION RUK PACKAGE

20 PINS

(TOP VIEW) PIN FUNCTIONS PIN NO. TPS51225NAME I/O DESCRIPTION TPS51225B TPS51225C CS1 1 O Setsthechannel1 OCL triplevel. CS2 5 O Setsthechannel2OCL triplevel. DRVH1 16 O High-sidedriveroutput DRVH2 10 O High-sidedriveroutput DRVL1 15 O Low-sidedriveroutput DRVL2 11 O Low-sidedriveroutput EN1 20 I Channel1 enable. EN2 6 I Channel2 enable. PGOOD 7 O Power good outputflag.Open drainoutput.Pullup toexternalrailviaa resistor SW1 18 O Switch-nodeconnection. SW2 8 O Switch-nodeconnection. VBST1 17 I Supplyinputforhigh-sideMOSFET (bootstrapterminal).ConnectcapacitorfromthispintoSW terminal.VBST2 9 I VCLK 19 O Clockoutputforchargepump. VFB1 2 I VoltagefeedbackInput VFB2 4 I Power conversionvoltageinput.Applythesame voltageas drainvoltageofhigh-sideMOSFETs ofVIN 12 I channel1 and channel2. VO1 14 I Outputvoltageinput,5-V inputforswitch-over. VREG3 3 O 3.3-VLDO output. VREG5 13 O 5-V LDO output. Thermal — — GND terminal,soldertothegroundplanepad Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS51225 TPS51225B TPS51225C

+ + 155°C/145°C 4.5 V/4.0 V VO_OK EN FAULT REF PGOOD DCHG VIN VDDVDRV GNDPGND Switcher Controller (CH1) EN FAULT REF PGOOD DCHG VINVDD VDRV GND PGND Switcher Controller (CH2) + 2 V Osc GND (Thermal Pad) TPS51225,TPS51225B,TPS51225C SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM (TPS51225/B/C)

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VO_OK DRVL PWM Control Logic UDG-12007 VREF +15% SKIP UV OV VREF –40% VIN GND REF One-Shot Discharge 10 µA VBST DRVH FAULT PGOOD CS VFB OC SS Ramp Comp VREF +5%/10% VREF –5%/10% EN VDD HS LS VDRV PGND PGOOD TPS51225,TPS51225B,TPS51225C www.ti.com SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 SWITCHER CONTROLLER BLOCK DIAGRAM Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS51225 TPS51225B TPS51225C

/c40 /c41 /c40 /c41 /c45 /c180/c61 /c180 /c180 /c180 IN OUT OUT OUT LL SW IN V V V1I 2 L f V TPS51225,TPS51225B,TPS51225C SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 www.ti.com DETAILED DESCRIPTION PWM Operations The main controlloopoftheswitchmode power supply(SMPS) isdesignedas an adaptiveon-timepulsewidth modulation(PWM) controller.Itsupportsa proprietaryD-CAP ™ mode. D-CAP ™ mode does notrequireexternal conpensationcircuitand issuitableforlow externalcomponent countconfigurationwhen used withappropriate amount ofESR attheoutputcapacitor(s). At thebeginningofeach cycle,thesynchronoushigh-sideMOSFET isturnedon,or enterstheON state.This MOSFET isturnedoff,orentersthe‘OFF state,aftertheinternal,one-shottimerexpires.The MOSFET isturned on againwhen the feedbackpointvoltage,VVFB , decreasedto match the internal2-V reference.The inductor currentinformationisalsomonitoredand shouldbe below theovercurrentthresholdtoinitiatethisnew cycle.By repeatingthe operationinthismanner, the controllerregulatesthe outputvoltage.The synchronouslow-side (rectifying)MOSFET isturnedon atthebeginningofeach OFF statetomaintaina minimum ofconductionloss. The low-sideMOSFET isturnedoffbeforethe high-sideMOSFET turnson at nextswitchingcycleor when inductorcurrentinformationdetectszero level.This enables seamless transitionto the reduced frequency operationduringlight-loadconditionsso thathighefficiencyismaintainedovera broadrangeofloadcurrent. AdaptiveOn-Time/ PWM Frequency Control Bacause the TPS51225/B/C does not have a dedicatedoscillatorforcontrolloopon board,switchingcycleis controlledby the adaptiveon-timecircuit.The on-timeiscontrolledto meet the targetswitchingfrequencyby feed-forwardingtheinputand outputvoltageintotheon-timeone-shottimer.The targetswitchingfrequencyis variedaccordingto the inputvoltageto achievehigherdutyoperationforlowerinputvoltageapplication.The switchingfrequencyofCH1 (5-Voutput)is300 kHz duringcontinuousconductionmode (CCM) operationwhen VIN = 20 V.The CH2 (3.3-Voutput)is355 kHz duringCCM when VIN = 20 V. LightLoad ConditioninAuto-SkipOperation(TPS51225/C) The TPS51225/C automaticallyreduces switchingfrequencyduringlight-loadconditionsto maintainhigh efficiency.Thisreductionoffrequencyisachievedsmoothlyand withoutan increaseinoutputvoltageripple.A more detaileddescriptionof thisoperationis as follows.As the outputcurrentdecreases from heavy-load condition,the inductorcurrentisalsoreduced and eventuallyapproaches valleyzero current,which isthe boundarybetween continuousconductionmode and discontinuousconductionmode. The rectifyingMOSFET is turnedoffwhen thiszeroinductorcurrentisdetected.As theloadcurrentfurtherdecreases,theconverterrunsin discontinuousconductionmode and ittakeslongerand longertodischargetheoutputcapacitortothelevelthat requiresthenextON cycle.The ON timeismaintainedthesame as thatintheheavy-loadcondition.Inreverse, when theoutputcurrentincreasefrom lightloadtoheavy load,theswitchingfrequencyincreasestothepreset valueas the inductorcurrentreachesto the continuousconduction.The transitionloadpointto the lightload operationIOUT(LL) (i.e.thethresholdbetween continuousand discontinuousconductionmode) can be calculated as shown inEquation1. where

  • fSW isthePWM switchingfrequency (1) Switchingfrequencyversus outputcurrentduringlight-loadconditionsis a functionof inductance(L),input voltage(VIN) and outputvoltage(VOUT ),but itdecreasesalmostproportionalto the outputcurrentfrom the IOUT(LL).

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/c61 /c163/c112 /c180 /c180 SW OUT f1f 2 ESR C 4 Voltage Divider VFB VREF PWM Control Logic and Divider L ESR COUT VC RLOAD IIND IOUT UDG-12010 IC Switching Modulator Output Capacitor VOUT TPS51225 TPS51225B TPS51225C VIN DRVH DRVL TPS51225,TPS51225B,TPS51225C www.ti.com SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 Light-LoadConditioninOut-of-Audio™ Operation(TPS51225B) Out-of-Audio™ (OOA) light-loadmode isa unique controlfeaturethatkeeps the switchingfrequencyabove acousticaudiblefrequenciestoward a virtualno-loadcondition.During Out-of-Audio™ operation,the OOA controlcircuitmonitorsthe statesof both MOSFETs and forcesthem to transitionintothe ON stateifboth of MOSFETs are offformore than40 μs.When bothhigh-sideand low-sideMOSFETs are offfor40 µs duringa light-loadcondition,theoperationmode ischanged toFCCM. Thismode change initiatesthelow-sideMOSFET on and pullsdown theoutputvoltage.Then,thehigh-sideMOSFET isturnedon and stopsswitchingagain. Table1.SKIP Mode Operation(TPS51225/B/C) SKIP MODE OPERATION TPS51225 Auto-skip TPS51225B OOA TPS51225C Auto-skip D-CAP ™ Mode From small-signalloopanalysis,a buck converterusingD-CAP ™ mode can be simplifiedas shown inFigure1. Figure1. SimplifyingtheModulator The outputvoltageiscompared withinternalreferencevoltageafterdividerresistors,R1 and R2. The PWM comparatordeterminesthe timingto turnonthe high-sideMOSFET. The gainand speed of the comparatoris highenough tokeep thevoltageatthebeginningofeach ON cyclesubstantiallyconstant.For theloopstability, the0dB frequency,ƒ0,definedinEquation2 must be lowerthan1/4oftheswitchingfrequency. (2) As ƒ0 isdeterminedsolelyby the outputcapacitorcharacteristics,the loopstabilityduringD-CAP ™ mode is determinedby thecapacitorchemistry.Forexample,specialtypolymercapacitorshave outputcapacitanceinthe orderofseveralhundredmicro-Faradsand ESR inrangeof10 milli-ohms.These yieldan f0 valueon theorder of100 kHz orlessand theloopisstable.However,ceramiccapacitorshave ƒ0 atmore than700 kHz,whichis notsuitableforthisoperationalmode. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS51225 TPS51225B TPS51225C

VIN-UVLO_threshold EN_threshold 95% of VOUT 95% of Vout EN_threshold VIN VREG3 EN1 VREG5 5-V VOUT PGOOD EN2 Soft-Start Time (tSS) Soft-Start Time (tSS(ramp)) Soft-Start Time (tSS) Soft-Start Time (tSS(ramp)) PGOOD Delay tPGDEL 3.3-V VOUT UDG-12013 VREG5-UVLO_threshold TPS51225,TPS51225B,TPS51225C SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 www.ti.com Enable and Powergood VREG3 isan always-onregulator(TPS51225/B),VREG3/VREG5 arealways-onregulators(TPS51225C),when the inputvoltageisbeyond the UVLO thresholditturnsON. VREG5 isturnedON when eitherEN1 or EN2 enterstheON state.The VCLK signalinitiateswhen EN1 enterstheON state(TPS51225/B/C).Enable states areshown inTable2 throughTable3. Table2.Enabling/PGOOD State(TPS51225/B) EN1 EN2 VREG5 VREG3 CH1 (5Vout) CH2 (3.3Vout) VCLK PGOOD OFF OFF OFF ON OFF OFF OFF Low ON OFF ON ON ON OFF ON Low OFF ON ON ON OFF ON OFF Low ON ON ON ON ON ON ON High Table3.Enabling/PGOOD State(TPS51225C) EN1 EN2 VREG5 VREG3 CH1 (5Vout) CH2 (3.3Vout) VCLK PGOOD OFF OFF ON ON OFF OFF OFF Low ON OFF ON ON ON OFF ON Low OFF ON ON ON OFF ON OFF Low ON ON ON ON ON ON ON High Figure2. TPS51225 and TPS51225B Timing

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VIN-UVLO_threshold 95% of VOUT 95% of Vout EN_threshold VIN VREG3 VREG5 5-V VOUT PGOOD EN2 Soft-Start Time (tSS) Soft-Start Time (tSS(ramp)) Soft-Start Time (tSS) Soft-Start Time (tSS(ramp)) PGOOD Delay tPGDEL 3.3-V VOUT UDG-12015 EN_threshold EN1 2.4 V TPS51225,TPS51225B,TPS51225C www.ti.com SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 Figure3. TPS51225C Timing Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS51225 TPS51225B TPS51225C

/c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41IND ripple IN OUT OUTTRIP TRIP OCP SW INDS on DS on I V V VV V 1I R 2 R 2 L f V /c45 /c180/c61 /c43 /c61 /c43 /c180 /c180 /c180 CS CS TRIP R IV 1 mV 8 /c180/c61 /c43 TPS51225,TPS51225B,TPS51225C SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 www.ti.com Soft-Startand Discharge The TPS51225/B/C operatesan internal,0.8-ms,voltageservosoft-startforeach channel.When theENx pin becomes higherthantheenablethresholdvoltage,an internalDAC beginsrampingup thereferencevoltageto thePWM comparator.Smooth controloftheoutputvoltageismaintainedduringstart-up.When ENx becomes lowerthan the lowerlevelof thresholdvoltage,TPS51225/B/C dischargesoutputsusinginternalMOSFETs throughVO1 (CH1) and SW2 (CH2). VREG5/VREG3 LinearRegulators There are two setsof100-mA standbylinearregulatorswhich output5 V and 3.3V, respectively.The VREG5 pinprovidesthecurrentforthegatedrivers.The VREG3 pinfunctionsas themain power supplyfortheanalog circuitryofthedevice.VREG3 isan AlwaysON LDO and TPS51225C has AlwaysON VREG5. (seeTable2 and Table3) Add ceramiccapacitorswitha valueof 1 µF or larger(X5R grade or better)placedcloseto the VREG5 and VREG3 pinstostabilizeLDOs. The VREG5 pinswitchoverfunctionisassertedwhen threeconditionsarepresent:

  • CH1 internalPGOOD ishigh
  • CH1 isnotinOCL condition
  • VO1 voltageishigherthanVREG5-1V Inthisswitchovercondition,threethingsoccur:
  • theinternal5-V,LDO regulatorisshutoff
  • theVREG5 outputisconnectedtoVO1 by internalswitchoverMOSFET
  • VREG3 inputpass ischanged fromVIN toVO1 VCLK forCharge Pump The 260-kHz VCLK signalcan be used inthechargepump circuit.The VCLK signalbecomes availablewhen EN1. The VCLK driverisdrivenby VO1 voltage.Ina designthatdoes notrequireVCLK output,leavetheVCLK pinopen. OvercurrentProtection TPS51225/B/C has cycle-by-cycleovercurrentlimitingcontrol.The inductorcurrentismonitoredduringtheOFF stateand the controllermaintainsthe OFF stateduringthe inductorcurrentislargerthan the overcurrenttrip level.Inordertoprovidebothgood accuracyand costeffectivesolution,TPS51225/B/C supportstemperature compensated MOSFET R DS(on) sensing.The CSx pin shouldbe connectedto GND throughthe CS voltage settingresistor,R CS .The CSx pinsourcesCS current(ICS )whichis10 µA typicallyatroom temperature,and the CSx terminalvoltage(VCS = R CS × ICS ) shouldbe intherange of0.2V to2 V overalloperationtemperatures. The triplevelissettotheOCL tripvoltage(VTRIP)as shown inEquation3. (3) The inductorcurrentismonitoredby the voltagebetween GND pinand SWx pinso thatSWx pinshouldbe connected to the drainterminalof the low-sideMOSFET properly.TheCS pin currenthas a 4500 ppm/°C temperatureslopeto compensate the temperaturedependency of the R DS(on). GND isused as the positive currentsensingnode so thatGND shouldbe connectedtothesourceterminalofthelow-sideMOSFET. As thecomparisonisdone duringtheOFF state,VTRIP setsthevalleyleveloftheinductorcurrent.Thus,theload currentattheovercurrentthreshold,IOCP ,can be calculatedas shown inEquation4. (4) Inan overcurrentcondition,thecurrenttotheloadexceeds thecurrenttotheoutputcapacitorthustheoutput voltagetends to falldown. Eventually,itends up withcrossingthe undervoltageprotectionthresholdand shutdownbothchannels.

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TPS51225,TPS51225B,TPS51225C www.ti.com SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 Output Overvoltage/UndervoltageProtection TPS51225/B/C assertstheovervoltageprotection(OVP) when VFBx voltagereachesOVP tripthresholdlevel. When an OVP eventisdetected,thecontrollerchanges theoutputtargetvoltageto0 V. Thisusuallyturnsoff DRVH and forcesDRVL tobe on.When theinductorcurrentbeginstoflowthroughthelow-sideMOSFET and reachesthenegativeOCL, DRVL isturnedoffand DRVH isturnedon.Aftertheon-timeexpires,DRVH isturned offand DRVL isturnedon again.Thisactionminimizestheoutputnode undershootdue toLC resonance.When theVFBx reaches0V, thedriveroutputislatchedas DRVH off,DRVL on.The undervoltageprotection(UVP) latchissetwhen theVFBx voltageremainslowerthanUVP tripthresholdvoltagefor250 µs or longer.Inthis faultcondition,the controllerlatchesDRVH low and DRVL low and dischargesthe outputs.UVP detection functionisenabledafter1.35ms ofSMPS operationtoensurestartup. UndervoltageLockout (UVLO) Protection TPS51225/B/C has undervoltagelockoutprotectionatVIN,VREG5 and VREG3. When each voltageislower thantheirUVLO thresholdvoltage,bothSMPS areshut-off.They arenon-latchprotections. Over-TemperatureProtection TPS51225/B/C featuresan internaltemperaturemonitor.Ifthe temperatureexceeds the thresholdvalue (typically155°C),TPS51225/B/C isshutoffincludingLDOs. Thisisnon-latchprotection. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS51225 TPS51225B TPS51225C

(2) tON tOFF Slope (2) Jitter 20 mV Slope (1) Jitter UDG-12012 VREF +Noise (1) /c40 /c41 OUT SW IND ripple V 20 mV (1 D) 20 mV L fESR 2 V I 2 V /c180 /c180 /c45 /c180 /c180/c61 /c61 /c180 /c40 /c41 /c40 /c41 /c40 /c41/c40 /c41 /c40 /c41 IN OUT OUTmaxTRIP IND peak SW INDS on max V V VV 1I R L f V /c45 /c180 /c61 /c43 /c180 /c180 /c40 /c41 /c40 /c41/c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41/c40 /c41/c45 /c180 /c45 /c180 /c61 /c180 /c61 /c180 /c180 /c180 IN OUT OUT IN OUT OUTmax max SW IN OUT SW IN(max)IND ripple max max V V V V V V1 3L I f V I f V /c40 /c41 OUT RIPPLEV 0.5 V 2.0R1 R2 2.0 /c45 /c180 /c45/c61 /c180 TPS51225,TPS51225B,TPS51225C SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 www.ti.com ExternalComponents Selection The externalcomponents selectionisrelativelysimplefora designusingD-CAP ™ mode. Step 1.Determine theValue ofR1 and R2 The recommended R2 valueisbetween 10 kΩ and 20 kΩ.DetermineR1 usingEquation5. (5) Step 2.Choose theInductor The inductancevalueshouldbe determinedtogivetheripplecurrentofapproximately1/3ofmaximum output current.Largerripplecurrentincreasesoutputripplevoltage,improvessignal:noiseratio,and helpsensurestable operation. (6) The inductoralsoneeds to have low DCR to achievegood efficiency,as wellas enough room above peak inductorcurrentbeforesaturation.The peak inductorcurrentcan be estimatedas shown inEquation7. (7) Step 3.Choose Output Capacitor(s) Organicsemiconductorcapacitor(s)orspecialtypolymercapacitor(s)arerecommended. DetermineESR tomeet requiredripplevoltageabove.A quickapproximationisas shown inEquation8. where

  • D as theduty-cyclefactor
  • therequiredoutputripplevoltageslopeisapproximately20 mV pertSW (switchingperiod)intermsofVFB terminal (8) Figure4. RippleVoltageSlope and JitterPerformance

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TPS51225,TPS51225B,TPS51225C www.ti.com SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 Layout Considerations Good layoutisessentialforstablepower supplyoperation.Followtheseguidelinesforan efficientPCB layout. Placement

  • Placevoltagesettingresistorsclosetothedevicepins.
  • PlacebypasscapacitorsforVREG5 and VREG3 closetothedevicepins. Routing (Sensitiveanalog portion)
  • Use smallcopperspace forVFBx. Thereareshortand narrowtracestoavoidnoisecoupling.
  • Connect VFB resistortracetothepositivenode oftheoutputcapacitor.Routinginnerlayeraway frompower tracesisrecommended.
  • Use shortand widetracefromVFB resistortoviastoGND (internalGND plane). Routing (Power portion)
  • Use wider/shortertracesofDRVL forlow-sidegatedriverstoreducestrayinductance.
  • Use the paralleltracesof SW and DRVH forhigh-sideMOSFET gate driveina same layeror on adjoin layers,and keep them away fromDRVL.
  • Use wider/shortertracesbetween thesourceterminalofthehigh-sideMOSFET and thedrainterminalofthe low-sideMOSFET
  • Thermalpad istheGND terminalofthisdevice.Fiveormore viaswith0.33-mm (13-mils)diameterconnected fromthethermalpad totheinternalGND planeshouldbe used tohave strongGND connectionand helpheat dissipation. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS51225 TPS51225B TPS51225C

−40 −25 −10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C) CS Source Current (µA) G005 210 220 230 240 250 260 270 280 290 300 310 −40 −25 −10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C) VCLK Frequency (kHz) G006 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 −40 −25 −10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C) VO1 Supply Current 1 (mA) G003 100 150 200 250 300 −40 −25 −10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C) VIN Stand−By Current (µA) TPS51225C Only G004 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 −40 −25 −10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C) VIN Supply Current 1 (mA) G001 −40 −25 −10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C) VIN Supply Current 2 (µA) G002 TPS51225,TPS51225B,TPS51225C SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS Figure5.VIN Supply Current1 vs.JunctionTemperature Figure6.VIN Supply Current2 vs.JunctionTemperature Figure7.VO1 Supply Current1 vs.JunctionTemperature Figure8.VIN Stand-By Currentvs.JunctionTemperature Figure9.CS Source Currentvs.JunctionTemperature Figure10.Clock Frequency vs.JunctionTemperature

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0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) VVIN = 8 V VVIN = 12 V VVIN = 20 V Auto−Skip VVOUT = 3.3 V G010 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) VVIN = 8 V VVIN = 12 V VVIN = 20 V Out−of_Audio VVOUT = 3.3 V G011 4.85 4.90 4.95 5.00 5.05 5.10 5.15 0.001 0.01 0.1 1 10 Output Current (A) Output Volage (V) VVIN = 8 V VVIN = 12 V VVIN = 20 V Auto−Skip VVOUT = 5 V G014 4.85 4.90 4.95 5.00 5.05 5.10 5.15 0.001 0.01 0.1 1 10 Output Current (A) Output Volage (V) VVIN = 8 V VVIN = 12 V VVIN = 20 V Out−of−Audio VVOUT = 5 V G015 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) VVIN = 8 V VVIN = 12 V VVIN = 20 V Auto−Skip VVOUT = 5 V G007 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) VVIN = 8 V VVIN = 12 V VVIN = 20 V Out−of−Audio VVOUT = 5 V G008 TPS51225,TPS51225B,TPS51225C www.ti.com SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS (continued) Figure11.Efficiencyvs.Output Current Figure12.Efficiencyvs.Output Current Figure13.Load Regulation Figure14.Load Regulation Figure15.Efficiencyvs.Output Current Figure16.Efficiencyvs.Output Current Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS51225 TPS51225B TPS51225C

0.001 0.01 0.1 1 10 Output Current (A) Switching Frequency (kHz) VVIN = 8 V VVIN = 12 V VVIN = 20 V Auto−Skip VVOUT = 3.3 V G018 100 150 200 250 300 350 400 450 0.001 0.01 0.1 1 10 Output Current (A) Switching Frequency (kHz) VVIN = 8 V VVIN = 12 V VVIN = 20 V Out−of−Audio VVOUT = 3.3 V G019 100 150 200 250 300 350 0.001 0.01 0.1 1 10 Output Current (A) Switching Frequency (kHz) VVIN = 8 V VVIN = 12 V VVIN = 20 V Auto−Skip VVOUT = 5 V G016 100 150 200 250 300 350 0.001 0.01 0.1 1 10 Output Current (A) Switching Frequency (kHz) VVIN = 8 V VVIN = 12 V VVIN = 20 V Out−of−Audio VVOUT = 5 V G017 3.23 3.28 3.33 3.38 3.43 0.001 0.01 0.1 1 10 Output Current (A) Output Volage (V) VVIN = 8 V VVIN = 12 V VVIN = 20 V Auto−skip VVOUT = 3.3 V G012 3.23 3.28 3.33 3.38 3.43 0.001 0.01 0.1 1 10 Output Current (A) Output Volage (V) VVIN = 8 V VVIN = 12 V VVIN = 20 V Out−of−Audio VVOUT = 3.3 V G013 TPS51225,TPS51225B,TPS51225C SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure17.Load Regulation Figure18.Load Regulation Figure19.SwitchingFrequency vs.Output Current Figure20.SwitchingFrequency vs.Output Current Figure21.SwitchingFrequency vs.Output Current Figure22.SwitchingFrequency vs.Output Current

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Input Voltage (V) Switching Frequency (kHz) VOUT = 5 V IOUT = 6 A G000 100 150 200 250 300 350 400 450 500 5 10 15 20 25 Input Voltage (V) Switching Frequency (kHz) VOUT = 3.3 V IOUT = 6 A G000 Time (100 µs/div) VVIN = 12 V IOUT 3A /c223/c2248 A VOUT 1(50 mV/div) SW1 (10 V/div) VOUT 20 A( 50 mV/div) IIND 1 (5 A/div) VVIN = 12 V IOUT 3A /c223/c2248 A VOUT 1(50 mV/div) SW1 (10 V/div) VOUT 20 A ( 50 mV/div) Time (100 µs/div) IIND 1 (5 A/div) VOUT1 (2 V/div) PGOOD (5 V/div) VOUT2 (2 V/div) Time (400 µs/div) EN1 = EN2 (5 V/div) VOUT1 (2 V/div) EN1 = EN2 (5 V/div) VOUT2 (2 V/div) PGOOD (5 V/div) Time (10 ms/div) TPS51225,TPS51225B,TPS51225C www.ti.com SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS (continued) Figure23.Start-Up Figure24.Output Discharge Figure25.5-V Load Transient Figure26.3.3-VLoad Transient Figure27.SwitchingFrequency vs.InputVoltage Figure28.SwitchingFrequency vs.InputVoltage Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS51225 TPS51225B TPS51225C

0.1 µF 15.3 k/c87 DRVL115 VO114 VFB12 CS11 EN120 51 k/c87 10 k/c87 EN 5V 0.1 µF 0.1 µF VCLK19 VREG513 10 µF x 2 VIN VOUT

5 V-8A

10 µF x 2 0.1 µF 6.57 k/c87 47 k/c87 10 k/c87 EN 3.3 V 1 µF VOUT

3.3 V - 8A

(3.3-V LDO) UDG-12008 2.2 /c87 2.2 /c87 0.1 µF GND 0.1 µF VREG5 (5-V LDO) 1 µF TPS51225,TPS51225B,TPS51225C SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 www.ti.com APPLICATION DIAGRAM (TPS51225/TPS51225B/TPS51225C) Table4.Key ExternalComponents (APPLICATION DIAGRAM (TPS51225/TPS51225B/TPS51225C) ) REFERENCE FUNCTION MANUFACTURER PART NUMBERDESIGNATOR L1 OutputInductor(5-VOUT ) Toko FDVE1040-3R3M L2 OutputInductor(3.3-VOUT ) Toko FDVE1040-2R2M C1 OutputCapacitor(5-VOUT ) SANYO 6TPE330MIL x 2 C2 OutputCapacitor(3.3-VOUT ) SANYO 4TPE470MIL Q1 High-sideMOSFET (5-VOUT ) Fairchild FDMC7692 Q2 High-sideMOSFET (3.3-VOUT ) Fairchild FDMC7692 Q3 Low-sideMOSFET (5-VOUT ) Fairchild FDMC7672 Q4 Low-sideMOSFET (3.3-VOUT ) Fairchild FDMC7672

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TPS51225,TPS51225B,TPS51225C www.ti.com SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012 Changes from Original(January2012)toRevisionA Page Changes from RevisionA (JUNE 2012)toRevisionB Page Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS51225 TPS51225B TPS51225C

www.ti.com 24-Oct-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples FX011Z ACTIVE WQFN RUK 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 51225 TPS51225BRUKR ACTIVE WQFN RUK 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 1225B TPS51225BRUKT ACTIVE WQFN RUK 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 1225B TPS51225CRUKR ACTIVE WQFN RUK 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 1225C TPS51225CRUKT ACTIVE WQFN RUK 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 1225C TPS51225RUKR ACTIVE WQFN RUK 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 51225 TPS51225RUKT ACTIVE WQFN RUK 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 51225 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

www.ti.com 24-Oct-2014 Addendum-Page 2 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 31-Oct-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51225BRUKR WQFN RUK 20 3000 367.0 367.0 35.0 TPS51225BRUKR WQFN RUK 20 3000 367.0 367.0 35.0 TPS51225BRUKT WQFN RUK 20 250 210.0 185.0 35.0 TPS51225CRUKR WQFN RUK 20 3000 367.0 367.0 35.0 TPS51225CRUKR WQFN RUK 20 3000 367.0 367.0 35.0 TPS51225CRUKT WQFN RUK 20 250 210.0 185.0 35.0 TPS51225RUKR WQFN RUK 20 3000 367.0 367.0 35.0 TPS51225RUKR WQFN RUK 20 3000 367.0 367.0 35.0 TPS51225RUKT WQFN RUK 20 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 31-Oct-2015 Pack Materials-Page 2

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