FX009LG

FX009 CMLMICRO | Alldatasheet

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—) PRODUCT INFORMATION FX009 Digitally Controlled Amplifier Array Publication D/009/3 December 1991 Provisional Issue

8 Digitally Controlled Amplifiers 8-Bit Serial Data Control

15 Gain/Attenuation Steps Output Mute/Powersave Function

7 Trimmers, with a + 3dB Range Audio and Data Gain Control

in 0.43dB Steps Applications 1 ‘Volume’ Trimmer, with a + 14dB Cellular, PMR, PABX Applications Range in 2.0dB Steps SERIAL CLOCK INPUT 8. BIT LOADALATCH SERIAL DATA INPUT SERIAL DATA INPUT LINE DECODERS TOADLATCH Yoo « Vous iy 16-LINE STEP CONTROLS TO AMPLIFIERS 1 to 8 5 Cht *ouTmUT MITE POWERSAVE * Chs

2 Vans Vas 6

“ : : * FX009

3 Veusi Vans 7

Ch3 * “ Ch7 ch4 . - LY & che 49°21 8 6 7 B-VOLUME Ao CONTROLLED AUDIO OUTPUT LINES Fig.1 Functional Block Diagram The FX009 Digitally Adjustable Amplifier Array is This product replaces the need for manual trimming of intended to replace trimmer potentiometers and volume audible signals by using the host microprocessor to controls in Cellular, PMR, Telephony and digitally control the set-up of all audio levels. Communications applications where d.c., voice or data . signals need adjustment. 1) Cont adjustment and set-up of communications The FX009 is a single-chip LSI consisting eight digitally equipment by an Intelligent ATE without manual controlled amplifier stages, each with 15 distinct gain/ - aoe . aati an intervention — eg. Deviation, Microphone and L/S. attenuation steps. Control of each individual amplifier Level, Rx Audio Level etc is by an 8-bit serial data stream. Seven of the amplifier noe . oo . . stages offer a +/-3dB range in steps of 0.43dB, whilst (ii) Automatic Dynamic Compensation of drift caused the remaining amplifier offers a +/-14dB range in steps by variations in temperature, linearity, etc. of 2dB, and is intended for volume contro! applications. (iii) Fully automated servicing and re-alignment. Each amplifier includes a 16th ‘Mute’ state which sets The FX009 is a low-power, single 5-volt CMOS device the output to bias (V,,/2) and powersaves the entire available in both 24-pin DIL and SMD package section. Minimum current drain may be achieved by versions. muting all eight sections.

FXx009J | FXOO9LG/LS 1 1 Serial Clock : This external clock pulse input is used to “clock in” the Control Data. See Figure 4, Data Load Timing. This input has an internal 1MQ pullup resistor. 2 2 Load/Latch : Governs the loading and execution of the control data. During serial data loading this input should be kept at a logical '0' to ensure that data rippling past the latches has no effect. When all 8 bits have been loaded, this input should be strobed '0' = '1' = ‘0' to latch the new data in. Data is executed on the falling edge of the strobe. If the Load/Latch input is used this pin should be left open circuit. This input has an internal 1MQ pullup resistor. 3 3 Load/Latch : The inverted Load/Latch input. This function governs the loading and execution of the control data. During serial data loading this input should be kept at a logical '1' to ensure that data rippling past the latches has no effect. When all 8 bits have been loaded, this input should be strobed '1' = '0' = '1' to latch the new data in. Data is executed on the rising edge of the strobe. If the Load/Latch input is used this pin should be left open circuit. This input has an internal 1MQ pulldown resistor. 4 4 Ch1 Input : Analogue Inputs : These individual amplifier inputs are self-biasing, a.c. input 5 5 Ch2 Input : analogue signals must be capacitively coupled to these pins, | as shown in Figure 2. 6 6 Ch3 Input : In the powersave modes the inputs are biased at V,,/2. 7 7 Ch4 Input : Note that amplifiers Ch1 to Ch8 are ‘inverting amplifiers.’ 8 8 Vass ? The output of the on-chip bias circuitry, held at V,,/2. This pin should be decoupled to V., as shown in Figure 2. 9 9 Ch5 Input : Analogue Inputs : 10 10 Ch6 Input : 1 11 Ch7 Input : 12 12 Ch8 Input : 13 13 Vgg : Negative supply rail (GND). 14 14 Ch8 Output : Analogue Outputs : 15 15 Ch7 Output : The individual "Gain Controlled" amplifier outputs. \\ Ch1 to Ch7 range from -3dB to +3dB in 0.43dB steps, Ch8 16 16 Ch6 Output : could be utilized as a volume control, ranging from -14dB to +14dB in 2.0dB steps. 17 7 Ch5 Output : In the powersave mode the selected output is biased at V,,/2. 18 18 No internal connection. Do not use. 19 19 Ch4 Output : Analogue Outputs 20 20 Ch3 Output : Note that amplifiers Ch1 to Ch8 are ‘inverting amplifiers.’ 21 21 Ch2 Output : 22 22 Ch1 Output : 23 23 Vop : Positive supply rail. A single +5-volt power supply is required. 24 24 Control Data Input : Operation of the 8 amplifier channels (Ch1 - Ch8) is controlled by the 8 bits of data entered serially at this pin. The data is entered (bit 7 to bit 0) on the rising edge of the external Serial Clock. The data format is described in Tables 1, 2 and Figure 4. This input has an internal 1MQ pullup resistor.

Ves —L— ‘SERIAL CLOCK INPUT 1 24 SERIAL CONTROL DATA INPUT LOAD/CATCH 2 23 [J Voo COABLATCH 3 2 CHANNEL 1 OUTPUT CHANNEL 1 INPUT Cy 4 a1 CHANNEL 2 OUTPUT CHANNEL 2 INPUT_C2 5 2 CHANNEL 3 OUTPUT CHANNEL 3 INPUT Cs 6 FXx009 19 CHANNEL 4 OUTPUT CHANNEL 4 INPUT o4 7 2. Vous Py J-LG-LS . * CHANNEL § OUTPUT CHANNEL 5 INPUT C5 [| ° ‘6 CHANNEL 6 OUTPUT (CHANNEL 6 INPUT cy —_ 10 18 CHANNEL 7 OUTPUT CHANNEL 7 INPUT C7 | 4 ‘ CHANNEL 8 OUTPUT CHANNEL 8 INPUT Ca [die i Ves Cy Notes Ves Component Unit Value (1) Channel Amplifiers 1 to 8 are inverting amplifiers. C,to 6, Otp (2) Analogue input capacitors C, to C, are only required for a.c. c, 1.0p input signals, d.c. input signals do not require these c,, 1.0, components. Tolerances: C = + 20% Fig.2 External Component Connections Application Recommendations To avoid excess noise and instability in the final installation it is recommended that the following points be noted. (a) A noisy or badly regulated power supply can (f) Analogue tracks should not run parallel to digital cause instability and/or variance of selected gains. tracks. (b) Care should be taken on the design and layout of (g) A"Ground Plane" connected to V,, will assist in the printed circuit board. eliminating external pick-up on the channel input and (c) All external components (Figure 2) should be output pins. kept close to the FX009 package. (h) Do not run high-level output tracks close to low- (d) Inputs and outputs should be screened wherever _ level input tracks. possible. (i) Input signal amplitudes should be applied with due (e) Tracks should be kept short. regard to Figure 3. SINAD (4B) 50, Input Frequency = 1.0kHz input Level OdB ref: = 775mVrms Ch1 to Ch8 Gain Set to OdB 40. 10000 1730.0 “40 “30 2007 “10 INPUT eve. oB Fig.3 SINAD vs Input Level — Typical Values

The gain of each amplifier block (Channel 1 to Channel 8) _Datais loaded to the FX009 on the rising edge of the Serial in the FX009 is set by a separate 8-bit data word (bit 7to Clock. Loaded datais executed on the falling (rising) edge bit 0 ). This 8-bit word, consisting of 4 Address bits (bit 7 of the Load/Latch (Load/Latch) pulse. Table 1 shows the to bit 4) and 4 Gain Control bits (bit 3 to bit 0), is loaded format of each 4-bit Address word, Table 2 shows the tothe Control Data Input in serial format using the external format of each Gain Control word with Figure 4 describing data clock. the data loading operation and timing. Table 1 Address Word Format Table 2 Gain Control Word Format Bit7 Bité Bits Bit4 Channel Bits Bit2 Bit1 BitO Stage1to7 Stages MSB LSB Selected MSB LSB (0.43dB) (2.0dB) 1 0 0 0 1 0 0 0 0 Powersave = Powersave 1 0 0 1 2 O 0 0 1 3.0 -14.0 dB 1 0 1 ) 3 0 oO 1 0 2.571 12.0 dB 1 0 1 1 4 () () 1 1 2.143 10.0 4B 1 1 0 } 5 0 1 0 te) 1.714 8.0 dB 1 1 0 1 6 0 1 i) 1 -1.286 6.0 dB 1 1 1 [} 7 0 1 1 0 -0.857 4.0 dB 1 1 1 1 8 0 1 1 1 0.428 2.0 dB 1 0 0 0 0 Oo dB 1 () 0) 1 0.428 2.0 dB Data Loading 1 t) 1 t) 0.857 4.0 dB The 8-bit data word is loaded bit 7 first and bit 0 last. 1 ° 1 1 1.286 6.0 4B Bit 7 must be a logic “1” to address the chip. 1 1 ° o 1.714 8.0 dB If bit 7 in the word is a logic “0” that 8-bit word will not be 1 1 0 1 2.143 10.0 dB executed. Figure 4 (below) shows the timing information 1 1 1 oO 2.571 12.0 dB required to load and operate this device. 1 1 1 1 3.0 14.0 dB SERIAL DATA CLOCK \\ ‘ ais y . towne Lo j ftom i E | SERIAL DATAIN, | tos —> [+ ton be Ef BIT7 BT6 oem BITO | Ef +— te —+ Timing So ; tos he Serial Clock “High” Pulse Width Data Set-up Time Load/Latch Set-up Time ow. ton lw Serial Clock "Low" Pulse Width Data Hold Time Load/Latch Pulse Width Fig.4 Serial Control Data Loading Diagram

Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage -0.3 to 7.0V Input voltage at any pin (ref V.. = OV) -0.3 to (Vp, + 0.3V) Sink/source current (supply pins) +/-30MA (other pins) +/- 20MA Total device dissipation @ Ty, 25°C 800mW Max. Derating 10mwirc Operating temperature range: FXO0SJ -30°C to +85°C (cerdip) FXOO9LG/LS -30°C to +70°C (plastic) Storage temperature range: FXO09J -55°C to +125°C (cerdip) FXOOSLG/LS -40°C to +85°C (plastic) Operating Limits All device characteristics are measured under the following conditions unless otherwise specified: Vp = 5-0V, Taye = 25°C. Audio Level 0dB ref: = 775mVrms. Amplifier Gain Set = OdB. Characteristics See Note Min. Typ. Max. Unit Static Values Supply Voltage (V,,) 45 5.0 5.5 Vv Supply Current — - All Stages Quiescent - 0.13 - mA — All Stages Operating - 2.6 - mA Dynamic Values Control Functions Input Logic '1' 3.5 - - Vv Input Logic '0" - - 15 v Digital Input Impedances 0.5 1.0 - MQ Amplifier Stages (General) Bandwidth (-3dB) 20.0 - - kHz Output Impedance - 0.8 3.0 kQ Total Harmonic Distortion 1 - 0.35 05 % Output Noise Level (per stage) 2 - 180.0 400.0 yuVrms Onset of Clipping 3 - 1.73 - Vrms Gain Variation 4 - - 0.41 dB Interstage Isolation - 60.0 - dB “Trimmer” Stages (Ch1 — Ch7) Gain -3.0 +3.0 dB Gain per Step (15 in No.) - 0.43 - dB Step Error - - 0.2 dB Input Impedance 100.0 - - kQ “Volume” Stage (Ch8) Gain -14.0 +14.0 dB Gain per Step (15 in No.) - 2.0 - dB Step Error - - 0.4 dB Input Impedance 50.0 - - kQ Timing (Figure 4) Serial Clock "High" Pulse Width (toy,,) 250 - - ns Serial Clock “Low” Pulse Width (toy,) 250 - - ns Data Set-up Time (tpg) 150 - - ns Data Hold Time (tow) 50 - - ns Load/Latch Set-up Time (t,) 250 - - ns Load/Latch Pulse Width (tiw) 150 - - ns Serial Data Clock Frequency - - 2.0 MHz Notes 1. Gain Set 0dB, Input Level 1kHz -3.0dB (549mVrms). 2. a.c short-circuit input, measured in a 30kHz bandwidth. 3. See Figure 3. 4. Over temperature and supply voltage range.

The FX009u, the cerdip package is shown in Figure 5. The FX009 is a CMOS LSI circuit which includes input The ‘LG’ version is shown in Figure 6, and the 'LS’ Protection. However precautions should be taken to version in Figure 7. To allow complete identification, prevent static discharges which may cause damage. the FX009 LG and LS packages have an indent spot adjacent to pin 1 and a chamfered comer between pins 3 and 4. t— ‘ Be eae 0381} rol ) + a ca ' ame i nt ‘ sr BS . ‘7S ts La \\ —. 5m al. 4u = tlle nore atanasininan. Aner ope is Loe DIMENSION MAX Min | ae ar ane! AY oat & Symmety --% ¢ 1025 100 HOTT At dentin ni , peti: @ & DIMENSION MAX. iN. Lie - A f os ow A ‘est 1308 se i 23 ™ € 1561 15.8 " ra 18.65 = D 28.04 788 wom L ~ oF F 3% } Trica q 13, os 6 430 4.10 . t on 016 J 18.20 Lad v 23 TYPICAL w oo . “ x i ae | (ll le. we oe kL a Fx009J 24-pin cerdip DIL Precis FXO09LG —_24-pin quad plastic (O] i ge encapsulated bent and Possess? cropped NOTE: Al dimensions in mm. FXOO9LS = 24-lead plastic leaded chip oo 03s ed carrier § 1g As peal e 965 264 ia 055 O47 § 11.0 635 ‘ 10.20 J 3.50 pra 3.25 k 022 o%8 CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry.