FSYA254D INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • 21A, 250V, rDS(ON) = 0.150Ω
  • Total Dose - Meets Pre-RAD Specifications to 100K RAD (Si)
  • Single Event - Safe Operating Area Curve for Single Event Effects - SEE Immunity for LET of 36MeV/mg/cm 2 with VDS up to 80% of Rated Breakdown and VGS of 10V Off-Bias
  • Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IDM
  • Photo Current - 15nA Per-RAD(Si)/s Typically
  • Neutron - Maintain Pre-RAD Specifications for 1E13 Neutrons/cm2 - Usable to 1E14 Neutrons/cm2 Symbol Packaging SMD-1Ordering Information RAD LEVEL SCREENING LEVEL PART NO./BRAND 10K Commercial FSYA254D1 10K TXV FSYA254D3 100K Commercial FSYA254R1 100K TXV FSYA254R3 100K Space FSYA254R4 D G S Data Sheet March 1999 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified FSYA254D, FSYA254R UNITS Continuous Drain Current Maximum Power Dissipation (Distance >0.063in (1.6mm) from Case, 10s (Max) 300 oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 1mA, VGS = 0V 250 - - V Gate Threshold Voltage V GS(TH) VGS = VDS , ID = 1mA TC = -55oC - - 5.0 V TC = 25oC 1.5 - 4.0 V TC = 125oC 0.5 - - V Zero Gate Voltage Drain Current I DSS VDS = 200V, VGS = 0V TC = 25oC- - 2 5 µA TC = 125oC - - 250 µA Gate to Source Leakage Current I GSS VGS =±20V T C = 25oC - - 100 nA TC = 125oC - - 200 nA Drain to Source On-State Voltage V DS(ON) VGS = 12V, ID = 21A - - 3.31 V On Resistance r DS(ON)12 ID = 14A, VGS = 12V TC = 25oC - 0.120 0.150 Ω TC = 125oC - - 0.276 Ω Turn-On Delay Time t d(ON) VDD = 125V, ID = 21A, R L = 6.0Ω , VGS = 12V, R GS = 2.35Ω - - 40 ns Rise Time t r - - 65 ns Turn-Off Delay Time t d(OFF) - - 80 ns Fall Time t f - - 15 ns Total Gate Charge Q g(TOT) VGS = 0V to 20V V DD = 125V, ID = 21A - - 260 nC Gate Charge at 12V Q g(12) VGS = 0V to 12V - 130 150 nC Threshold Gate Charge Q g(TH) VGS = 0V to 2V - - 10 nC Gate Charge Source Q gs -2 7 3 6 n C Gate Charge Drain Q gd -5 8 7 6 n C Plateau Voltage V (PLATEAU) ID = 21A, VDS = 15V - 8 - V Input Capacitance C ISS VDS = 25V, VGS = 0V, f = 1MHz - 3000 - pF Output Capacitance C OSS - 550 - pF Reverse Transfer Capacitance C RSS - 150 - pF Thermal Resistance Junction to Case R θJC - - 0.83 oC/W FSYA254D, FSYA254R

  1. Insitu Gamma bias must be sampled for both V
  2. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.
  3. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).

FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT

Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table). Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent)TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Gate to Source Leakage Current I GSS VGS =±20V ±20 (Note 7) nA Zero Gate Voltage Drain Current I DSS VDS = 80% Rated Value ±25 (Note 7) µA On Resistance r DS(ON) TC = 25oC at Rated ID ±20% (Note 8) Ω Gate Threshold Voltage V GS(TH) ID = 1.0mA ±20% (Note 8) V NOTES: 7. Or 100% of Initial Reading (whichever is greater). 8. Of Initial Reading. Screening Information TEST JANTXV EQUIVALENT JANS EQUIVALENT Gate Stress V GS = 30V, t = 250µsV GS = 30V, t = 250µs Pind Optional Required Pre Burn-In Tests (Note 9) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25 oC) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) Steady State Gate Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests and Limits Table All Delta Parameters Listed in the Delta Tests and Limits Table Steady State Reverse Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 160 hours MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours PDA 10% 5% Final Electrical Tests (Note 9) MIL-S-19500, Group A, Subgroup 2 MIL-S-19500, Group A, Subgroups 2 and 3 NOTE: 9. Test limits are identical pre and post burn-in. Additional Screening Tests PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Safe Operating Area SOA V DS = 200V, t = 10ms 1.77 A Unclamped Inductive Switching I AS VGS(PEAK) = 15V, L = 0.1mH 63 A Thermal Response ΔVSD tH = 10ms; VH = 25V; IH = 4A 70 mV Thermal Impedance ΔVSD tH = 500ms; VH = 20V; IH = 4A, HEAT SINK REQUIRED 159 mV FSYA254D, FSYA254R

Rad Hard Data Packages - Intersil Power Transistors TXV Equivalent 1. RAD HARD TXV EQUIVALENT - STANDARD DATA PACKAGE A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet D. Group A - Attributes Data Sheet E. Group B - Attributes Data Sheet F. Group C - Attributes Data Sheet G. Group D - Attributes Data Sheet 2. RAD HARD TXV EQUIVALENT - OPTIONAL DATA PACKAGE A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet - Precondition Lot Traveler - Pre and Post Burn-In Read and Record Data D. Group A - Attributes Data Sheet - Group A Lot Traveler E. Group B - Attributes Data Sheet - Group B Lot Traveler - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup B3) - Bond Strength Data (Subgroup B3) - Pre and Post High Temperature Operating Life Read and Record Data (Subgroup B6) F. Group C - Attributes Data Sheet - Group C Lot Traveler - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup C6) - Bond Strength Data (Subgroup C6) G. Group D - Attributes Data Sheet - Group D Lot Traveler - Pre and Post RAD Read and Record Data Class S - Equivalents 1. RAD HARD “S” EQUIVALENT - STANDARD DATA PACKAGE A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data F. Group A - Attributes Data Sheet G. Group B - Attributes Data Sheet H. Group C - Attributes Data Sheet I. Group D - Attributes Data Sheet 2. RAD HARD MAX. “S” EQUIVALENT - OPTIONAL DATA PACKAGE A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - X-Ray and X-Ray Report F. Group A - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups A2, A3, A4, A5 and A7 Data G. Group B - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups B1, B3, B4, B5 and B6 Data H. Group C - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups C1, C2, C3 and C6 Data I. Group D - Attributes Data Sheet - Hi-Rel Lot Traveler - Pre and Post Radiation Data FSYA254D, FSYA254R

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitewww.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 FSYA254D, FSYA254R SMD-1

3 PAD CERAMIC LEADLESS CHIP CARRIER

E D A D 1 b D 2 1 - GATE 2 - SOURCE 3 - DRAIN SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX A 0.129 0.139 3.27 3.53 - b 0.135 0.145 3.43 3.68 - D 0.445 0.455 11.30 11.55 - D 1 0.370 0.380 9.39 9.65 - D 2 0.100 0.110 2.54 2.79 - E 0.620 0.630 15.74 16.00 - E1 0.410 0.420 10.41 10.66 - E2 0.152 0.162 3.86 4.11 - NOTES: 1. No current JEDEC outline for this package. 2. Controlling dimension: INCH. 3. Revision 2 dated 6-98.