FSSD07UMX

FSSD07 ONSEMI | Alldatasheet

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© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSSD07 Rev. 1.0.2 FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer FSSD07 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer

Features

 On Resistance: 5Ω Typical, VDDC=2.7V  ftoggle: >75MHz  Low On Capacitance: 6pF Typical  Low Power Consumption: 2µA Maximum  Supports Secure Digital (SD), Secure Digital I/O (SDIO), and Multimedia Card (MMC) Specifications  Supports 1-Bit / 4-Bit Host Controllers (VDDH1/H2=1.65V to 3.6V) Communicating with High-Voltage (2.7-3.6V) and Dual-Voltage Cards - VDDC=1.65 to 3.6V, VDDH1/H2=1.65 to 3.6V  24-Lead MLP and UMLP Packages

Applications

 Cell Phone, PDA, Digital Camera, Portable GPS, and Notebook Computer  LCD Monitor, TV, and Set-Top Box Related Resources  FSSD07 Evaluation Board  Evaluation Board Users Guide  For samples, questions, or board requests; please contact analogswitch@fairchildsemi.com

Description

The FSSD07 is a 2:1 multiplexer that allows dual Secure Digital (SD), Secure Digital I/O (SDIO), and Multimedia Card (MMC) host controllers to share a common peripheral. The host controllers can be equal to, greater than, or less than peripheral card supply with minimal power consumption. This configuration enables dual host CMD, CLK, and D[3:0] si gnals to be multiplexed to a common peripheral. The architecture includes the necessary bi-directional data and command transfer capability for single high- voltage cards or dual-voltage supply cards. The clock path is a uni-directional buffer. Typical applications involve switching in portables and consumer applications: cell phones, digital cameras, home theater monitors, set-top boxes, and notebooks. Figure 1. Analog Symbol Diagram

Ordering Information

Temperature Range Package Description Packing Method FSSD07BQX FSSD07 -40°C to +85°C 24-Lead Molded Leadless Package (MLP), JEDEC MO-220, 3.5 x 4.5mm Tape & Reel FSSD07UMX JK -40°C to +85°C 24-Lead Ultra-thin Molded Leadless Package (UMLP), 0.4mm pitch Tape & Reel

Figure 2. MLP Pin Assignments Figure 3. UMLP Pin Assignments

Figure 4. Typical Application Diagram

© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSSD07 Rev. 1.0.2 4 FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer Functional Description The FSSD07 enables the multiplexing of dual ASIC / baseband processor hosts to a common peripheral card or module, providing bi-dir ectional support of the dual- voltage SD/SDIO or MMC cards available in the marketplace. Each host SDIO port has its own supply rail, such that hosts with different supplies can be interfaced to a common peripheral module or card. The peripheral card supply must be equal to or greater than the host(s) to minimize power consumption. The independent VDDC, VDDH1, and V DDH2 are defined by the supplies connected from the application Power Management ICs (PMICs) to the FSSD07. The clock path is a uni-directional buffe red path rather than a bi- directional switch port. The supplies (V DDC, V DDH1, and VDDH2) have an internal termination resistor (typically 3M) to ensure the supply rails internally do not float if the application turns off one or all of these sources. CMD, DAT Bus Pull-ups The CMD and DAT[3:0] ports do not have, internally, the system pull-up resistors as defined in the MMC or SD card system bus specificat ions. The system bus pull-up must be added external to the FSSD07. The value, within the specific specification limits, is a function of the individual application and type of card or peripheral connected. For SD card applications, the RCMD and RDAT pull-ups should be between 10k Ω and 100kΩ. For MMC applications, the R CMD pull-ups should be between 4.7kΩ and 100k Ω, and the R DAT pull-ups between 50kΩ and 100k Ω. The card-side CMD and DAT[3:0] outputs have a circuit that facilitates incident wave switching, so the external pull-up resistor s ensure retention of the output high level. The OE pin can be used to place the CMD and DAT[3:0] into high-impedance mode during power-up sequencing or when the system enters IDLE state ( see IDLE State CMD/DAT Bus “Parking”). CLK Bus The 1CLK and 2CLK inputs are bi-state buffer architectures, rather than a switch I/O, to ensure 52MHz incident wave switching. Si nce most host controllers also have a clock enable register bit to enable or disable the system clock when in ID LE mode, the CLK output is not disabled by the OE pin. Instead, the CLK output is a function of whichever host controller clock is selected by the S pin. Consequently, there is alwa ys a clock path connected between the selected host and the card. The state of the CLK pin is a function of the selected host controller nCLK output pin, which fac ilitates retaining clock duty cycle in the system or performing read / wait operations. IDLE State & Power-Up CMD/DAT Bus “Parking” The SD and MMC card specifications were written for a direct point-to-point communication between host controller and card. The introduction of the FSSD07 in that path, as an expander, r equires that the functional operation and system latenc y not be impacted by the switch characteristics. Si nce there are various card formats, protocols, and conf igurable controllers, an OE pin is available to facilitate a fast IDLE transition for the CMD/DAT[3:0] outputs. Some controllers, rather than placing CMD/DAT into hi gh-impedance mode, pull the outputs HIGH for a clock cycle prior to going into high- impedance mode (referred to as “parking” the output). Some legacy controllers pull their outputs HIGH versus high impedance. If the OE pin is pulled HIGH and the controller places its command and data outputs into high-impedance (driving nCMD/nDAT[3:0]), the F SSD07 CMD/DAT[3:0] output rise time is a function of the RC time constant through the switch path. Pulling OE LOW puts the switches into high impedance, disabling communication from the host to card, and the CMD/DAT[3: 0] outputs are pulled HIGH by the system pull-up re sistors chosen for the application. This mechani sm facilitates power-up sequencing by holding OE LOW until supplies are stable and communication between the host(s) and card is enabled. Power Optimization Since the FSSD07 has multiple supplies (V DDC, V DDH1, and VDDH2), the control signals have been referenced to the card peripheral side (V DDC). To minimize power consumption, current pat hs between supplies are isolated when one or more supplies are not present. This includes the configurat ion of the removal of V DDC with host controller supplies remaining present.

© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSSD07 Rev. 1.0.2 5 FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Conditions Min. Max. Unit VDDC Card Supply Voltage -0.5 4.6 V VDDH1,VDDH2 Host Controller Supply Voltage -0.5 4.6 V VSW Switch I/O Voltage (1) 1DAT[3:0], 2DAT[3:0], 1CMD, 2CMD Pins -0.5 VDDx (2)+ 0.3V (4.6V maximum) V DAT[3:0], CMD Pins -0.5 VDDx (2)+ 0.3V (4.6V maximum) V VCNTRL Control Input Voltage (1) S, OE -0.5 4.6 V VCLKI CLK Input Voltage (1) 1CLK, 2CLK -0.5 4.6 V VCLKO CLK Output Voltage (1) CLK -0.5 VDDx (2)+ 0.3V (4.6V maximum) V IINDC Input Clamp Diode Current -50 mA ISW Switch I/O Current SDIO Continuous 50 mA ISWPEAK Peak Switch Current SDIO Pulsed at 1ms Duration, <10% Duty Cycle 100 mA TSTG Storage Temperature Range -65 +150 C TJ Maximum Junction Temperature +150 C TL Lead Temperature Soldering, 10 Seconds +260 C ESD Human Body Model, JEDEC: JESD22-A114 I/O to GND 8 kV Supply to GND 10 All Other Pins 5 Charged Device Model, JEDEC-JESD-C101 2 Notes: 1. The input and output negativ e ratings may be exceeded if the input and output diode current ratings are observed. 2. V DDx references the specific SDIO port VDD rail (i.e. VDDH1, VDDH2, VDDC). Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device oper ation. Recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VDDC Supply Voltage - Card Side 1.65 3.60 V VDDH1, VDDH2 Supply Voltage - Dual Host Controller 1.65 3.60 V VCNTRL Control Input Voltage - V S, VOE 0 VDDC V VCLKI Clock Input Voltage - V CLKI 0 VDDH1/H2 V VSW Switch I/O Voltage CMD, DAT[3:0] 0 V DDC V 1CMD, 1DAT[3:0] 0 V DDH1 V 2CMD, 2DAT[3:0] 0 V DDH2 V TA Operating Temperature -40 +85 °C JA Thermal Resistance, Free Air MLP Package +50 °C/W

© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSSD07 Rev. 1.0.2 6 FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer All typical values are for VDDC=1.8V at 25°C unless otherwise specified. Symbol Parameter VDDC (V) VDDH1 / VDDH2 (V) Conditions TA=-40 to +85°C Unit Min. Typ. Max. Common Pins VIK Clamp Diode Voltage 1.80 1.80 I IK=-18mA -1.2 V VIH Control Input Voltage High 1.80 1.80 1.3 V VIL Control Input Voltage Low 1.80 1.80 0.5 V IIN S, OE Input High Current 1.95 1.95 V CNTRL=0V to VDDC -1 1 µA IOZ Off Leakage, Current of VOHC CLK Output Voltage High(3) 1.95 1.95 I OH=-2mA 1.6 V VOLC CLK Output Voltage Low(3) 1.65 1.65 I OL=-2mA 90 mV RON Switch On Resistance (4) 1.65 1.65 VCMD, DAT[3:0]=0V, ION=-2mA Figure 5 10 Ω ∆RON Delta On Resistance (3, 5) 1.65 1.65 VCMD, DAT[3:0]=0V, ION=- 2mA 0.85 Ω Power Supply ICC(VDDC) Quiescent Supply Current (Card) 1.95 0 V SW=0 or VDDC, IOUT=0 2 µA ICC(VDDH1/H2) Quiescent Supply Current (Hosts) 1.95 1.95 VSW=0 or VDDx, IOUT=0, VCLKI=VDDHX, VCLKO=Open, OE=VDDC 2 µA ∆IHOST Delta ICC(VDDH1, VDDH2) for One Host Powered Off 1.95 1.95 / 0 0 / 1.95 VSW=0 or VDDx, IOUT=0, VCLKI=VDDHX, VCLKO=Open, OE=VDDC 2 µA Notes: 3. Guaranteed by characteriza tion, not production tested. 4. On resistance is determined by the voltage drop between the switch I/O pins at the indicated current through the switch. 5. ∆ RON=RON max – RON min measured at identical VCC, temperature, and voltage.

© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSSD07 Rev. 1.0.2 7 FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer All typical values are for VDDC=2.7V at 25°C unless otherwise specified. Symbol Parameter V DDC (V) VDDH1 / VDDH2 (V) Conditions TA=-40 to +85°C Unit Min. Typ. Max. Common Pins VIK Clamp Diode Voltage 2.7 2.7 I IK=-18mA -1.2 V VIH Control Input Voltage High 2.7 2.7 1.8 VIL Control Input Voltage Low 2.7 2.7 0.8 IIN S, OE Input High Current 3.6 3.6 V CNTRL=0V to VDDC -1 1 µA IOZ Off Leakage Current of VOHC CLK Output Voltage High(6) 2.7 2.7 I OH=-2mA 2.4 V VOLC CLK Output Voltage Low(6) 3.6 3.6 I OL=-2mA 90 mV RON Switch On Resistance (7) 2.7 2.7 VCMD, DAT[3:0]=0V, ION=-2mA Figure 5 5.0 8.0 Ω ∆RON Delta On Resistance (6, 8) 2.7 2.7 VCMD, DAT[3:0]=0V, ION=- 2mA 0.8 Ω Power Supply ICC(VDDC) Quiescent Supply Current (Card) 3.6 0 V SW=0 or VDDC, IOUT=0 2 µA ICC (VDDH1/C2) Quiescent Supply Current (Hosts) 3.6 3.6 VSW=0 or VDDx, IOUT=0, VCLKI=VDDHX, VCLKO=Open, OE=VDDC 2 µA ∆IHOST Delta ICC(VDDH1, VDDH2) for One Card Powered Off 3.6 3.6 / 0 0 / 3.6 VSW=0 or VDDx, IOUT=0, VCLKI=VDDHX, VCLKO=Open, OE=VDDC 2 µA Notes: 6. Guaranteed by characteriza tion, not production tested. 7. On resistance is determined by the voltage drop between the switch I/O pins at the indicated current through the switch. 8. ∆ RON=RON max – RON min measured at identical VCC, temperature, and voltage.

2.225 3.700 0.400 0.225 0.663 2.225 2.800 0.563 0.50±0.05 0.025±0.025 SEATING PLANE C 3.40±0.10 2.50±0.10 PIN#1 IDENT A B (0.15) 4X 0.40 0.40±0.05 (23X) 0.05 PIN#1 IDENT DETAIL A 0.50±0.05 45° 0.20±0.05 0.50±0.05 0.10±0.05 0.025±0.025 SEATING PLANE C TOP VIEW BOTTOM VIEW SIDE VIEW - OPTION A LAND PATTERN RECOMMENDATION NOTES: A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC STANDARD B. ALL DIMENSIONS ARE IN MILLIMETERS C. LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN D. DRAWING FILENAME: MKT-UMLP24ArevE POTENTIAL PULL BACK SIDE VIEW - OPTION B DETAIL A SCALE 2:1 7 12 1924 7 12

0.10 C A B

0.05 C

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