FSSD06BQX

FSSD06 ONSEMI | Alldatasheet

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© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSSD06 • Rev. 1.0.5 FSSD06 — SD/SDIO and MMC Two-Port Multiplexer FSSD06 — SD/SDIO and MMC Two-Port Multiplexer

Features

 On Resistance Typically 4Ω, VDDH=2.7V  ftoggle: > 120MHz  Low On Capacitance: 9pF Typical  Low Power Consumption: 1µA Maximum  Conforms to Secure Digital (SD), Secure Digital I/O (SDIO), and Multimedia Card (MMC) Specifications  Supports 1-Bit / 4-Bit Host Controllers (VDDH=1.65V to 3.6V) Communicating with High-Voltage (2.7-3.6V) and Dual-Voltage Cards (1.65-1.95V, 2.7-3.6V) - VDDH=1.65 to 3.6V, VDDC1/C2=VDDH to 3.6V  24-Lead MLP (3.5 x 4.5mm) and UMLP Packages

Applications

 Cell Phone, PDA, Digital Camera, Portable GPS  LCD Monitor, Home Theater PC/TV, All-in-One Printer

Description

The FSSD06 is a two-port multiplexer that allows Secure Digital (SD), Secure Digital I/O (SDIO), and Multimedia Card (MMC) host controllers to be expanded out to multiple cards or peripherals. This configuration enables the CMD, CLK, and D[3:0] signals to be multiplexed to dual-card peripherals. It is optimized for 1-bit / 4-bit SD / MMC applications. The architecture includes the necessary bi-directional data and command transfer capability for single high- voltage cards or dual-voltage supply cards. The clock path for the FSSD06 is a uni-directional buffer with an integrated pull-up for high-impedance mode. Typical applications involve switching in portables and consumer applications: cell phones, digital cameras, home theater monitors, portable GPS units, and printers. Analog Symbol Diagram GND 1CLK 2CLK DAT[0:3], CMD CLK Control /OE S VDDC1 RPU 1DAT[0:3], 1CMD 2DAT[0:3], 2CMD VDD C2 RPU VDDC1 VDDC2 VDDH Figure 1. Analog Symbol Diagram

Ordering Information

Temperature Range Package Description Packing Method FSSD06BQX -40°C to +85°C 24-Lead Molded Leadless Package (MLP), JEDEC MO- 220, 3.5 x 4.5mm Tape & Reel FSSD06UMX -40°C to +85°C 24-Lead Ultrathin Molded Leadless Package (UMLP) Tape & Reel

Figure 2. MLP Pin Assignments Figure 3. UMLP Pin Assignments

allowed to float in the application. Figure 4. Typical Application Diagram SD/SDIO or MMC cards available in the marketplace. path rather than a bi-directional switch port. retention of the output high level. outputs HIGH versus high impedance. DAT[3:0] HIGH for one cycle before pulling /OE HIGH. HIGH before putting the switch I/Os in high impedance.

© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSSD06 • Rev. 1.0.5 4 FSSD06 — SD/SDIO and MMC Two-Port Multiplexer Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Conditions Min. Max. Unit VDDH Supply Voltage -0.5 4.6 V VDDC1,VDDC2 Supply Voltage -0.5 4.6 V VSW (1) Switch I/O Voltage 1DAT[3:0], 2DAT[3:0], 1CMD, 2CMD Pins -0.5 VDDx (2)+ 0.3V (4.6V maximum) V DAT[3:0], CMD Pins -0.5 VDDx (2)+ 0.3V (4.6V maximum) V VCNTRL (1) Control Input Voltage S, /OE -0.5 4.6 V VCLKI (1) CLK Input Voltage CLK -0.5 4.6 V VCLKO (1) CLK Output Voltage 1CLK, 2CLK -0.5 VDDx (2)+ 0.3V (4.6V maximum) V IINDC Input Clamp Diode Current -50 mA ISW Switch I/O Current SDIO Continuous 50 mA ISWPEAK Peak Switch Current SDIO Pulsed at 1ms Duration, <10% Duty Cycle 100 mA TSTG Storage Temperature Range -65 +150 C TJ Max Junction Temperature +150 C TL Lead Temperature Solderi ng, 10 Seconds +260C C ESD Human Body Model (JEDEC: JESD22-A114) I/O to GND 8 kV Supply to GND 9 All Other Pins 5 Charged Device Model (JEDEC: JESD22-C101) 2 kV Notes: 1. The input and output negativ e ratings may be exceeded if the input and output diode current ratings are observed. 2. V DDx references the specific SDIO port VDD rail (i.e. VDDC1, VDDC2, VDDH). Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device oper ation. Recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Minimum Maximum Unit VDDH Supply Voltage - Host Side 1.65 3.6V V VDDC1, VDDC2 Supply Voltage - SDIO Cards V DDH 3.6V V VCNTRL Control Input Voltage - V S,V/OE 0 VDDH V VCLKI Clock Input Voltage - V CLKI 0 VDDH V VSW Switch I/O Voltage - CMD, DAT[3:0] 0 V DDH V Switch I/O Voltage - 1CMD, 1DAT[3:0] 0 V DDC1 V Switch I/O Voltage - 2CMD, 2DAT[3:0] 0 V DDC2 V °C Operating Temperature -40 +85 °C JA Thermal Resistance (free air), MLP24 50 °C/W

© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSSD06 • Rev. 1.0.5 5 FSSD06 — SD/SDIO and MMC Two-Port Multiplexer All typical values are for VDDH=1.8V at 25°C unless otherwise specified. Symbol Parameter VDDC1 / VDDC2 (V) Conditions TA=- 40°C to +85°C Unit Min. Typ. Max. Common Pins VIK Clamp Diode Voltage 2.7 I IK=-18mA -1.2 V VIH Control Input Voltage High 2.7 VDDH=1.65V 1.3 VIL Control Input Volt age Low 2.7 0.5 IIN S, /OE Input High Current 3.6 VDDH=1.95V, VCNTRL=0V to VDDH -1 1 µA IOZ Off Leakage, Current of IPU CLK Pull-up Current 3.6 VCLKI=VDDH VCLKO=0V, /OE=VDDH 35 µA VOHC CLK Output Voltage High 2.7 I OH=-2mA 2.4 V VOLC CLK Output Voltage Low 3.6 I OL=-2mA 90 mV RPU CLK Pull-up Resistance (3) 50 100 k Ω RON Switch On Resistance (4) 2.7 VCMD, DAT[3:0]=0V, ION=-2mA, See Figure 5 4 6 Ω ∆RON Delta On Resistance (4, 5) 2.7 V CMD, DAT[3:0]=0V, ION=- 2mA 0.8 Ω Power Supply ICC(VDDH) Quiescent Supply Current (Host) 0 VDDH=1.95V, VSW=0 or VDDH, IOUT=0 1 µA ICC(VDDC1, VDDC2) Quiescent Supply Current (SDIO Cards) 3.6 VSW=0 or VDDx, IOUT=0, VCLKI=VDDH, VCLKO=Open, /OE=0V 1 µA ∆ICARD Delta ICC(VDDC1, VDDC2) for One Card Powered Off 3.6V / 0V VSW=0 or VDDx, IOUT=0, VCLKI=VDDH, VCLKO=Open, /OE=0V 1 µA Notes: 3. Guaranteed by characteriza tion, not production tested. 4. On resistance is determined by the voltage drop between the switch I/O pins at the indicated current through the switch. 5. ∆ RON=RON max – RON min measured at identical VCC, temperature, and voltage.

© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSSD06 • Rev. 1.0.5 6 FSSD06 — SD/SDIO and MMC Two-Port Multiplexer All typical values are for VDDH=2.7V at 25°C unless otherwise specified. Symbol Parameter VDDC1 / VDDC2 (V) Conditions TA=- 40°C to +85°C Unit Min. Typ. Max. Common Pins VIK Clamp Diode Voltage 2.7 I IK=-18mA -1.2 V VIH Control Input Voltage High 2.7 VDDH=2.7V 1.8 VIL Control Input Volt age Low 2.7 0.8 IIN S, /OE Input High Current 3.6 VDDH=3.6V, VCNTRL=0V to VDDH -1 1 µA IOZ Off Leakage Current of all IPU CLK Pull-up Current 3.6 VCLKI=VDDH, VCLKO=0V, /OE=VDDH 50 µA VOHC CLK Output Voltage High 2.7 I OH=-2mA 2.4 V VOLC CLK Output Voltage Low 3.6 I OL=-2mA 90 mV RPU CLK Pull-up Resistance (6) 50 100 k Ω RON Switch On Resistance (7) 2.7 VCMD, DAT[3:0]=0V, ION=-2mA See Figure 5 2.5 6.0 Ω ∆RON Delta On Resistance (7,8) 2.7 V CMD, DAT[3:0]=0V, ION=- 2mA 0.8 Ω Power Supply ICC(VDDH) Quiescent Supply Current (Host) 0 VDDH=3.6V, VSW=0 or VDDH, IOUT=0 1 µA ICC(VDDC1, VDDC2) Quiescent Supply Current (SDIO Cards) 3.6 VSW=0 or VDDx, IOUT=0, VCLKI=VDDH , VCLKO=Open, /OE=0V 1 µA ∆ICARD Delta ICC(VDDC1, VDDC2) for One Card Powered Off 3.6V/0V 0V/3.6V VSW=0 or VDDx, IOUT=0, VCLKI=VDDH, VCLKO=Open, /OE=0V 1 µA Notes: 6. Guaranteed by characteriza tion, not production tested. 7. On resistance is determined by the voltage drop between the switch I/O pins at the indicated current through the switch. 8. ∆RON=RON max – RON min measured at identical VCC, temperature, and voltage.

© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSSD06 • Rev. 1.0.5 7 FSSD06 — SD/SDIO and MMC Two-Port Multiplexer All typical values are for VDDH=1.8V at 25°C unless otherwise specified. Symbol Parameter VDDC1 / VDDC2 (V) Conditions TA=- 40°C to +85°C Unit Min. Typ. Max. tON1 Turn-On Time, S, /OE to CMD, DAT[3:0] 2.7 to 3.6 VSW=0V, RL=1kΩ, CL=30pF See Figure 7, Figure 8 10 24 ns tOFF1 Turn-Off Time, S, /OE to CMD, DAT[3:0] 2.7 to 3.6 VSW=0V, RL=1kΩ, CL=30pF See Figure 7, Figure 8 7 22 ns tPD Switch Propagation Delay(9) 2.7 to 3.6 See Figure 9 1 ns tSKEW Switch Skew(9, 10) CMD, DAT[3:0] 2.7 to 3.6 R L=1kΩ, CL=30pF 2 ns tON2 Turn-On Time, S, /OE to 1CLK, 2CLK 2.7 to 3.6 VSW=0V, RL=1kΩ, CL=30pF See Figure 7, Figure 8 17 35 ns tOFF2 Turn-Off Time S, /OE to 1CLK, 2CLK 2.7 to 3.6 VSW=0V, RL=1kΩ, CL=30pF See Figure 7, Figure 8 10 28 ns tPDCLK Clock Propagation Delay 2.7 to 3.6 RL=1kΩ, CL=30pF See Figure 11 3.0 5.5 ns OIRR Off Isolation (9) 2.7 to 3.6 f=10MHz, RT=50Ω, CL=30pF, See Figure 12 -60 dB Xtalk Non-Adjacent Channel Crosstalk(9) 2.7 to 3.6 f=10MHz, RT=50Ω, CL=30pF, See Figure 13 -60 dB ftoggle Clock Frequency (9) 2.7 to 3.6 C L=30pF 120 MHz Notes: 9. Guaranteed by characteriza tion, not production tested. 10. Skew is determined by |T PLH - TPHL | for worst-case temperature and VDDX.

© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSSD06 • Rev. 1.0.5 8 FSSD06 — SD/SDIO and MMC Two-Port Multiplexer All typical values are for VDDH=2.7V at 25°C unless otherwise specified. Symbol Parameter VDDC1 / VDDC2 (V) Conditions TA=- 40°C to +85°C Unit Min. Typ. Max. tON1 Turn-On Time S, /OE to CMD, DAT[3:0] 2.7 to 3.6 VSW=0V, RL=1kΩ, CL=30pF See Figure 7, Figure 8 8 17 ns tOFF1 Turn-Off Time S, /OE to CMD, DAT[3:0] 2.7 to 3.6 VSW=0V, RL=1kΩ, CL=30pF See Figure 7, Figure 8 6 13 ns tPD Switch Propagation Delay(11) 2.7 to 3.6 See Figure 9 1 ns tSKEW Switch Skew(12) CMD, DAT[3:0] 2.7 to 3.6 R L=1kΩ, CL=30pF 1.5 ns tON2 Turn-On Time S, /OE to 1CLK, 2CLK 2.7 to 3.6 VSW=0V, RL=1kΩ, CL=30pF See Figure 7, Figure 8 15 25 ns tOFF2 Turn-Off Time S, /OE to 1CLK, 2CLK 2.7 to 3.6 VSW=0V, RL=1kΩ, CL=30pF See Figure 7, Figure 8 10 25 ns tPDCLK Clock Propagation Delay 2.7 to 3.6 RL=1kΩ, CL=30pF See Figure 11 1.5 3.0 ns OIRR Off Isolation (11) 2.7 to 3.6 f=10MHz, RT=50Ω, CL=30pF See Figure 12 -60 dB Xtalk Non-Adjacent Channel Crosstalk(11) 2.7 to 3.6 f=10MHz, RT=50Ω, CL=30pF See Figure 13 -60 dB ftoggle Clock Frequency (11) 2.7 to 3.6 C L=30pF 120 MHz Notes: 11. Guaranteed by characteriza tion, not production tested. 12. Skew is determined by |T PLH - TPHL | for worst-case temperature and VDDX. Capacitance Symbol Parameter Conditions TA=- 40°C to +85°C Unit Min. Typ. Max. CIN (S, /OE, CLK) Control and CLK Pin Input Capacitance VDDH=0V 2.5 pF CON Common Port On Capacitance (CDAT[3:0], CMD) VDDH=1.8V,VDDC1=VDDC2=2.7V, V/OE=0V, Vbias=0V, f=1MHz See Figure 15 9.0 COFF Input Source Off Capacitance VDDH=1.8V,VDDC1=VDDLH2=2.7V, V/OE=3.3V, Vbias=0V, f=1MHz See Figure 14 4.0

© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSSD06 • Rev. 1.0.5 11 FSSD06 — SD/SDIO and MMC Two-Port Multiplexer Tape and Reel Specifications Package Designator Tape Selection Number Cavities Cavity Status Cover Tape Status MPX Leader (Start End) 125 (Typical) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed Tape Dimensions Dimensions are in millimeters unless otherwise noted. Reel Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Tape Size A B C D N W1 W2

2.225 3.700 0.400 0.225 0.663 2.225 2.800 0.563 0.50±0.05 0.025±0.025 SEATING PLANE C 3.40±0.10 2.50±0.10 PIN#1 IDENT A B (0.15) 4X 0.40 0.40±0.05 (23X) 0.05 PIN#1 IDENT DETAIL A 0.50±0.05 45° 0.20±0.05 0.50±0.05 0.10±0.05 0.025±0.025 SEATING PLANE C TOP VIEW BOTTOM VIEW SIDE VIEW - OPTION A LAND PATTERN RECOMMENDATION NOTES: A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC STANDARD B. ALL DIMENSIONS ARE IN MILLIMETERS C. LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN D. DRAWING FILENAME: MKT-UMLP24ArevE POTENTIAL PULL BACK SIDE VIEW - OPTION B DETAIL A SCALE 2:1 7 12 1924 7 12

0.10 C A B

0.05 C

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