FSPYE234R INTERSIL | Alldatasheet

Document overview

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  • PDF pages: 8

Technical content

Features

  • 9A, 250V, rDS(ON) = 0.215Ω
  • UIS Rated
  • Total Dose - Meets Pre-RAD Specifications to 100K RAD (Si) - Rated to 300K RAD (Si)
  • Single Event - Safe Operating Area Curve for Single Event Effects - SEE Immunity for LET of 36MeV/mg/cm 2 with VDS up to 100% of Rated Breakdown and VGS of 10V Off-Bias
  • Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IAS
  • Photo Current - 4.0nA Per-RAD (Si)/s Typically
  • Neutron - Maintain Pre-RAD Specifications for 1E13 Neutrons/cm2 - Usable to 1E14 Neutrons/cm2 Symbol Packaging SMD.5

Ordering Information

RAD LEVEL SCREENING LEVEL PART NUMBER/BRAND 10K Engineering samples FSPYE234D1 100K TXV FSPYE234R3 100K Space FSPYE234R4 300K TXV FSPYE234F3 300K Space FSPYE234F4 D G S Data Sheet June 2000

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified FSPYE234R, FSPYE234F UNITS Continuous Drain Current Maximum Power Dissipation (Distance >0.063in (1.6mm) from Case, 10s Max) 300 oC Weight (Typical) 1.0 (Typical) g CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications T C = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 1mA, VGS = 0V 250 - - V Gate Threshold Voltage V GS(TH) VGS = VDS , ID = 1mA TC = -55oC - - 5.5 V TC = 25oC 2.0 - 4.5 V TC = 125oC 1.0 - - V Zero Gate Voltage Drain Current I DSS VDS = 200V, VGS = 0V TC = 25oC- - 2 5 µA TC = 125oC - - 250 µA Gate to Source Leakage Current I GSS VGS =±30V T C = 25oC - - 100 nA TC = 125oC - - 200 nA Drain to Source On-State Voltage V DS(ON) VGS = 12V, ID = 9A - - 1.98 V Drain to Source On Resistance r DS(ON)12 ID = 6A, VGS = 12V TC = 25oC - 0.185 0.215 Ω TC = 125oC - - 0.413 Ω Turn-On Delay Time t d(ON) VDD = 125V, ID = 9A, R L = 13.9Ω , VGS = 12V, R GS = 7.5Ω - - 20 ns Rise Time t r - - 25 ns Turn-Off Delay Time t d(OFF) - - 30 ns Fall Time t f - - 15 ns Total Gate Charge Q g(12) VGS = 0V to 12V V DD = 125V, ID = 9A -3 0 3 3 n C Gate Charge Source Q gs -1 0 1 2 n C Gate Charge Drain Q gd - 8 10 nC Gate Charge at 20V Q g(20) VGS = 0V to 20V - 45 - nC Threshold Gate Charge Q g(TH) VGS = 0V to 2V - 3 - nC Plateau Voltage V (PLATEAU) ID = 9A, VDS = 15V - 6.5 - V Input Capacitance C ISS VDS = 25V, VGS = 0V, f = 1MHz - 1400 - pF Output Capacitance C OSS - 200 - pF Reverse Transfer Capacitance C RSS -8- p F Thermal Resistance Junction to Case R θJC - - 3.0 oC/W FSPYE234R, FSPYE234F

  1. Insitu Gamma bias must be sampled for both V
  2. Testing conducted at Brookhaven National Labs.
  3. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).

FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA FIGURE 2. TYPICAL SEE SIGNATURE CURVE

Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table). FIGURE 13. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 14. RESISTIVE SWITCHING WAVEFORMS

  1. Or 100% of Initial Reading (whichever is greater).
  2. Test limits are identical pre and post burn-in.

Rad Hard Data Packages - Intersil Power Transistors TXV Equivalent 1. RAD HARD TXV EQUIVALENT - STANDARD DATA PACKAGE A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet D. Group A - Attributes Data Sheet E. Group B - Attributes Data Sheet F. Group C - Attributes Data Sheet G. Group D - Attributes Data Sheet 2. RAD HARD TXV EQUIVALENT - OPTIONAL DATA PACKAGE A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet - Pre and Post Burn-In Read and Record Data D. Group A - Attributes Data Sheet E. Group B - Attributes Data Sheet - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup B3) - Bond Strength Data (Subgroup B3) - Pre and Post High Temperature Operating Life Read and Record Data (Subgroup B6) F. Group C - Attributes Data Sheet - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup C6) - Bond Strength Data (Subgroup C6) G. Group D - Attributes Data Sheet - Pre and Post RAD Read and Record Data Class S - Equivalents 1. RAD HARD “S” EQUIVALENT - STANDARD DATA PACKAGE A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data F. Group A - Attributes Data Sheet G. Group B - Attributes Data Sheet H. Group C - Attributes Data Sheet I. Group D - Attributes Data Sheet 2. RAD HARD MAX. “S” EQUIVALENT - OPTIONAL DATA PACKAGE A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - X-Ray and X-Ray Report F. Group A - Attributes Data Sheet - Subgroups A2, A3, A4, A5 and A7 Data G. Group B - Attributes Data Sheet - Subgroups B1, B3, B4, B5 and B6 Data H. Group C - Attributes Data Sheet - Subgroups C1, C2, C3 and C6 Data I. Group D - Attributes Data Sheet - Pre and Post Radiation Data FSPYE234R, FSPYE234F

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitewww.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369 FSPYE234R, FSPYE234F SMD.5

3 PAD CERAMIC LEADLESS CHIP CARRIER

b A D E 1 - GATE 2 - SOURCE 3 - DRAIN SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX A 0.112 0.124 2.84 3.15 3 b 0.090 0.100 2.28 2.54 - D 0.291 0.301 7.39 7.64 - D 1 0.281 0.291 7.13 7.39 - D 2 0.070 0.080 1.78 2.03 - E 0.395 0.405 10.03 10.28 - E1 0.220 0.230 5.58 5.84 - E2 0.115 0.125 2.92 3.17 - NOTES: 1. No current JEDEC outline for this package. 2. Controlling dimension: Inch. 3. Measurement prior to pre-solder coating the mounting pads. 4. Revision 4dated 5-00.