FSL4110LR ONSEMI | Alldatasheet
Document overview
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- PDF pages: 16
Technical content
Features
- Built−in Avalanche Rugged 1000 V SenseFET
- Precise Fixed Operating Frequency: 50 kHz
- VCC can be Supplied from either Bias−winding or Self−biasing
- Soft Burst−Mode Operation Minimizing Audible Noise
- Random Frequency Fluctuation for Low EMI
- Pulse−by−Pulse Current Limit
- Various Protection Functions: Overload Protection (OLP), Over−Voltage Protection (OVP), Abnormal Over−Current Protection (AOCP), Internal Thermal Shutdown (TSD) with Hysteresis. Under−Voltage Lockout (UVLO) and Line Over−V oltage Protection (LOVP) with Hysteresis.
- Built−in Internal Startup and Soft−Start Circuit
- Fixed 1.6 s Restart Time for Safe Auto−Restart Mode of All Protections
- These are Pb−Free Devices
Applications
- SMPS for Electric Metering
- Auxiliary Power Supply for 3−Phase Input Industrial Systems MARKING DIAGRAM See detailed ordering and shipping information on page 13 of this data sheet.
ORDERING INFORMATION
PDIP−7 (PDIP−8 LESS PIN 6) (7−DIP) CASE 626A PDIP7 MINUS PIN 6 GW (7−LSOP) CASE 707AA $Y&Z&2&K L4110LR $Y = Logo &Z = Assembly Plant Code &2 = 2−Digit Date Code &K = 2−Digits Lot Run Traceability Code L4110LR = Specific Device Code $Y&Z&2&K L4110LR FSL4110LRN FSL4110LRLX
Figure 3. Pin Configuration (Top View) 1 GND Ground. The SenseFET source terminal on primary side and the internal PWM control ground. is disable. A ceramic capacitor need to be placed as close as possible between this pin and pin 1 (GND). Recommended distance is less than 3 mm. current (IDELAY) for overload protection delay time. The resistance should not be exceed 5 M/C0087 in self−biasing. 1000 V. Minimizing the length of the trace connecting these pins to the transformer decreases leakage inductance.
should not be assumed, damage may occur and reliability may be affected.
- V FB and VIN are clamped by internal clamping diode (11 V, ICLAMP_MAX < 100 /C0109A).
- Repetitive peak switching current when the inductive load is assumed: Limited by maximum duty (DMAX = 0.73) and junction temperature
- Infinite cooling condition (refer to the SEMI G30−88).
- Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics.
Figure 4. Repetitive Peak Switching Current
- JEDEC recommended environment, JESD51−2, and test board, JESD51−3, with minimum land pattern.
www.onsemi.com ELECTRICAL CHARACTERISTICS (TJ = −40°C to 125°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Unit SenseFET SECTION BVDSS Drain−Source Breakdown Voltage (Note 9) VGS = 0 V, ID = 250 /C0109A 1000 − − V IDSS Zero−Gate−Voltage Drain Current (Note 9) VDS = 1000 V, VGS = 0 V − − 250 /C0109A RDS(ON) Drain−Source On−State Resistance (Note 9) VGS = 10 V, ID = 1.0 A − − 10 /C0087 CISS Input Capacitance (Note 9) (Note 10) VDS = 25 V, VGS = 0 V, f = 1 MHz − 367 477 pF COSS Output Capacitance (Note 9) (Note 10) − 37.5 48.8 pF td(on) Turn−On Delay Time (Note 9) VDD = 500 V, ID = 1.0 A, VGS = 10 V, Rg = 25 /C0087 − 13.7 − ns tr Rise Time (Note 9) − 14 − ns td(off) Turn−Off Delay Time (Note 9) − 33 − ns tf Fall Time (Note 9) − 45 − ns CONTROL SECTION fS Switching Frequency (Note 9) VCC = 14 V, VFB = 4 V 46.5 50.0 53.5 kHz fM Frequency Modulation (Note 10) − ±1.5 − kHz DMAX Maximum Duty Ratio VCC = 14 V, VFB = 4 V 61 67 73 % IFB Feedback Source Current (Note 9) VFB = 0 V 70 100 130 /C0109A VSTART UVLO Threshold Voltage VFB = 0 V, VCC Sweep 11 12 13 V VSTOP After Turn−on, VFB = 0 V 7 8 9 tS/S Internal Soft−Start Time VSTR = 40 V, VCC Sweep − 20 − ms BURST−MODE SECTION VBURH Burst−Mode Voltage (Note 9) VCC = 14 V, VFB Sweep 0.45 0.50 0.55 V VBURL 0.35 0.40 0.45 V VHYS − 100 − mV PROTECTION SECTION ILIM Peak Drain Current Limit (Note 9) di/dt = 240 mA//C0109s 0.45 0.52 0.59 A VOLP Overload Protection (Note 9) VCC = 14 V, VFB Sweep 4.0 4.4 4.8 V VAOCP Abnormal Over−Current Protection (Note 10) − 1.0 − V tLEB Leading−Edge Blanking Time (Note 10) (Note 11) − 250 − ns tCLD Current Limit Delay Time (Note 10) − − 200 ns VOVP Over−Voltage Protection VCC Sweep 23.0 24.5 26.0 V VINH Line Over−Voltage Protection Threshold Voltage VCC = 14 V, VIN Sweep 1.9 2.0 2.1 V VINHYS Line Over−Voltage Protection Hysteresis (Note 9) VCC = 14 V, VIN Sweep − 100 − mV tDELAY Overload Protection Delay − 100 − ms tRESTART Restart Time After Protection (Note 10) − 1.6 − s TSD Thermal Shutdown Temperature (Note 10) Shutdown Temperature 130 140 150 °C THYS Hysteresis (FSL4110LRN) − 60 − THYS Hysteresis (FSL4110LRLX) − 30 − HIGH VOLTAGE REGULATOR SECTION VHVREG HV Regulator Voltage VFB = 0 V, VSTR = 40 V 9 10 11 V
www.onsemi.com ELECTRICAL CHARACTERISTICS (TJ = −40°C to 125°C unless otherwise noted) (continued) Symbol UnitMaxTypMinConditionsParameter TOTAL DEVICE SECTION IOP Operating Supply Current, (Control Part in Burst Mode) (Note 9) VCC = 14 V, VFB = 0 V − 0.40 0.50 mA IOPS Operating Switching Current, (Control Part and SenseFET Part) (Note 9) VCC = 14 V, VFB = 2 V − 1.00 1.35 mA ISTART Start Current (Note 9) VCC = 11 V (Before VCC Reaches VSTART) − 160 240 /C0109A ICH Startup Charging Current (Note 9) VCC = VFB = 0 V, VSTR = 40 V 1.5 2.0 − mA VSTR Minimum VSTR Supply Voltage CVCC = 0.1 /C0109F, VSTR Sweep − − 26 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 9. T J = 25°C. 10.Although these parameters are guaranteed, they are not 100% tested in production. 11. tLEB includes gate turn−on time.
Figure 19. Auto−Restart Protection Waveforms internal OLP circuit is shown in Figure 21. Figure 20. OLP Waveforms
2.4 V tRESTART
Figure 21. OLP Circuit through the SenseFET during the minimum turn−on time. Figure 22. AOCP Waveforms
www.onsemi.com RDS(ON) (Max) Output Power Table (Note 12) Shipping† 45~460 VAC (Note 13) 85~460 VAC (Note 13) FSL4110LRN PDIP−7 (PDIP−8 LESS PIN 6) (7−DIP) (Pb−Free) −40°C~125°C 0.52 A 10 /C00874 W (Note 14) 9 W (Note 14) 3000 Units / Tube FSL4110LRLX PDIP7 MINUS PIN 6 GW (7−LSOP) (Pb−Free) 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 12.The junction temperature can limit the maximum output power. 13.Maximum practical continuous power in an open−frame design at 50°C ambient temperatures. 14.Bias winding condition.
PDIP−7 (PDIP−8 LESS PIN 6) CASE 626A ISSUE C DATE 22 APR 2015 SCALE 1:1 NOTE 8 D b L A eB XXXXXXXXX AWL YYWWG E GENERIC MARKING DIAGRAM* XXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb −Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ /C0071”, may or may not be present. A TOP VIEW C SEATING PLANE
0.010 CASIDE VIEW
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK- AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY . 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). M c B H NOTE 5 e e/2 A2 NOTE 3 M B M NOTE 6 M DIM MIN MAX INCHES A −−−− 0.210 A1 0.015 −−−− b 0.014 0.022 C 0.008 0.014 D 0.355 0.400 D1 0.005 −−−− e 0.100 BSC E 0.300 0.325 M −−−− 10 −−− 5.33 0.38 −−− 0.35 0.56 0.20 0.36 9.02 10.16 0.13 −−−
2.54 BSC
7.62 8.26 −−− 10 MIN MAX MILLIMETERS E1 0.240 0.280 6.10 7.11 0.060 TYP 1.52 TYP A2 0.115 0.195 2.92 4.95 L 0.115 0.150 2.92 3.81 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON11774DDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1PDIP−7 (PDIP−8 LESS PIN 6) © Semiconductor Components Industries, LLC, 2019 www.onsemi.com
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON13755GDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1PDIP7 MINUS PIN 6 GW © Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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