FSDH321 FAIRCHILD | Alldatasheet
Document overview
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Technical content
Features
- Internal Avalanche Rugged Sense FET
- Consumes only 0.65W at 240V AC & 0.3W load with Advanced Burst-Mode Operation
- Frequency Modulation for EMI Reduction
- Precision Fixed Operating Frequency
- Internal Start-up Circuit
- Pulse-by-Pulse Current Limiting
- Abnormal Over Current Protection (AOCP)
- Over V oltage Protection (OVP)
- Over Load Protection (OLP)
- Internal Thermal Shutdown Function (TSD)
- Auto-Restart Mode
- Under V oltage Lockout (UVLO)
- Low Operating Current (max 3mA)
- Adjustable Peak Current Limit
- Built-in Soft Start
Applications
- SMPS for STB, Low cost DVD Player
- Auxiliary Power for PC
- Adapter & Charger Related Application Notes
- AN-4137, 4141, 4147(Flyback) / AN-4134(Forward)
Description
Each product in the FSDx321 (x for H, L) family consists of an integrated Pulse Width Modulator (PWM) and Sense FET, and is specifically designed for high performance off- line Switch Mode Power Supplies (SMPS) with minimal external components. Both devices are integrated high volt- age power switching regulators which combine an avalanche rugged Sense FET with a current mode PWM control block. The integrated PWM controller features include: a fixed oscillator with frequency modulation for reduced EMI, Under V oltage Lock Out (UVLO) protection, Leading Edge Blanking (LEB), an optimized gate turn-on/turn-off driver, Thermal Shut Down (TSD) protection, Abnormal Over Cur- rent Protection (AOCP) and temperature compensated preci- sion current sources for loop compensation and fault protection circuitry. When compared to a discrete MOSFET and controller or RCC switching converter solution, the FSDx321 devices reduce total component count, design size, weight while increasing efficiency, productivity and system reliability. Both devices provide a basic platform that is well suited for the design of cost-effective flyback converters. Notes: 1. Typical continuous powe r in a non-ventilated enclosed adapter with sufficient drain pattern as a heat sinker, at 50°C ambient. 2. Maximum practical continuous power in an open frame design with sufficient drain pattern as a heat sinker, at 50°C ambient. 3. 230 VAC or 100/115 VAC with doubler. Typical Circuit Figure 1. Typical Flyback Application
Figure 2. Functional Block Diagram of FSDx321
Figure 3. Pin Configuration (Top View) 1 GND Sense FET source terminal on primary side and internal control ground. vice power is supplied via the auxiliary transformer winding. The feedback voltage pin is the non-inverting input to the PWM comparator. external capacitor Cfb from 3V to 6V using an internal 5uA current source. allows the protection mechanism to operate under true overload conditions. 12V, the internal switch is opened.
FSDH321, FSDL321 Absolute Maximum Ratings (Ta=25°C, unless otherwise specified) Note: 1. Repetitive rating: Pulse width is limited by maximum junction temperature 2. L = 24mH, starting Tj = 25°C Thermal Impedance (Ta=25°C, unless otherwise specified) Note: 1. Free standing with no heatsink; Without copper clad. / Measurement Condition : Just before junction temperature TJ enters into OTP. 2. Measured on the DRAIN pin close to plastic interface. - all items are tested with the standards JESD 51-2 and 51-10 (DIP). Characteristic Symbol Value Unit Drain Pin Voltage V DRAIN 650 V Vstr Pin Voltage V STR 650 V Drain-Gate Voltage V DG 650 V Gate-Source Voltage V GS ±2 0 V Drain Current Pulsed(1) IDM 1.5 A Continuous Drain Current (Tc=25℃) ID 0.7 A Continuous Drain Current (Tc=100℃) ID 0.32 A Single Pulsed Avalanche Energy(2) EAS 10 mJ Supply Voltage V CC 20 V Feedback Voltage Range V FB -0.3 to VCC V Total Power Dissipation P D 1.40 W Operating Junction Temperature T J Internally limited °C Operating Ambient Temperature T A -25 to +85 °C Storage Temperature T STG -55 to +150 °C Parameter Symbol Value Unit 8DIP Junction-to-Ambient Thermal(1) θJA 88.84 °C/W Junction-to-Case Thermal(2) θJC 13.94 °C/W
FSDH321, FSDL321
Electrical Characteristics
(Ta = 25°C unless otherwise specified) Note: 1. Pulse test: Pulse width ≤ 300us, duty ≤ 2% 2. These parameters, although guaranteed, are tested in EDS (wafer test) process 3. These parameters, although guaranteed, are not 100% tested in production Parameter Symbol Condition Min. Typ. Max. Unit SENSE FET SECTION Zero-Gate-Voltage Drain Current I DSS VDS=650V, VGS=0V - - 25 µAVDS=520V, VGS=0V, TC=125°C - - 200 Drain-Source On-State Resistance RDS(ON) VGS=10V, ID=0.5A - 14 19 Ω Forward Trans-Conductance(1) gfs VDS=50V, ID=0.5A 1.0 1.3 - S Input Capacitance C ISS VGS=0V, VDS=25V, f=1MHz - 162 - pFOutput Capacitance C OSS -1 8- Reverse Transfer Capacitance C RSS -3 . 8- Turn-On Delay Time t d(on) VDS=325V, ID=1.0A -9 . 5- nsRise Time t r -1 9- Turn-Off Delay Time t d(off) -3 3- Fall Time t f - 42 - Total Gate Charge Q g VGS=10V, ID=1.0A, VDS=325V -7 . 0- nCGate-Source Charge Q gs -3 . 1- Gate-Drain (Miller) Charge Q gd -0 . 4- CONTROL SECTION Switching Frequency f OSC FSDH321 90 100 110 KHz Switching Frequency Modulation ∆fMOD ±2.5 ±3.0 ±3.5 KHz Switching Frequency f OSC FSDL321 45 50 55 KHz Switching Frequency Modulation ∆fMOD ±1.0 ±1.5 ±2.0 KHz Switching Frequency Variation(2) ∆fOSC -25°C ≤ Ta ≤ 85°C - ±5 ±10 % Maximum Duty Cycle D MAX FSDH321 62 67 72 % FSDL321 71 77 83 % UVLO Threshold Voltage VSTART V FB=GND 11 12 13 V VSTOP V FB=GND 7 8 9 V Feedback Source Current I FB V FB=GND 0.7 0.9 1.1 mA Internal Soft Start Time t S/S V FB=4V 10 15 20 ms BURST MODE SECTION Burst Mode Voltage VBURH Tj=25°C 0.4 0.5 0.6 V VBURL 0.25 0.35 0.45 V VBUR(HYS) Hysteresis - 150 - mV PROTECTION SECTION Peak Current Limit I LIM Tj=25°C, ∆i/∆t=250mA/us 0.60 0.70 0.80 A Current Limit Delay Time(3) tCLD Tj=25 °C - 600 - ns Thermal Shutdown Temperature(3) TSD 125 145 - °C Shutdown Feedback Voltage V SD 5.5 6.0 6.5 V Over Voltage Protection V OVP 18 19 20 V Shutdown Delay Current I DELAY V FB=4V 3.5 5.0 6.5 µA Leading Edge Blanking Time t LEB 200 - - ns TOTAL DEVICE SECTION Operating Supply Current (control part only) IOP V CC=14V, VFB=0V 1 3 5 mA Start-Up Charging Current I CH V CC=0V 0.7 0.85 1.0 mA Vstr Supply Voltage V STR VCC=0V 35 - - V
FSDH321, FSDL321 Comparison Between FSDM311 and FSDx321 Function FSDM311 FSDx321 FSDx321 Advantages Soft-Start 15ms 15ms (same for both devices)
- Gradually increasing current limit during soft-start further reduces peak current and voltage stresses
- Eliminates external components used for soft-start in most applications
- Reduces or eliminates output overshoot External Current Limit not applicable Programmable of default current limit
- Smaller transformer
- Allows power limiting (constant over- load power)
- Allows use of larger device for lower losses and higher efficiency. Frequency Modulation not applicable ±3.0KHz @100KHz ±1.5KHz @50KHz
- Reduces conducted EMI Burst Mode Operation Built into controller Built into controller (same for both devices)
- Improves light load efficiency
- Reduces power consumption at no- load
- Transformer audible noise reduction Drain Creepage at Package 7.62mm 7.62mm (same for both devices)
- Greater immunity to arcing provoked by dust, debris and other contami- nants
FSDH321, FSDL321 Typical Performance Characteristics (Control Part) (These characteristic graphs are normalized at Ta = 25°C) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 Temp[ ℃] Normalized Operating Frequency (Fosc) vs. Ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 Temp[ ℃] Normalized Frequency Modulation (∆FMOD) vs. Ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 Temp[ ℃] Normalized Maximum Duty Cycle (DMAX) vs. Ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 Temp[ ℃] Normalized Operating Supply Current (IOP) vs. Ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 Temp[ ℃] Normalized Start Threshold Voltage (VSTART) vs. Ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 Temp[ ℃] Normalized Stop Threshold Voltage (VSTOP) vs. Ta
FSDH321, FSDL321 Typical Performance Characteristics (Continued) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 Temp[ ℃] Normalized Feedback Source Current (IFB) vs. Ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 Temp[ ℃] Normalized Peak Current Limit (ILIM) vs. Ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 Temp[ ℃] Normalized Start Up Charging Current (ICH) vs. Ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 Temp[ ℃] Normalized Burst Peak Current (IBUR(pk)) vs. Ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 Temp[ ℃] Normalized Over Voltage Protection (VOVP) vs. Ta
- Startup : In previous generations of Fairchild Power
Figure 4. High Voltage Current Source
- Feedback Control : The FSDx321 employs current mode
Figure 5. Pulse Width Modulation (PWM) Circuit
- Leading Edge Blanking (LEB) : At the instant the inter-
LEB) after the Sense FET is turned on.
- Protection Circuits : The FPS has several protective
until the fault condition is eliminated.
4.1 Over Load Protection (OLP) : Overload is defined as
tion (OLP) circuit can be activated during the load transition.
3 OSC
Figure 6. Over Load Protection (OLP)
4.2 Thermal Shutdown (TSD) : The Sense FET and the
4.3 Abnormal Over Current Protection (AOCP) : Even
the Sense FET within 350ns after it is activated. Figure 7. Abnormal Over Current Protection (AOCP)
4.4 Over Voltage Protection (OVP) : In the event of a mal-
tion, Vcc should be properly designed to be below 19V .
FSDH321, FSDL321 Typical Application Circuit
- High efficiency (>70% at full load, full input range)
- Low standby mode power consumption (<1W at DC 375V input and 0.5W load)
- Low component count
- Enhanced system reliability through various protection functions
- Low EMI through frequency modulation
- Internal soft-start (15ms) Key Design Notes
- The delay time for over load protection is designed to be about 13ms with C104 of 22nF. If faster/slower triggering of OLP is required, C104 can be changed to a smaller/larger value(eg. 47nF for about 30ms).
- The pule-by-pulse peak current limit level(I LIM) is set to default value 0.7A by floating the Ipk pin (#4).
- R102 and C101 clamp the DRAIN voltage of MOSFET below 650V under all conditions. 1. Schematic Application Output power Input vo ltage Output voltage (Max current) PC Auxiliary Power Supply 10W DC 140~375V 5.0V (2.0A) 10W PC Auxiliary Power Circuit EE1625 D201 SB360 C201 1000uF 16V C203 470uF 16V L201 10uH 5V (+/-5%) C101 10nF 630V R102 100kΩ D101 UF 4007 C104 22nF C103 10uF 50V D103 1N 4937 R104 10Ω R202 330Ω R201 1kΩ R203 2kΩ C202 100nF R204 2kΩ IC 301 H11A817A IC201 KA431 Vfb Vcc Drain GND 140~375 VDC INPUT IC101 FSDx321 6,7,8 R103 10Ω D102 1N4937 C102 47uF 50V M Vcc C301 2.2nF Vstr R101 680kΩ ZD1 18V ZD2 18V
FSDH321, FSDL321 2. Transformer Schematic Diagram 3. Winding Specification 4. Electrical Characteristics 5. Core & Bobbin Core : EER1625 Bobbin : EER1625 EE1625 Np/2 Na N5V NM Vcc 10Np/2 Na NM Vcc N5V Np/2 Np/2 Pin(S → F) Wi r e Turns Winding Method N p/2 3 → 2 0.15φ ×1 80 Solenoid winding Insulation : Polyester Tape t = 0.050m m, 3Layers N 5V 10 → 7 0.55φ ×1 12 Solenoid winding Insulation : Polyester Tape t = 0.050m m, 3Layers N MVcc 4 → 6 0.20φ ×1 40 Solenoid winding Insulation : Polyester Tape t = 0.050m m, 3Layers N P/2 2 → 1 0.15φ ×1 80 Solenoid winding Insulation : Polyester Tape t = 0.050m m, 3Layers N a 5 → 6 0.20φ ×1 34 Solenoid winding Outer Insulation : Polyester Tape t = 0.050m m, 3Layers Pi n Spec. Remar k Inductance 1－ 3 1.8 m H 1kH z, 1V Leakage 1－ 3 100 uH 2nd side all short
FSDH321, FSDL321 6. Demo Circuit Part List Part Value Note Part Value Note Resistor Inductor R101 680K 1W L201 10uH - R102 100K 1W - R103 10 1/4W Diode R104 10 1/4W D101 UF4007 PN Ultra Fast R201 1K 1/4W D102 1N4937 PN Ultra Fast R202 330 1/4W D103 1N4937 PN Ultra Fast R203 2K 1/4W D201 SB360 Schottky R204 2K 1/4W ZD1 1N4746A 18V Zener ZD2 1N4746A 18V Zener Capacitor C101 10nF/630V Film IC C102 47uF/50V Electrolytic IC101 FSDH321 FPS™ C103 10uF/50V Electrolytic IC201 KA431(TL431) Voltage reference C104 22nF/50V Film IC301 H11A817A Opto-Coupler C201 1000uF/16V Electrolytic C202 100nF/50V Ceramic C203 1uF/100V Electrolytic C204 470uF/16V Electrolytic C301 2.2nF/35V Ceramic
FSDH321, FSDL321 Package Dimensions 8DIP
FSDH321, FSDL321 Package Dimensions (Continued) 8LSOP
FSDH321, FSDL321
Ordering Information
Product Number Package Marking Code BV DSS fOSC RDS(ON) FSDH321 8DIP DH321 650V 100KHz 14 Ω FSDL321 8DIP DL321 650V 50KHz 14 Ω FSDH321L 8LSOP DH321 650V 100KHz 14 Ω FSDL321L 8LSOP DL321 650V 50KHz 14 Ω
FSDH321, FSDL321 9/29/05 0.0m 001 © 2005 Fairchild Semiconductor Corporation LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.