FSB50250S FAIRCHILD | Alldatasheet

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Technical content

Features

  • 500V 2.0A 3-phase FRFET inverter including high voltage integrated circuit (HVIC)
  • 3 divided negative dc-link terminals for inverter current sens- ing applications
  • HVIC for gate driving and undervoltage protection
  • 3/5V CMOS/TTL compatible, active-high interface
  • Optimized for low electromagnetic interference
  • Isolation voltage rating of 1500Vrms for 1min.
  • Surface mounted device package
  • Moisture Sensitive Level 3 General Description FSB50250S is a tiny smart power module (SPM) based on FRFET technology as a compact inverter solution for small power motor drive applications such as fan motors and water suppliers. It is composed of 6 fast-recovery MOSFET (FRFET), and 3 half-bridge HVICs for FRFET gate driving. FSB50250S provides low electromagnetic in terference (EMI) characteristics with optimized switching speed. Moreover, since it employs FRFET as a power switch, it has much better ruggedness and larger safe operation area (SOA) than that of an IGBT-based power module or one-chip solution. The package is optimized for the thermal performance and compactness for the use in the built-in motor application and any other application where the assembly space is concerned. F SB50250S is the most solution for the compact inverter providing the energy efficiency, compactness, and low electromagnetic interference. Absolute Maximum Ratings Symbol Parameter Conditions Rating Units VPN1 DC Link Input Voltage, Drain-source Voltage of each FRFET T J = 25°C 500 V VPN2 TJ = 150°C 500 V ID25 Each FRFET Drain Current, Continuous T C = 25°C 1.0 A ID80 Each FRFET Drain Current, Continuous T C = 100°C 0.7 A IDP Each FRFET Drain Current, Peak T C = 25°C, PW < 100µs 2.0 A PD Maximum Power Dissipation T C = 25°C, For Each FRFET 13 W VCC Control Supply Voltage Applied between V CC and COM 20 V VBS High-side Bias Voltage Applied between V B and VS 20 V VIN Input Signal Voltage Applied between IN and COM -0.3 ~ VCC+0.3 V TJ Operating Junction Temperature -20 ~ 150 °C TSTG Storage Temperature -50 ~ 150 °C RθJC Junction to Case Thermal Resistance Each FRFET under inverter operat- ing condition (Note 1) 9.3 °C/W VISO Isolation Voltage 60Hz, Sinusoidal, 1 minute, Con- nection pins to heatsink 1500 V rms

Source terminal of each MOSFET is not connected to supply ground or bias voltage ground inside SPM. External connections should be made as indicated in Figure 2 and 5. Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)

1 COM IC Common Supply Ground

10 IN (VL) Signal Input for V Phase Low-side

11 V S(V) Bias Voltage Ground for V Phase High Side FRFET Driving

12 V B(W) Bias Voltage for W Phase High Side FRFET Driving

13 V CC(W) Bias Voltage for W Phase IC and Low Side FRFET Driving

14 IN (WH) Signal Input for W Phase High-side

15 IN (WL) Signal Input for W Phase Low-side

16 V S(W) Bias Voltage Ground for W Phase High Side FRFET Driving

17 P Positive DC–Link Input

18 U, V S(U) Output for U Phase & Bias Voltage Ground for High Side FRFET Driving

19 N U Negative DC–Link Input for U Phase

20 N V Negative DC–Link Input for V Phase

21 V, V S(V) Output for V Phase & Bias Voltage Ground for High Side FRFET Driving

22 N W Negative DC–Link Input for W Phase

23 W, V S(W) Output for W Phase & Bias Voltage Ground for High Side FRFET Driving

3 www.fairchildsemi.com FSB50250S Rev. A FSB50250S Smart Power Module (SPM) Electrical Characteristics (TJ = 25°C, VCC=VBS=15V Unless Otherwise Specified) Inverter Part (Each FRFET Unless Otherwise Specified) Control Part (Each HVIC Unless Otherwise Specified) Note: 1. For the measurement point of case temperature T C, please refer to Figure 3 in page 4. 2. BV DSS is the absolute maximum voltage rating between drain and source terminal of each FRFET inside SPM. VPN should be sufficiently less than this value considering the effect of the stray inductance so that VDS should not exceed BVDSS in any case. 3. t ON and tOFF include the propagation delay time of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the field applcations due to the effect of different printed circuit boards and wirings. Please see Figure 4 for the switching time definition with the switching test circuit of Figure 5. 4. The peak current and voltage of each FRFET during the switching operation should be included in the safe operating area (SOA) . Please see Figure 5 for the RBSOA test cir- cuit that is same as the switching test circuit. Symbol Parameter Conditions Min Typ Max Units BVDSS1 Drain-Source Breakdown Voltage VIN= 0V, ID = 250µA (Note 2) 500 - - V BVDSS2 VIN= 0V, ID = 250µA, TJ = 150°C 500 - - V ∆BVDSS/ ∆TJ Breakdown Voltage Tem- perature Coefficient ID = 250µA, Referenced to 25°C - 0.53 - V IDSS Zero Gate Voltage Drain Current VIN= 0V, VDS = 500V - - 250 µA RDS(on) Static Drain-Source On-Resistance VCC = VBS = 15V, VIN = 5V, ID = 0.5A - 3.3 4.0 Ω VSD Drain-Source Diode Forward Voltage VCC = VBS = 15V, VIN = 0V, ID = -0.5A - - 1.2 V tON Switching Times VPN = 300V, VCC = VBS = 15V, ID = 0.5A VIN = 0V ↔ 5V, REH = 0Ω Inductive load L=3mH High- and low-side FRFET switching (Note 3) - 1273 - ns t OFF - 800 - ns trr - 213 - ns EON -4 2- µJ EOFF -2 . 8- µJ RBSOA Reverse-bias Safe Oper- ating Area VPN = 400V, VCC = V BS = 15V, ID = I DP, VDS=BVDSS, TJ = 150°C High- and low-side FRFET switching (Note 4) Full Square Symbol Parameter Conditions Min Typ Max Units IQCC Quiescent VCC Current V CC=15V, VIN=0V Applied between V CC and COM - - 160 µA IQBS Quiescent VBS Current V BS=15V, VIN=0V Applied between VB(U)-U, VB(V)-V, VB(W)-W - - 100 µA UVCCD Low-side Undervoltage Protection (Figure 6) VCC Undervoltage Protection Detection Level 7.4 8.0 9.4 V UVCCR VCC Undervoltage Protection Reset Level 8.0 8.9 9.8 V UVBSD High-side Undervoltage Protection (Figure 7) VBS Undervoltage Protection Detection Level 7.4 8.0 9.4 V UVBSR VBS Undervoltage Protection Reset Level 8.0 8.9 9.8 V VIH ON Threshold Voltage Logic High Level Applied between IN and COM 3.0 - - V VIL OFF Threshold Voltage Logic Low Level - - 0.8 V IIH Input Bias Current VIN = 5V Applied between IN and COM -1 0 2 0 µA IIL VIN = 0V - - 2 µA

Figure 8. Example of Application Circuit

7 www.fairchildsemi.com FSB50250S Rev. A FSB50250S Smart Power Module (SPM) Detailed Package Outline Drawings 12.00±0.20 29.00±0.20 0.60±0.10 Max 1.00 (1.80) (1.30) 1.95 #1 #16 #17 #23 2x3.90=7.80±0.30 0.508 0.15±0.05 5°±3° 1.50±0.20 (2.50) (1.30) GAGE PLANE Max 3.50 13.34±0.30 SEATING PLANE (1.80) 3.10±0.20 (1.00) 17.00±0.20 0.50+0.10 -0.05 #1 #16 17.90 12.30 2.80 15*1.778=26.67 1.30 13.34±0.30 15.607.80 4.43 2.48 LAND PATTERN RECOMMENDATIONS 0.60±0.10 Max 1.00

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 8 www.fairchildsemi.com FSB50250S Rev. A FSB50250S Smart Power Module (SPM) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO M AKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELI ABILITY, FUNCTION OR DESIGN. FAI RCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PR ODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This data sheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datas heet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. FAST® FASTr™ FPS™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ I 2C™ i-Lo™ ImpliedDisconnect™ IntelliMAX™ ISOPLANAR™ LittleFET™ MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerEdge™ PowerSaver™ PowerTrench QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ µSerDes™ SILENT SWITCHER SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic TINYOPTO™ TruTranslation™ UHC™ UltraFET UniFET™ VCX™ ACEx™ ActiveArray™ Bottomless™ CoolFET™ CROSSVOLT™ DOME™ EcoSPARK™ E 2CMOS™ EnSigna™ FACT™ FACT Quiet Series™ Across the board. Around the world.™ The Power Franchise Programmable Active Droop™ Rev. I15