FSB50250B ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- UL Certified No. E209204 (UL1557)
- Optimized for over 10 kHz Switching Frequency
- 500 V FRFET MOSFET 3−Phase Inverter with Gate Drivers and Protection
- Built−In Bootstrap Diodes Simplify PCB Layout
- Separate Open−Source Pins from Low−Side MOSFETs for Three−Phase Current−Sensing
- Active−HIGH Interface, Works with 3.3 / 5 V Logic, Schmitt−trigger Input
- Optimized for Low Electromagnetic Interference
- HVIC Temperature−Sensing Built−In for Temperature Monitoring
- HVIC for Gate Driving and Under−V oltage Protection
- Isolation Rating: 1500 Vrms / min.
- Moisture Sensitive Level (MSL)3 for SMD
- These Devices are Pb−Free and are RoHS Compliant
Applications
- 3−Phase Inverter Driver for Small Power AC Motor Drives Related Source
- AN−9080 − FSB50450AS − User’s Guide for Motion SPM 5 Series
- AN−9082 − Motion SPM5 Series Thermal Performance by Contact Pressure SPM5E−023 / 23LD, PDD STD CASE MODEJ See detailed ordering and shipping information on page 2 of this data sheet.
ORDERING INFORMATION
www.onsemi.com $Y = ON Semiconductor Logo &Z = Assembly Plant Code &3 = Data Code (Year & Week) &K = Lot FSB50250X = Specific Device Code ⇒ X = B or BS MARKING DIAGRAM FSB50250X SPM5H−023 / 23LD, PDD STD, SPM23−BD CASE MODEM
www.onsemi.com PACKAGE MARKING AND ORDERING INFORMATION Device Device Marking Package Packing Type Reel Size Quantity FSB50250B FSB50250B SPM5P−023 Rail NA 15 FSB50250BS FSB50250BS SPM5Q−023 Tape & Reel 330 mm 450 ABSOLUTE MAXIMUM RATINGS (TC = 25°C, Unless otherwise noted) Symbol Parameter Conditions Rating Unit INVERTER PART (Each MOSFET Unless Otherwise Specified) VDSS Drain−Source Voltage of Each MOSFET 500 V *ID 25 Each MOSFET Drain Current, Continuous TC = 25°C 1.9 A *ID 80 Each MOSFET Drain Current, Continuous TC = 80°C 1.2 A *IDP Each MOSFET Drain Current, Peak TC = 25°C, PW < 100 /C0109s 5.0 A *IDRMS Each MOSFET Drain Current, Rms TC = 80°C, FPWM < 20 kHz 0.9 Arms CONTROL PART (Each HVIC Unless Otherwise Specified) VDD Control Supply Voltage Applied Between VDD and COM 20 V VBS High−side Bias Voltage Applied Between VB and VS 20 V VIN Input Signal Voltage Applied Between IN and COM −0.3 ~ VDD+0.3 V BOOTSTRAP DIODE PART (Each Bootstrap Diode Unless Otherwise Specified.) VRRMB Maximum Repetitive Reverse Voltage 500 V * IFB Forward Current TC = 25°C 0.5 A * IFPB Forward Current (Peak) TC = 25°C, Under 1 ms Pulse Width 1.5 A THERMAL RESISTANCE Rth(j−c)Q Junction to Case Thermal Resistance (Note 1) Inverter MOSFET part, (Per Module) 2.6 °C/W TOTAL SYSTEM TJ Operating Junction Temperature −40 ~ 150 °C TSTG Storage Temperature −40 ~ 125 °C VISO Isolation Voltage 60 Hz, Sinusoidal, 1 minute, Connection Pins to Heatsink
1500 Vrms
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. For the Measurement Point of Case Temperature T C, Please refer to Figure 4. 2. Marking “ * ” Is Calculation Value or Design Factor. 3. Using continuously under heavy loads or excessive assembly conditions (e.g. the application of high temperature/ current/ voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/ current/ voltage, etc.) are within the absolute maximum ratings and the operating ranges.
1 COM IC Common Supply Ground
2 VB(U) Bias Voltage for U Phase High Side FRFET Driving
3 VDD(U) Bias Voltage for U Phase IC and Low Side FRFET Driving
4 IN(UH) Signal Input for U Phase High−side
5 IN(UL) Signal Input for U Phase Low−side
7 VB(V) Bias Voltage for V Phase High Side FRFET Driving
8 VDD(V) Bias Voltage for V Phase IC and Low Side FRFET Driving
9 IN(VH) Signal Input for V Phase High−side
10 IN(VL) Signal Input for V Phase Low−side
11 VTS Output for HVIC Temperature Sensing
12 VB(W) Bias Voltage for W Phase High Side FRFET Driving
13 VDD(W) Bias Voltage for W Phase IC and Low Side FRFET Driving
14 IN(WH) Signal Input for W Phase High−side
15 IN(WL) Signal Input for W Phase Low−side
17 P Positive DC–Link Input
18 U, VS(U) Output for U Phase & Bias Voltage Ground for High Side FRFET Driving
19 NU Negative DC–Link Input for U Phase
20 NV Negative DC–Link Input for V Phase
21 V, VS(V) Output for V Phase & Bias Voltage Ground for High Side FRFET Driving
22 NW Negative DC–Link Input for W Phase
23 W, VS(W) Output for W Phase & Bias Voltage Ground for High Side FRFET Driving
Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)
- Source Terminal of Each Low−Side MOSFET is Not Connected to Supply Ground or Bias Voltage Ground Inside Motion
SPM 5 product. External Connections Should be Made as Indicated in Figure 3.
www.onsemi.com ELECTRICAL CHARACTERISTICS (TJ = 25°C, VDD = VBS = 15 V Unless Otherwise Specified) Symbol Parameter Test Conditions Min. Typ. Max. Unit INVERTER PART (Each MOSFET Unless Otherwise Specified) BVDSS Drain−Source Breakdown Voltage VIN = 0 V, ID = 1 mA ( Note 5) 500 − − V IDSS Zero Gate Voltage Drain Current VIN = 0 V, VDS = 500 V − − 1 mA RDS(on) Static Drain−Source On−Resistance VDD = VBS = 15 V, VIN = 5 V, ID = 0.5 A − 5.5 6.4 /C0087 VSD Drain−Source Diode Forward Voltage VDD = VBS = 15 V, VIN = 0 V, ID = −0.5 A − − 1.1 V tON Switching Times VPN = 300 V, VDD = VBS = 15 V, ID = 0.5 A VIN = 0 V ↔ 5 V, Inductive Load L = 3 mH High− and Low−Side MOSFET Switching (Note 6) − 580 − ns tOFF − 450 − ns trr − 150 − ns EON − 30 − /C0109J EOFF − 3 − /C0109J RBSOA Reverse−Bias Safe Operating Area VPN = 400 V, VDD = VBS = 15 V, ID = IDP, VDS = BVDSS, TJ = 150°C High− and Low−Side MOSFET Switching (Note 7) Full Square CONTROL PART (Each HVIC Unless Otherwise Specified) IQDD Quiescent VDD Current VDD = 15 V, VIN = 0 V Applied Between VDD and COM − − 200 /C0109A IQBS Quiescent VBS Current VBS = 15 V, VIN = 0 V Applied Between VB(U)−U, VB(V)−V, VB(W)−W − − 100 /C0109A IPDD Operating VDD Supply VDD − COM VDD = 15 V, fPWM = 20 kHz, Duty = 50%, Applied to One PWM Signal Input for Low−Side − − 900 /C0109A IPBS Operating VBS Supply Current VB(U)− VS(U), VB(V) − VS(V), VB(W) − VS(W) VDD = VBS = 15 V, fPWM = 20 kHz, Duty = 50%, Applied to One PWM Signal Input for High−Side − − 800 /C0109A UVDDD Low−Side Undervoltage Protection (Figure 8) VDD Undervoltage Protection Detection Level 7.4 8.0 9.4 V UVDDR VDD Undervoltage Protection Reset Level 8.0 8.9 9.8 V UVBSD High−Side Undervoltage Protection (Figure 9) VBS Undervoltage Protection Detection Level 7.4 8.0 9.4 V UVBSR VBS Undervoltage Protection Reset Level 8.0 8.9 9.8 V VTS HVIC Temperature sensing voltage output VDD = 15 V, THVIC = 25°C (Note 8) 600 790 980 mV VIH ON Threshold Voltage Logic High Level Applied between IN and COM − − 2.9 V VIL OFF Threshold Voltage Logic Low Level 0.8 − − V BOOTSTRAP DIODE PART (Each Bootstrap Diode Unless Otherwise Specified) VFB Forward Voltage IF = 0.1 A, TC = 25°C (Note 9) − 2.5 − V trrB Reverse Recovery Time IF = 0.1 A, TC = 25°C − 80 − ns Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10 High side FRFET On
11 Forbidden Shoot through
Figure 3. Recommended MCU Interface and Bootstrap Circuit with Parameters
- RC−coupling (R5 and C5) and C4 at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent
improper signal due to surge−noise. 12.Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge−voltage. Bypass capacitors such as C1, C2 and C3 should have good high−frequency characteristics to absorb high−frequency ripple−current. Figure 4. Case Temperature Measurement to get the correct temperature measurement. Figure 5. Temperature Profile of VTS (Typical)
Figure 10. Example of Application Circuit 14.About pin position, refer to Figure 1. signal caused by surge−noise. 17.Ground−wires and output terminals, should be thick and short in order to avoid surge−voltage and malfunction of HVIC. high−frequency ripple current.
www.onsemi.com PACKAGE DIMENSIONS SPM5H−023 / 23LD, PDD STD, SPM23−BD (Ver1.5) SMD TYPE CASE MODEM ISSUE O
www.onsemi.com SPM5E−023 / 23LD, PDD STD, FULL PACK, DIP TYPE CASE MODEJ ISSUE O
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