FSAL200_06 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

■ Typical 6Ω switch connection between two ports ■ Minimal propagation delay through the switch ■ Low ICC ■ Zero bounce in flow-through mode ■ Control inputs compatible with TTL level ■ Rail-to-rail signal handling ■ Low insertion loss ■ Route communications signals include:

  • 10/100 Ethernet
  • 100VG-AnyLAN
  • A T M 2 5
  • SONET OCI 51.8 Mbps
  • USB1.1
  • T 1 / E 1
  • Token Ring 4/16 Mbps

Description

The Fairchild Switch FSAL200 is a rail-to-rail quad 2:1 high-speed CMOS TTL-compatible analog multiplexer/ demultiplexer switch. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. When OE is LOW, the select pin connects the A Port to the selected B Port output. When OE is HIGH, the switch is OPEN and a high-impedance state exists between the two ports.

Ordering Information

This device is also available in tape and reel. To order, append X to the part number. Part Number Package Number Pb-Free Package Packing Method FSAL200QSC MQA16 Yes 16-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide FSAL200MTC MTC16 Yes 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

© 2002 - 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FSAL200 Rev. 1.7.0 2 Analog Symbol Connection Diagram Truth Table Pin Descriptions SO E Function X HIGH Disconnect LOW LOW A=B1 HIGH LOW A=B2 Pin Name Function OE Switch Enable S Select Input A, B1, B2 Data Port

© 2002 - 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FSAL200 Rev. 1.7.0 3 Absolute Maximum Ratings The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines the condi- tions for actual device operation. Recommended Operating Conditions(2) 1. The input and output negative voltage ratings may be e xceeded if the input and output diode current ratings are observed. 2. Control input must be held HIGH or LOW; it must not float. Symbol Parameter Min. Max. Unit VCC Supply Voltage -0.5 7.0 V VS DC Switch Voltage(1) -0.5 0.5 V VIN DC Input Voltage(1) -0.5 7.0 V IIK DC Input Diode Current @ (IIK) VIN < 0V -50 mA IOUT DC Output Current 120 mA ICC/IGND DC VCC or Ground Current ±100 mA TSTG Storage Temperature Range -65 +150 °C PD Power Dissipation @ ±85°C 0.5 W TA Ambient Temperature with Power Applied -40 85 °C Symbol Parameter Min. Max. Unit VCC Supply Voltage Operating 3.0 5.5 V VIN Control Input Voltage 0 V CC V VIN Switch Input Voltage 0 V CC V VOUT Output Voltage 0 V CC V TA Operating Temperature -40 +85 °C tr, tf Input RIse and Fall Time Control Input Vcc = 2.3V - 3.6V 0 10 ns/V Control Input Vcc = 4.5V - 5.5V 0 5 ns/V O JA Thermal Resistance 350 °C/W

© 2002 - 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FSAL200 Rev. 1.7.0 4 3. Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two (A or B Ports). 4. ΔRON = RON maximum - RON minimum measured at identical VCC, temperature, and voltage levels. 5. Flatness is defined as the difference between the maximum and minimum value of On Resistance over the speci- fied range of conditions. Symbol Parameter Conditions VCC TA =-40°C to+85°C Units(V) Min. Typ. Max. VIH HIGH-Level Input Voltage 4.5 - 5.5 2.0 V 3.0 - 3.6 2.0 VIL LOW-Level Input Voltage 4.5 - 5.5 -0.5 0.8 V 3.0 - 3.6 -0.5 0.8 IOZ OFF State Leakage Current 0 £ V IN £5.5V 0 - 5.5 100 nA RON Switch On Resistance(3) ION = 10 - 30 mA 4.5 - 5.5 6 12 Ω ION = 10 - 30 mA 3.0 - 3.6 15 22 IIN Control Input Leakage Current V IN = VCC or GND 5.5 ±1 mA VIN = VCC or GND 3.6 ±1 ICC Quiescent Supply Current V IN = VCC or GND 5.5 1 mA All Channels ON or OFF I OUT = 0 Analog Signal Range V CC 0V CC V ΔRON On Resistance Match Between I A= -30 mA, VBn = 3.15 4.5 - 5.5 0.4 2 Ω Channels (3,4) IA = -10 mA, VBn 2.1 3.0 - 3.6 1 3 IO Output Current B n, Bn, S = 0V to 5V 4.5 - 5.5 100 mA 3.0 - 3.6 80 Rflat On Resistance Flatness(3,5) A, B1, B2 = 0V to 5V 4.5 - 5.5 3 Ω A, B1, B2 = 0V to 5V 3.0 - 3.6 7

Dimensions are in inches (millimeters) unless otherwise noted. Figure 9. 16-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0/0150” Wide,

Dimensions are in inches (millimeters) unless otherwise noted. Figure 10. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide,

© 2002 - 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FSAL200 Rev. 1.7.0 10