FSA9285A ONSEMI | Alldatasheet

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© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA9285A • Rev. 1.3 FSA9285A — MCPC Compliant USB Port Multimedia Switch with Auto-Detection, 12 V VBUS FSA9285A — MCPC-Compliant, USB-Port, Multimedia Switch with Auto-Detection, 12 V VBUS

Features

Switch Type Audio, FS/HS-USB, Charging Switch Mechanism Programmable Switching with Available Interrupt Accessory Detection Headsets with MIC and Send/End USB Data Cable USB Chargers (Car, CDP, DCP) USB On-The-Go (OTG) MCPC Specification Compliant Programmable Modes USB FS and HS 2.0 Compliant USB Charging Battery Charging 1.2 Compliant Integrated FET, Charger Detect, OCP (1.45 A), OVP (6.5 V - 14.0 V) Audio Left, Right, MIC (Negative Swing) Built-in Termination Resistors for Audio Pop Reduction VBAT 2.7 to 4.4 V Programmability I2C ESD 15 kV IEC 61000-4-2 Air Gap Package 20-Lead, WLCSP (2.010 x 1.672 x 0.625 mm, 0.4 mm Pitch)

Description

The FSA9285A is a high-performance multimedia switc h featuring automatic switching and accessory detection for a USB port. The FSA9285A allows sharing of a common USB p ort to pass audio and USB data while simultaneously charging. In addition, the FSA9285A integrates detection of accessories such as headphones, headsets Mobile Computing Promotion Consortium (MCPC) with MIC and Send/End, car chargers, USB chargers, USB On-The-Go (OTG), and Accessory Charging Adapters (ACA) to use a common USB connector. The FSA9285A can be programmed for manual or automatic switching of USB data paths based on the accessory detected . With an integrated 14 V over-voltage and 1.45 A over-current protected FET, the FSA9285A integrates common USB protection functions for VBUS.

Applications

 Mobile Phones, Portable Media Players

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA9285A • Rev. 1.3 3 FSA9285A— MCPC Compliant USB Port Multimedia Switch with Auto-Detection, 12 V VBUS Pin Descriptions Name Pin # Type Default State Description USB Interface DP_HOST1 D1 Signal Path Open D+ signal switch path, dedicated USB port to be connected to the resident USB transceiver on the phone DM_HOST1 C1 Signal Path Open D- signal switch path, dedicated USB port to be connected to the resident USB transceiver on the phone DP_HOST2 A2 Signal Path Open D+ signal switch path, dedicated USB port to be connected to the resident USB transceiver on the phone DM_HOST2 A3 Signal Path Open D- signal switch path, dedicated USB port to be connected to the resident USB transceiver on the phone VBUS_IN E4 Power Path N/A Input voltage supply pin to be connected to the VBUS pin of the USB connector VBUS_OUT D4 Power Path N/A Output voltage supply pin to be connected to the source voltage pin on the charger IC CHG_DETB C2 Open-Drain Output Hi-Z Open-drain active LOW output, used to signal the charger IC that a charger has been attached Audio Interface Audio_R D2 Signal Path Open Right audio channel switch path from mobile phone audio CODEC Audio_L D3 Signal Path Open Left audio channel switch path from mobile phone audio CODEC MIC B2 Signal Path Open Connected to the mobile phone audio CODEC MIC input pin to complete the MIC switch path Connector Interface ID_CON E1 Signal Path Open Connected to the USB connector ID pin and used for detecting accessories or button presses DP_CON E2 Signal Path Open Connected to the USB connector D+ pin; depending on the signaling mode, can be switched to DP_HOST1, DP_HOST2, or Audio_R pins DM_CON E3 Signal Path Open Connected to the USB connector D- pin; depending on the signaling mode, can switched to DM_HOST1, DM_HOST2, or Audio_L pins Power Interface VBAT A4 Power Path N/A Input voltage supply pin to be connected to the mobile phone battery output or to an internal regulator on the phone VDDIO B4 Power Path N/A Baseband processor interface I/O supply pin GND1 B1 Ground N/A Ground GND A1 Ground N/A Ground I2C Interface I2C_SCL C3 Input Hi-Z I2C serial clock signal to be connected to the phone-based I2C master I2C_SDA B3 Open-Drain I/O Hi-Z I2C serial data signal to be connected to the phone-based I2C master INTB C4 CMOS Output HIGH Interrupt active LOW output used to prompt the phone baseband processor to read the I2C register bits, indicates a change in ID_CON or VBUS_IN pin status or accessories’ attach status

  1. Power-Up Initialization and Reset

VBUS_IN and VBAT are shown in Table 2. As shown in Table 2, VBAT is used as the primary power supply. I2C interface and interrupt processing within the FSA9285A. state and is able to detect USB accessories and all chargers. default values shown in Table 6 (see Section 4 - Configuration). Table 2. Power States Summary

  1. V DDIO is expected to be the same supply used by the baseband I/Os.
  2. This is not a typical state. Both V BAT and VDDIO are typically provided from the same regulator.

The FSA9285A must be configured for operation upon reset.

  1. The Interrupt Mask bit is set and must be cleared for the

FSA9285A to interrupt the host processor.

  1. Upon hardware reset, the USB Path DP_HOST1 /

switches may be opened using I2C commands.

  1. If MIC Mode is going to be used, it is recommended that

MIC_OVP_EN bit be set to 1 at reset.

  1. To enable manual configuration of the USB switches, the
  2. Performing a software reset sets all I 2C Register Map

default on a hardware reset.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA9285A • Rev. 1.3 6 FSA9285A— MCPC Compliant USB Port Multimedia Switch with Auto-Detection, 12 V VBUS 5. Interrupt Operation The baseband processor recognizes interrupt signals by observing the INTB signal, which is active LOW. Interrupts are masked upon reset via the INT Mask register bit (bit 0 of Control register, address 02h in Table 6 of the I2C register map) and INTB pin defaults HIGH. After the INT Mask bit is cleared by the baseband processor, the INTB pin is generally driven HIGH (INTB is not an open-drain output) in preparation f or a future interrupt. The INTB remains HIGH until the INTB mask is cleared. If the Interrupt Mask bit in the I 2C Control register is written LOW when an interruptible event occurs, INTB transitions LOW and returns HIGH when the processor reads the Interrupt register at addresses 03h. 6. Analog Switch Descriptions The FSA9285A has a three-port data switch, providing routi ng capability to two data ports and one audio port. The two d ata switches are high bandwidth to provide high-speed USB 2.0 “eye” compliance. These switches also operate full-swing for full-speed USB and UART signals up to 4.4 V. The hi gh-performance negative-swing-capable audio switch utilizes a termination resistor for audio pop reduction. The audio configuration also provides for routing a microphone signal from a headset. The MIC signals can be routed to either the V BUS_IN pin for stereo audio configurations or the DP_CON pin for mono audio configurations that also allow simultaneous charging over the VBUS line. 7. Accessory Detection In Standby Mode, after power-up or reset, the FSA9285A monitors the V BUS_IN and ID_CON pins for any connectivity using very low power ( see “Battery Supply Standby Mode Current” in the Switch Path DC Electrical Characteristics section). To minimize standby power, many functional blocks are powered down until an accessory attach is detected. The VBUS_IN detection recognizes if the voltage on V BUS_IN is within the valid range (>4.0 V). For resistance to GND on the ID_CON pin, the FSA9285A measures voltage with an injected current to determine this resistance. All accessories attached or detached are reported to the processor via the Interrupt register. Any changes of resistance on the ID_CON pin are reported as a Resistor_Change interrupt. Additional information about the accessory is reported in the Device Type, Resistor Code, and Status registers. For USB accessories without an ID_CON resistance, a V BUS_Valid Change interrupt is reported to signal an attach or detach condition. Status of V BUS_Valid and ID_CON resistance is always available after any interrupt. The USB detection flow is show in Figure 5. Note that the INTB Mask bit in the Control register must be cleared after a reset or power-up before interrupts can be signaled by the FSA9285A . Individual Interrupt Masks bits can be enabled by writing the Interrupt Mask register (see Table 6). ID_CON resistor detection is accomplished in a little more tha n three times the “Resistor Detection Time, ” where Resistor Detection Time bits are programmable in the Timing Set register. The FSA9285A is designed to allow up to 1 nF capacitance on the ID_CON pin. ID_CON is short-circuit protected from a faulty resistor or an accidental short where the current is limited to 5 mA sourced by the FSA9285A. The detection of a V BUS_IN goes through the USB detection flow only once. V BUS_IN must be removed before the USB detection state machine reverts to its initial state. After an initial attach, the FSA9285A continuously monitors t he ID pin for changes and reports those changes to the baseban d processor. To provide the fastest response for changes in button checking after initial attach, the FSA9285A indicates a change in ID_CON resistor after two samples are taken instead of the three consecutive samples taken on initial attach. To save power, the resistor detection block can be disabled aft er an initial attach with the ID_DIS bit in the Control register. The resistor detection block is normally disabled when no ID_ CON resistance is present (ID_CON floating) to save power. The condition of ID_FLOAT continues to be monitored regardless o f the ID_DIS setting. Whenever a resistance is measured on ID_CON, the USB discovery state machine halts after completion of its curre nt state and the ID_CON state machine continues for accessory detection. The only exception is when an ACA RID-A accessory is detected. In this case, the USB discovery state machine i s used to differentiate between a docking station and a powe red A-device attached to a docking station (per USB Battery Charging Specification 1.2). If the EN_MAN_SW bit is set on attach, FSA9285A configures the switches to the state in the MANUAL SW register. Upon the removal of any accessory, the FSA9285A detects and indicates a change in ID_CON resistance (regardless of ID_DIS bit setting), a removal of V BUS_IN, or both. The FSA9285A automatically opens all switches (and V BUS FET) on detach (ID_FLOAT and VBUS not valid), even if the FSA9285A is set to Manual Switching Mode. For the weak battery case, the FSA9285A needs to be in Automatic Switching Mode. Should the processor NOT be able to respond to INTB, FSA9285A must be placed in Automatic Switching Mode explicitly or V DDIO must be removed, resetting the FSA9285A state to its default values. Note: If the FSA9285A is to be used in automatic switching mode (EN_MAN_SW = 0) then the Manual SW register must be configured for all switches OPEN).

Figure 5. Accessory Discovery State Machine Flow Diagram

  1. Figure 5 illustrates operation with a valid V DDIO supply voltage. Figure 5 does not illustrate Dead Battery Provision (DBP) See

Table 3. ID_CON Resistor Identification

  1. The resistor code values are reported in the Resistor Code reg ister whenever a valid resistor code value changes.
  2. See Table 4 for details, additional requirements may be applicable for detection.
  3. Resistance 970 kΩ status bit /ID_FLOAT=0.
  1. USB Port and Charger Detection

in Table 4. VBUS must be present to detect these accessories. Manual Switch register when EN_MAN_SW is enabled. sourcing greater than 100 mA. Table 4. ID_CON and V BUS Detection for USB and Car Kit Devices

  1. The resistor code values are reported in the Resistor Code regis ter, independent of the state of USB switches or VBUS_IN.
  2. In Table 4, switches auto-close and CHG_DETB are asserted only if V BUS_VALID.
  3. The FSA9285A follows the Battery Charging 1.2 specification, whic h uses DP_CON and DM_CON to determine the USB

accessory attached. Refer to Battery Charging 1.2 Specification for details. on the V BUS FET after BC1.2 charger detection is complete. at the same time as the VBUS FET. (14h); VBUS must be valid to do so.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA9285A • Rev. 1.3 10 FSA9285A— MCPC Compliant USB Port Multimedia Switch with Auto-Detection, 12 V VBUS 10. Over-Voltage Protection (OVP) and Over-Current Protection (OCP) When V BUS_IN is less than nominally 6.5 V, the FSA9285A allows the VBUS_IN supply to enter the chip-power select voltage regulator block. For V BUS_IN greater than nominally 6.5 V, the input is disconnected, protecting the FSA9285A from excess voltage. Upon entering Shutdown Mode, the OVP bit in the Interrupt register is set HIGH (to reflect a change in OVP state) and an interrupt is sent to the baseband. The OVP Status register is also written HIGH to indicate that an OVP conditio n is present. In Shutdown Mode, the FSA9285A continually monitors V BUS and exits Shutdown Mode when V BUS drops to below 6.5 V or it senses an accessory detach. Upon exitin g an OVP condition, another OVP interrupt is triggered (reflecting a change in OVP state) and the OVP status bit is cleared (indicating an OVP condition is not present). The Over-Current Protection (OCP) feature limits current through the charger FET to nominally 1.45 A. OCP is only implemented when V BUS_IN is provided by the attached accessory. The FSA9285A senses an over-current event, opens (turns off) the V BUS FET, and reports this to the baseband by asserting the OCP bit (to reflect a change in OCP state) in the Interrupt register. When in an OCP state, the OCP status bit is written HIGH. While the OCP condition is present , the FSA9285A continually monitors the V BUS current and exits Shutdown Mode when the V BUS current drops below nominally 1.45 A or it senses an accessory detach. Upon exiting OCP state, the OCP Interrupt bit is again written HIGH, indicating a change in OCP state and the OCP Status bit is written LOW, indicating an OCP state is not present. 11. Audio Accessory Detection After an audio device is attached and a change in ID_CON resistance is detected (if ID_DIS=0), the FSA9285A asserts an interrupt and the baseband processor can read the Resistor Code register to determine the ID_CON resistance change to detect if a key, such as MCPC SEND / END, was pressed. For powered audio accessories with V BUS present, the FSA9285A detects when V BUS is valid and interrupts the baseband processor. The baseband processor must manua lly control the FSA9285A switches for proper functionality. MIC can be switched to either V BUS or DP_CON through the Manual SW register, allowing more flexibility.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA9285A • Rev. 1.3 11 FSA9285A— MCPC Compliant USB Port Multimedia Switch with Auto-Detection, 12 V VBUS 12. Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may a ffect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VBAT/VDDIO Supply Voltage from Battery / Baseband -0.5 6.0 V VBUS_IN Supply Voltage from Micro-USB Connector -0.5 28.0 V VSW Switch I/O Voltage USB -1.0 6.0 V Stereo/Mono Audio Path Active -2.0 6.0 All Other Channels -0.5 6.0 IIK Input Clamp Diode Current -50 mA ICHG Charger Detect CHG_DETB Pin Current Sink Capability 30 mA ISW Switch I/O Current (Continuous) USB 50 mA Audio 60 All Other Channels 50 ISWPEAK Peak Switch Current (Pulsed at 1 ms Duration, <10% Duty Cycle) USB 150 mA Audio 150 mA Charger FET 2 A All Other Channels 150 mA TSTG Storage Temperature Range -65 +150 C TJ Maximum Junction Temperature +150 C TL Lead Temperature (Soldering, 10 Seconds) +260 C ESD IEC 61000-4-2 System Level USB Connector Pins (DP_CON, DM_CON, VBUS_IN, ID_CON) to GND Air Gap 15000 V Contact 8000 Human Body Model, JEDEC JESD22-A114 All Pins 5000 Charged Device Model, JEDEC JESD22-C101 All Pins 1500 13. Recommended Operating Conditions The Recommended Operating Conditions table defines the con ditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommen d exceedin g them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit VBAT Battery Supply Voltage 2.7 3.8 4.4 V VBAT_TH Battery Supply Voltage Threshold for Weak / Dead Battery 2.7 3.0 3.3 V VBUS_IN Supply Voltage from VBUS_IN Pin 4.0 14.0(10) V VDDIO Processor Supply Voltage 1.7 3.6 V VSW Switch I/O Voltage USB Path Active 0 4.4 V Audio Path Active -1.5 3.0 All Other Pins 0 5.0 IDCAP Capacitive Load on ID_CON Pin for Reliable Accessory Detection 1.0 nF TA Operating Temperature -40 +85 ºC Note: 10. Maximum operating condition set by design.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA9285A • Rev. 1.3 12 FSA9285A— MCPC Compliant USB Port Multimedia Switch with Auto-Detection, 12 V VBUS 14. Switch Path DC Electrical Characteristics All typical values are at TA=25°C unless otherwise specified. Symbol Parameter VBAT (V) Condition TA = -40 to +85°C Unit Min. Typ. Max. Host Interface Pins (INTB, CHG-DETB) VOH Output High Voltage(11) 3.0 to 4.4 IOH=2 mA 0.7 x VDDIO V VOL Output Low Voltage 3.0 to 4.4 IOL=8 mA 0.4 V I2C Interface Pins – Fast Mode (I2C_SDA, I2C_SCL) VIL Low-Level Input Voltage 3.0 to 4.4 0.3 x VDDIO V VIH High-Level Input Voltage 3.0 to 4.4 0.7 x VDDIO V II2C Input Current of I2C_SDA and I2C_SCL Pins, Input Voltage 0.26 V to 2.34 V 3.0 to 4.4 -10 10 µA Switch Off Characteristics IOFF Power-Off Leakage Current 0 All Data Ports Except Audio & MIC, VSW=4.4 V 10 µA INO(OFF) Off Leakage Current 4.4 All Ports Except Audio & MIC, I/O Pins=0.3 V,

4.1 V, or Floating

-0.100 0.001 0.100 µA IIDSHRT Short-Circuit Current 3.0 to 4.4 Current Limit if ID_CON=0 5 mA USB Switch (DP_HOSTn, DM_HOSTn) ON Paths RON USB Switch Paths On Resistance(12,13) 3.0 to 4.4 VD+/D-=0, 0.4 V, ION=8 mA 8 10 Ω VD+/D-=0, 3.6 V, ION=8 mA 11 17 Ω Charging FET ON Path VOVP Over-Voltage Protection (OVP) Threshold Voltage RON Charging FET On Resistance(12,13) 3.0 to 4.4 VBUS_IN=4.2 V-5.0 V, ION=1 A 200 mΩ IOCP Over-Current Protection (OCP) Threshold Current Continued on the following page…

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA9285A • Rev. 1.3 13 FSA9285A— MCPC Compliant USB Port Multimedia Switch with Auto-Detection, 12 V VBUS Switch Path DC Electrical Characteristics (Continued) All typical values are at TA=25°C unless otherwise specified. Symbol Parameter VBAT (V) VBUS(V) Condition TA = -40 to +85°C Unit Min. Typ. Max. Audio_R / Audio_L Switch ON Paths RON Audio Switch On Resistance(12,13) 3.0 to 4.4 VL/R=-0.8 V, 0.8 V; ION=30 mA; f=0-470 kHz 3.5 Ω VL/R=-1.5 V, 1.5 V; ION=30 mA, f=0-470 kHz 4.0 RFLAT Audio RON Flatness(12,14) 3.0 to 4.4 VL/R=-0.8 V, 0.8 V; ION=30 mA, f=0-470 kHz 0.1 Ω VL/R=-1.5 V, 1.5 V; ION=30 mA, f=0-470 kHz 0.2 RTERM Internal Termination Resistors 1.5 kΩ MIC Switch ON Paths RON MIC Path ON Resistance(12,13) 3.0 to 4.4 MIC Connected to VBUS_IN, VSW=0, 2.8 V; ION=30 mA Ω MIC Connected to DP_CON, VSW=0, 2.8 V; ION=30 mA MICOVP Over-Voltage Protection (OVP) Threshold Voltage with MIC on VBUS_IN (15) MIC Connected to VBUS_IN Entering OVP 2.80 3.35 V Total Current Consumption(17) IBAT Battery Supply Standby Mode Current No Accessory Attached (ID_CON Floating) 3.0 to 4.4 Floating VBUS Floating 10 15 µA Average Battery Supply Standby Mode Current with Accessory Attached (ID_CON Not Floating)

0.0 ID_DIS=1 35 50

5.0 ID_DIS=1 100(16) 150(16)

Notes: 11. Does not apply to the CHG_DETB pin because it is open drain. 12. Limits based on Electrical Characterization data. 13. On resistance is the voltage drop between the two terminals at the indicated current through the switch. 14. Flatness is the difference between the maximum and minimum val ues of on resistance over the specified range of conditions. 15. The MIC bias applied should not exceed 2.8 V. 16. V DDIO of either 0 V or in the valid range of 1.7 V to 3.6 V. 17. Typically the battery charg es from VBUS.

  1. I2C AC Electrical Characteristics
  2. C b equals the total capacitance of one BUS line in pf. If mixed with high-speed devices; faster fall times are allowed, according

to the I2C Bus specification.

  1. A fast-mode I 2C Bus® device can be used in a Standard-Mode I2C-Bus system, but the requirement that tSU;DAT ≥ 250 ns must

the SCL line is released (according to the Standard-Mode I2C Bus specification). Figure 6. Definition of Timing for Full-Speed Mode Devices on the I 2C Bus® Table 5. I 2C Slave Address

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA9285A • Rev. 1.3 15 FSA9285A— MCPC Compliant USB Port Multimedia Switch with Auto-Detection, 12 V VBUS 17. Switch Path AC Electrical Characteristics All typical values are for VBAT=3.8 V at TA=25ºC unless otherwise specified. Symbol Parameter Conditions TA = -40 to +85°C Unit Min. Typ. Max. Xtalk Active Channel Crosstalk DP_CON to DM_CON Audio Mode f=20 kHz, RT=32 Ω, CL=0 pF -90 dB USB Mode f=1 MHz, RT=50 Ω, CL=0 pF -60 OIRR Off Isolation Audio Mode f=20 kHz, RT=32 Ω, CL=0 pF -100 dB USB Mode f=1 MHz, RT=50 Ω, CL=0 pF -60 PSRR Power Supply Rejection Ratio, MIC on VBUS_IN Power Supply Noise 300 MvPP, f=217 Hz Sine Wave -100 dB THD Total Harmonic Distortion (Audio Path) 20 Hz to 20 kHz, RL=32/16 Ω, Input Signal Range -1.5 V, +1.5 V 0.07 % tSK(P) Skew of Opposite Transitions of the Same Output (USB Mode) tr=tf=750 ps (10-90%) at 240 MHz, CL=0 pF, RL=50 Ω 35 ps tI2CRST Time When I2C_SDA and I2C_SCL Both LOW to Cause Reset See Figure 7 30 ms tSDPDET Time from VBUS_IN Valid to VBUS_OUT Valid with Charger FET Closed and USB Switches Closed for USB Standard Downstream Port See Figure 9 120 ms tCHGOUT Time from VBUS_IN Valid to VBUS_OUT Valid with Charger FET Closed for Both USB Charging Ports (CDP and DCP) See Figure 10 160 ms tCARKIT Time from VBUS_IN Valid to Car Kit Type-1 or Type-2 Charger Detected See Figure 11 140 ms tIDDET Time from ID_CON Not Floating to INTB LOW to Signal Accessory Attached that is ID_CON Resistance-Based Only (VBUS_IN Not Valid, Default timing configuration) See Figure 12 150 ms tBC11 Timeout for Data Contact During DCD Check 300 600 900 ms

Table 6. I 2C Register Map Table 7. Device ID Table 8. Control 7 DCDTimeout_EN 1 1: DCD timeout is enabled.

6 RESETB 1

Manual SW (13H), and Manual CHG_CTRL(14H). Note: This bit is momentarily set to 0 on a write. It immediately reverts to 1.

5 ID_DIS 1

1: ID_CON resistor detection is disabled after a resistance is detected on ID_CON. 0: ID_CON resistor detection is enabled after a resistance is detected on ID_CON. Note: The FSA9285A continues to monitor for an ID_FLOAT condition. 4 EN_MAN_SW 1 1: Configure switches based on Manual SW register settings.

0: Use only defined automatic switch settings. defaulted via a VDDIO reset for the dead battery case to operate properly.

0 INT Mask 1

Table 9. Interrupt

7 Do Not Use 1 N/A

6 OCP

Change 1 1: OCP state changed. 0: OCP state has not changed.

5 OVP

Change 1 1: OVP state changed. 0: OVP state has not changed.

4 MIC_OVP

Change 1 1: MIC OVP state changed. 0: MIC OVP state not changed.

3 Resistor Code

1: Resistor Code value changed. 0: Resistor Code value has not changed. from a non-zero Resistor Code to a Resistor Code=zero (ID_CON floating).

2 VBUS_Valid

Change 1 1: VBUS_Valid state changed. 0: VBUS_Valid state has not changed. 1 BC1.2_Complete 1 1: BC1.2 charger detection complete. 0: No change in BC1.2 charger detection status.

0 Do Not Use 1 N/A

Table 10. Interrupt Mask 6 OCP 1 1: Mask OCP state-change interrupt. 0: Do not mask OCP state-change interrupt. 5 OVP 1 1: Mask OVP state-change interrupt. 0: Do not mask OVP state-change interrupt. 4 MIC_OVP 1 1: Mask MIC_OVP state-change interrupt. 0: Do not mask MIC_OVP state-change interrupt.

Change 1 1: Mask Resistor Code value-change interrupt. 0: Do not mask Resistor Code value-change interrupt. 2 VBUS_Valid 1 1: Mask VBUS_Valid state-change interrupt. 0: Do not mask VBUS_Valid state-change interrupt. 1 BC1.2_Complete 1 1: Mask BC1.2_complete interrupt. 0: Do not mask BC1.2_complete interrupt. Table 11. Resistor Code 4:0 Resistor Code 5 Resistor code value read from ID_CON (see Table 3 Resistor Identification). Table 12. Timing Set Table 13. Timing Table for Timing Set Register

Table 14. Status 7 ID_SHORT 1 1: ID_SHORT detected. 6 OCP 1 1: VBUS in over-current state. 0: VBUS not in over-current state. 5 OVP 1 1: VBUS in over-voltage state. 0: VBUS not in over-voltage state.

4 MIC_OVP 1 1: MIC in over-voltage state

3 /ID_FLOAT 1 1: ID_CON not floating (resistor detected). 0: ID_CON floating (no resistor detected). 2 VBUS_Valid 1 1: VBUS is valid. 0 DCD 1 1: Data contact detected on last charger-detect sequence. 0: No data contact detected on last charger-detect sequence. Table 15. Device Type 5 Dock 1 1: Charging dock detected. 0: Charging dock not detected. 2 DCP 1 1: USB dedicated charging port (DCP) charger detected. 0: USB dedicated charging port (DCP) charger not detected. 1 CDP 1 1: USB charging downstream port (CDP) charger detected. 0: USB charging downstream port (CDP) charger not detected. 0 SDP 1 1: USB standard downstream port (SDP) detected. 0: USB standard downstream port (SDP) not detected.

Table 16. DAC SAR Table 17. Manual SW (22) 001: DM_CON connected to DM_HOST1 of USB port. 010: DM_CON connected to Audio_L. 011: DM_CON connected to DM_HOST2 of USB port. 001: DP_CON connected to DP_HOST1 of USB port. 010: DP_CON connected to Audio_R. 011: DP_CON connected to DP_HOST2 of USB port. 100: DP_CON connected to MIC. 10: VBUS_IN connected to MIC.

  1. When changing manual switch configurations on a single attach, the accessory must pass through an “Open All Switches” state

between configurations. Manual Modes require the EN_MAN_SW Manual Mode bit in the Control register (02H) to be set.

  1. V BUS_IN must be valid for the charger FET to close in manual FET switching.

Table 18. Manual CHG_CTRL

4 Assert

Note: EN_MAN_SW is not required for this bit to take effect.

3 MIC_OVP_EN 1

1: Enable MIC_OVP (only use when MIC is connected to VBUS). Note: EN_MAN_SW is not required for this bit to take effect.

2 Assert_D+ 1

0: Do not force 0.6 V on DP_CON. Note: EN_MAN_SW is not required for this bit to take effect, VBUS must be valid.

Table 19. Applications1 Table 20. Applications2

Figure 13. Reference Schematic

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA9285A • Rev. 1.3 25 FSA9285A— MCPC Compliant USB Port Multimedia Switch with Auto-Detection, 12 V VBUS 21. Layout Guidelines PCB Layout Guidelines for High-Speed USB Signal Integrity 1. Place the FSA9285A as close to the USB controller as possible. Shorter traces mean less loss, less chance of picking up stray noise, and less radiated EMI. a) Keep the distance between the USB controller and the device less than 25.4 mm (or one inch <1 in). b) For best results, keep this distance <18 mm. This keeps it less than one quarter (¼) of the transmission electrical length. 2. Use an impedance calculator to ensure 90 Ω differential impedance for DP_COM/DM_CON lines. 3. Select the best transmission line for the application. a) For example, for a densely populated board, select an edge-coupled differential stripline. 4. Minimize the use of vias and keep HS USB lines on same plane in the stack. a) Vias are an interruption in the impedance of the transmission line and should be avoided. b) Try to avoid routing schemes that generally force the use of at least two vias: one on each end to get the signal to and from the surface. 5. Cross lines, only if necessary, orthogonally to avoid noise coupling (traces running in parallel couple). 6. If possible, separate HS USB lines with GND to improve isolation. a) Avoid routing GND, power, or components close to the transmission lines to avoid impedance discontinuities. 7. Match transmission line pairs as much as possible to improve skew performance. 8. Avoid sharp bends in PCB traces; a chamfer or rounding is generally preferred. 9. Place decoupling for power pins as close to the device as possible. a) Use low-ESR capacitors for decoupling if possible. b) If needed, a tuned PI filter should be used to negate the effects of switching power supplies and other noise sources. Layout for Global System for Mobile Communication (GSM) Time Division Multiple Channel (TDMA) Buzz Reduction There are two possible mechanisms for TDMA/GSM noise to negatively impact FSA9285A device’s performance. The first is the result of large current draw by the phone transmitter during active signaling when the transmitter is at full or almost f ull power. With the phone transmitter dumping large amounts of current in the phone GND plane; it is possible for there to be temporary voltage excursions in the GND plane if not properly designed. This noise can be coupled back up through the GND plane into the FSA9285A device and, although the FSA9285A has very good isolation; if the GND noise amplitude is la rge enough, it can result in noise coupling to the VBUS_In / MIC pin. The second path for GSM noise is through electromagnetic coupling onto the signal lines themselves.

Ordering Information

Part Number Operating Temperature Range Top Mark Package FSA9285AUCX -40 to +85°C NQ 20-Lead, WLCSP (2.010 x 1.672 x 0.625 mm, 0.4 mm Pitch) Product-Specific Package Dimensions Product D E X Y FSA9285AUCX 2.010 mm 1.672 mm 0.236 mm 0.205 mm

A B C D E SEATING PLANE 20X C

0.005 C A B

F E D B A 0.625 0.547 0.06 C

0.05 C E

D F NOTES: A. NO JEDEC REGISTRATION APPLIES. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCE PER ASMEY14.5M, 2009. D. DATUM C IS DEFINED BY THE SPHERICAL CROWNS OF THE BALLS. E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS 0,&5216 0,&5216 F. FOR DIMENSIONS D, E, X, AND Y SEE PRODUCT DATASHEET. G. DRAWING FILNAME: MKT-UC020AArev4. 0.03 C 0.03 C 0.40 1.20 0.40 1.60 RECOMMENDED LAND PATTERN (NSMD TYPE) Cu Pad ‘6ROGHU Mask Opening 0.40 1.20 0.401.60 A1‘ Cu Pad ‘6ROGHU Mask Opening 0.40 1.20 option 1 option 2

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