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© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA880 / FSA881 • Rev. 1.0.7 FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection FSA880 / FSA881 – USB Port 2:1 Switch with Accessory and Charger Detection
Features
Switch Type 2:1 USB Switch Mechanism Automatic switching with Available Interrupt Accessory Detection USB Data Cable Chargers (CDP, DCP, Travel Adapter, Car Kit-CEA -936-A) Factory-Mode Cables USB FS and HS 2.0 Compliant USB Charging Battery Charging 1.1 Compliant Charger Detect, DCD, OVT (28 V) UART RxD and TxD VBAT 3.0 to 4.4 V Programmability I2C ESD 15kV IEC 61000-4-2 Air Gap Operating Temperature -40°C to 85°C Package 16-Lead UMLP 1.8x2.6x0.55 mm, 0.4 mm Pitch JIG Option FSA880 – Active LOW FSA881 – Active HIGH FSA881UMX
Description
The FSA88x is a high -performance switch featuring automatic switching and accessory detection for a USB port. The FSA88x allows sharing of a common USB port to pass USB data, as well as factory programmability. In addition, the FSA88x integrates accessory detection of devices such as USB chargers and factory data cables. The FSA88x can be programmed for manual switching or automatic switching of data paths. VBUS_IN has 28 V over-voltage tolerance. The difference between the FSA880 and the FSA881 is that FSA880 JIG output is an open-drain, active-LOW output, while FSA881 JIG is an active-HIGH, CMOS output.
Applications
Cellular Phones, Smart Phones MP3 and PMP Related Resources FSA8 80 / FSA881 D emonstration Board Typical Application Figure 1. Mobile Phone Example
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA880 / FSA881 • Re v. 1.0.7 2 FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection
Ordering Information
Part Number Operating Temperature Range Top Mark Package FSA880UMX - 40 to +85°C KU 16-Lead, Ultrathin Molded Leadless Package (UMLP), 1.8 mm x 2.6 mm x 0.55 mm, 0.4 mm Pitch FSA881UMX - 40 to +85°C KX 16-Lead, Ultrathin Molded Leadless Package (UMLP), 1.8 mm x 2.6 mm x 0.55 mm, 0.4 mm Pitch Block Diagram Figure 2. Block Diagram
Figure 3. Pin Assignment (Through View)
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA880 / FSA881 • Re v. 1.0.7 4 FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection Pin Descriptions Name Pin # T ype Default State D escription USB /UART Interface DP_HOST 2 Signal Path Open D+ signal switch path, dedicated USB port to be connected to the resident USB / UART on the phone. Default port for all USB accessories and USB factory modes. DM_HOST 1 Signal Path Open D- signal switch path, dedicated USB port to be connected to the resident USB / UART on the phone. Default port for all USB accessories and USB factory modes. VBUS_IN 13 Input N/A Input voltage supply pin to be connected to the VBUS pin of the USB connector USB /UART Interface 1 DM _HOST 1 3 Signal Path Open D- signal switch path, dedicated USB port to be connected to the secondary resident USB / UART on the phone. Default port for UART factory modes. DP _HOST 1 4 Signal Path Open D + signal switch path, dedicated USB port to be connected to the secondary resident USB / UART on the phone. Default port for UART factory modes. Connector Interface GND 12 Ground N/A Ground ID_CON 16 Signal Path Open Connected to the USB connector ID pin and used for detecting accessories DP_CON 15 Signal Path Open Connected to the USB connector D+ pin; depending on the signaling mode, this pin can be switched to DP_HOST or RxD_HOST pins. DM_CON 14 Signal Path Open Connected to the USB connector D- pin; depending on the signaling mode, this pin can switched to DM_HOST or TxD_HOST pins. Power Interface VDDIO 8 Power N/A Input baseband interface I/O supply pin VBAT 5 Power N/A Input voltage supply pin to be connected to the mobile phone battery output or to an internal regulator on the phone Factory Interface JIG 7 FSA880: Open -Drain Output FSA881: CMOS Output FSA880:Hi-Z FSA881: LOW Output control signal and used by the processor for factory test modes FSA880: Active LOW open-drain output FSA881: Active HIGH CMOS output BOOT 6 CMOS Ou tput LOW Output control signal and used by the processor for factory test modes I2C Interface I2C_SCL 10 Input Hi-Z I 2C serial clock signal to be connected to the phone-based I2C master I2C_SDA 11 Open -Drain I/O Hi-Z I 2C serial data signal to be connected to the phone-based I2C master INTB 9 CMOS Output LOW Interrupt active LOW output used to prompt the phone baseband processor to read the I2C register bits, indicate a change in ID_CON pin status or accessories’ attach status Note: 1. LOW = VOL or VIL; H IGH = VOH or VIH.
automatic switching of data paths. USB eye compliance test with ample margin. references to more detailed information. Figure 4. Basic Operation Flow
correct operation. The main power is provided by VBAT only. VDDIO is only used for I2C interface and interrupt processing. Table 1. Power States Summary
- V DDIO is expected to be the same supply used by the baseband I/Os.
- Typically VDDIO is only present when VBAT is valid.
VBUS_IN and / or ID_CON pins. Reset bit in the Register (1BH).
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA880 / FSA881 • Re v. 1.0.7 8 FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection 5. Detection The FSA88x monitors both VBUS_IN and ID_CON to detect accessories. The ID_CON detection is a “resistive detection” that reads the resistance to GND on the ID_CON pin to determine the accessory attached. Table 3 shows the assignment of accessories based on resistor values. FSA88x can also detect accessories with ID resistances outside the specified ranges. The FSA88x detects these unknown accessories in the same manner as the defined accessories and interrupts the baseband processor and provides the correct ADC value, as shown in Table 3. Table 3. ID_CON Accessory Detection 4 3 2 1 0 Min. Target Max. 1 0 1 0 1 117.4 kΩ 121 kΩ 124.6 kΩ Unknown Accessory 1 0 1 1 0 145.5 kΩ 150 kΩ 1 54.5 kΩ Unknown Accessory 1 0 1 1 1 176.4 kΩ 200 kΩ(4) 206 kΩ Travel Adapter (TA) or Car Kit Type 1 Charger 1 1 0 0 0 247.3 kΩ 255 kΩ 262.7 kΩ Factory Mode Boot OFF-USB 1 1 0 0 1 291.9 kΩ 301 kΩ 310.1 kΩ Factory Mode Boot ON-USB 1 1 0 1 0 3 54 kΩ 365 kΩ 3 75.9 kΩ Unknown Accessory 1 1 0 1 1 428.7 kΩ 442 kΩ(4) 455.3 kΩ Unknown Accessory 1 1 1 0 0 507.3 kΩ 523 kΩ 538.7 kΩ Factory Mode Boot OFF-UART 1 1 1 0 1 600.4 kΩ 619 kΩ 637.6 kΩ Factory Mode Boot ON-UART 1 1 1 1 0 750 kΩ 1000 kΩ 1030 kΩ Unknown Accessory Not ‘h1F or any code above 3 M Ω None of the above ranges Unknown Accessory Note: 4. These accessories need VBUS to be valid in order to be detected since they are charger accessories. 5.1. Factory Cable Detection Factory modes are initiated with the attachment of special test hardware, called a “JIG box” for factory testing. The FSA88x automatically configures switch paths to any of the factory-mode accessories when the appropriate resistor is sensed on the ID_CON pin. A change of resistor on the ID_CON pin dynamically switches between factory modes and auto-configures the appropriate switch paths without detaching and attaching the cable. The different factory mode accessories with the associated resistor values (1% standard resistors) on the ID_CON pin and the JIG and BOOT logic states are listed in Table 4. The FSA88x allows both HS USB and FS USB in addition to UART signals to be passed on both ports with matched performance. This allows greater flexibility when designing with the FSA88x. JIG output signals when a factory mode accessory is plugged in and BOOT output signals the mobile phone to boot up. The switch paths for factory modes are shown in Table 4. Table 4. ID_CON Factory Cable Detection Figure 7 shows the operation of the detection algorithm.
Figure 7. Factory Cable Detection Flow Chart (FSA880)
The multiple types of USB 2.0 ports the FSA88x can detect are summarized in Table 5. Table 5. ID_CON and VBUS Detection Table for USB Devices
- The accessory type is reported in the Device Type 1 (0Ah) register for each valid accessory detected.
- The FSA88x follows the Battery Charging 1.1 specification, which uses DP_CON and DM_CON to determine the USB
accessory attached. Refer to Battery Charging 1.1 specification for further details.
- INTB is asserted LOW , indicating change in accessory
- Processor reads Interrupt 1 (03h) register to determine if
an attach or detach event was detected.
- Processor reads Status registers to determine the exact
CDP , or DCP accessory was detected. unknown accessory was detected.
baseband to configure the switches correctly. Figure 8. Switch Configurations Manual Switch 1 (13h): Configures the switches for DM_CON, and DP_CON. Manual Switch 2 (14h): Configures the BOOT, and JIG pins.
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA880 / FSA881 • Re v. 1.0.7 14 FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection 9. Product Specifications 9.1. Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VBAT Supply Voltage from Battery -0.5 6.0 V VBUS_IN Supply Voltage from USB Connector -0.5 28.0 V VSW Switch I/O Voltage USB -1.0 6.0 V UART -1.0 6.0 IIK Input Clamp Diode Current -50 mA ISW Switch I/O Current (Continuous) USB at TA=85°C 25 mA UART at TA=85°C 12 ISWPEAK Peak Switch Current (Pulsed at 1ms Duration, <10% Duty Cycle) 150 mA TSTG Storage Temperature Range -65 +150 °C TJ Maximum Junction Temperature +150 °C TL Lead Temperature (Soldering, 10 Seconds) +260 °C ESD IEC 61000-4-2 System ESD USB Connector Pins (DP_CON, DM_CON, VBUS_IN , ID_CON) to GND Air Gap 15 kV Contact 8 Human Body Model, JEDEC JESD22-A114 Al l Pins 4 Charged Device Model, JEDEC JESD22-C101 All Pins 2 9.2. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit VBAT Battery Supply Voltage 3.0 4.4 V VBUSIN V BUS_IN Voltage 4.0 5.5 V VDDIO Processor Supply Voltage 1.8 3.6 V VSW Switch I/O Voltage USB Path Active 0 3.6 V UART Path Active 0 3.6 IDCAP Capacitive Load on ID_CON Pin for Reliable Accessory Detection 1.0 nF TA Operating Temperature -40 +85 ºC
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA880 / FSA881 • Re v. 1.0.7 15 FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection 9.3. Switch Path DC Electrical Characteristics All typical values are at TA=25°C unless otherwise specified. Symbol Parameter V BAT (V) Conditions TA = -40 to +85°C Unit Min. Typ. Max. Host Interface Pins (BOOT, JIG, INTB) VOH Output High Voltage (FSA881 JIG Output) 3.0 to 4.4 IOH =-2 mA 0.8•VBAT V VOH Output High Voltage (just BOOT & INTB Outputs)(7) 3.0 to 4.4 IOH =-2 mA 0.7•VDDIO V VOL Output Low Voltage (INTB, JIG & BOOT Outputs) 3.0 to 4.4 IOL =3 mA 0.4 V I2C Interface Pins – Fast Mode (I2C_SDA, I2C_SCL) VIL Low -Level Input Voltage 3.0 to 4.4 0.3•VDDIO V VIH High-Level Input Voltage 3.0 to 4.4 0.7•VDDIO V VHYS Hysteresis of Schmitt Trigger Inputs 3.0 to 4.4 VDDIO >2 V 0.05 VDDIO V VDDIO <2 V 0.1 VDDIO V VOL 1 Low -Level Output Voltage at 3 mA Sink Current (Open-Drain) 3.0 to 4.4 VDDIO >2 V 0.4 VDDIO <2 V 0.2•VDDIO V II2C Input Current of I2C_SDA and I2C_SCL Pins 3.0 to 4.4 Input Voltage 0.26 V to
2.34 V -10 10 µA
Switch OFF Characteristics IOFF Powe r-Off Leakage Current 0 All Data Ports VSW =0 V to
4.4 V 10 µA
INO(OFF) Off Leakage Current 3.0 to 4.4 VBAT =4.4 V; I/O Pins=0.3 V, 4.1 V, or Floating -0.100 0.001 0.100 µA IIDSHRT Short- Circuit Current 3.0 to 4.4 Current Limit if ID_CON=0 V 1 mA USB Switch ON Path R ONUSB USB Switch On Resistance(8) 3.0 to 4.4 VD+/D-=0 V, 0.4 V; ION =8 mA 8 10 Ω VSW =0 V, 3.6 V; ION =30 mA 25 30 Ω VBUS Path VBUSIN V BUS_IN Valid Threshold 0.8 4.0 V R BUS V BUS_IN Resistance to GND 3 M Ω UART Switch ON Paths VASR_UART Analog Signal Range 3.0 to 4.4 0 3.6 V R ONUART UART Switch On Resistance 3.0 to 4.4 VD +/D-=0 V, 0.4 V; ION =8 mA 8 10 Ω VSW =0 V, 3.6 V; ION =30 mA 25 30 Total Current Consumption ICCSL Battery Supply Standby Mode Current (No Accessory Attached) 3.0 to 4.4 No Accessory, Static Current During Standby Mode 15 25 µA ICCSLWA Battery Supply Standby Mode Current with Accessory Attached(7) 3.0 to 4.4 With non-Factory M ode Accessories Attached 30 40 µA With Factory M ode Accessories Attached(9) 100 120 µA Notes: 7. Limits based on electrical characterization data. 8. On resistance is the voltage drop between the two terminals at the indicated current through the switch. 9. Factory mode accessories leave the detection circuitry active after attach to allow detection of ID changes without an attach.
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA880 / FSA881 • Re v. 1.0.7 16 FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection 9.4. Capacitance Symbol Parameter V BAT (V) Conditions TA = -40 to +85°C Unit Min. Typ. Max. C ON DP_CON, DM_CON On Capacitance 3.8 V BIAS=0.2 V, f=1 MHz 6 pF C I Capacitance for Each I/O Pin 3.8 5 pF 9.5. I 2C D C Electrical Characteristics Sym bol Parameter V BAT (V) Conditions TA = -40 to +85°C Unit Min. Max. Fast Mode (I2C_SDA, I2C_SCL) VIL Low -Level Input Voltage 3.0 to 4.4 0.3•VDDIO V VIH High-Level Input Voltage 3.0 to 4.4 0.7•VDDIO V Vhys Hysteresis of Schmitt Trigger Inputs 3 .0 to 4.4 VDDIO >2 V 0.05 VDDIO V VDDIO <2 V 0.1 VDDIO V VOL1 Low -Level Output Voltage at 3 mA Sink Current (Open-Drain) 3.0 to 4.4 VDDIO >2 V 0.4 VDDIO <2 V 0.2•VDDIO V Ii2C Input Current of I2C_SDA and I2C_SCL Pins 3.0 to 4.4 Input Voltage 0.26 V to 9.6. I 2C AC Electrical Characteristics Symbol Parameter Fast Mode Unit Min. Max. fSCL I2C_SCL Clock Frequency 0 400 kHz tHD;STA Hold Time (Repeated) START Condition 0.6 µs tLOW LOW Period of I2C_SCL Clock 1.3 µs tHIGH HIGH Period of I2C_SCL Clock 0.6 µs tSU;STA Set- up Time for Repeated START Condition 0.6 µs tHD;DAT Data Hold Time 0 0.9 µs tSU;DAT Data Set-up Time(10) 100 ns tr Rise Time of I2C_SDA and I2C_SCL Signals(10,11) 20+0.1Cb 300 ns tf Fall Time of I2C_SDA and I2C_SCL Signals(10,11) 20+0.1Cb 300 ns tSU;STO Set- up Time for STOP Condition 0.6 µs tBUF BUS -Free Time between STOP and START Conditions 1.3 µs tSP Pulse Width of Spikes that Must Be Suppressed by the Input Filter 0 50 ns Notes: 10. A fast-mode I2C Bus® device can be used in a Standard-Mode I2C Bus system, but the requirement tSU;DAT ≥ 250 ns must be met. This is automatically the case if the device does not stretch the LOW period of the I2C_SCL signal. If a device does stretch the LOW period of the I2C_SCL signal, it must output the next data bit to the I2C_SDA line tr_max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C bus specification) before the I2C_SCL line is released. 11. C b equals the total capacitance of one bus line in pF. If mixed with high-speed devices, faster fall times are allowed by the I2C specification.
Figure 15. Definition of Timing for Full-Speed Mode Devices on the I2C Bus® Table 6. I2C Slave Address All typical values are for VBAT =3.8 V at TA=25°C unless otherwise specified.
240 MHz, CL=0 pF, RL=50 Ω
Table 7. I2C Register Map
- Write “0” to undefined register bits.
- Values read from undefined register bits are not defined and invalid.
- Do not use undefined register locations.
Table 8. Device ID Table 9. Control
4 Switch Open 1 1: Open all switches
3 DoNotUse 1 N/A
2 Auto Config 1 1: Automatic switching (also called auto-configuration)
1 DoNotUse 1 N/A
0 INT Mask 1
Table 10. Interrupt
1 Detach 1 1: Accessory detached
0 Attach 1 1: Accessory attached
Table 11. Device Type 1 Table 12. Device Type 1
7 DoNotUse 1 N/A
6 Dedicated Charger
5 USB Charger (CDP) 1 1: USB charging downstream port (CDP) charger detected
4 Car Kit Type 1 & TA
2 Standard USB
Table 13. Dev ice Type 2
7 Unknown Accessory 1
3 JIG_UART_OFF 1 1: Factory mode BOOT -OFF-UART detected
2 JIG_UART_ON 1 1: Factory mode cable UART path with BOOT ON detected
1 JIG_USB_OFF 1 1: Factory mode cable USB path with BOOT OFF detected
0 JIG_USB_ON 1 1: Factory mode cable USB path with BOOT ON detected
Table 14. Manual S/W 1(15)
- Wh en switching between manual switch configurations on a single attach, the accessory must pass through an “000:
Open Switch” state between configurations. Manual M odes must have an accessory attached prior to operation. The FSA88x does not configure per the Manual Modes register if an accessory has not been previously attached. Table 15. Manual S/W 2
3 BOOT_SW 1 1: HIGH
2 JIG_ON 1 1: JIG output=GND (FSA880) or JIG output=HIGH (FSA881)
Table 16. Reset
0 Reset 1 1: Resets the FSA88x
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA880 / FSA881 • Re v. 1.0.7 23 FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection 10. Layout Guidelines 10.1. PCB Layout Guidelines for High-Speed USB Signal Integrity 1. Place FSA 88x as close to the USB controller as possible. Shorter traces mean less loss, less chance of picking up stray noise, and less radiated EMI. a) Keep the distance between the USB c ontroller and the device less than 25 mm (< one inch). b) For best results, this distance should be <18mm. This keeps it less than one quarter (¼) of the transmission electrical length. 2. Use an impedance calculator to ensure 90 Ω differential impedance for DP_CON and DM_CON lines. 3. Select the best transmission line for the application. a) For example, for a densely populated board, select an edge-coupled differential stripline. 4. Minimize the use of vias and keep HS USB lines on same plane in the stack. a) Vias are an interruption in the impedance of the transmission line and should be avoided. b) Try to avoid routing schemes that generally force the use of at least two vias: one on each end to get the signal to and from the surface. 5. Cross lines, only if necessary, orthogonally to avoid noise coupling (traces running in parallel couple). 6. If possible, separate HS USB lines with GND to improve isolation. a) Routing GND, power, or components close to the transmission lines can create impedance discontinuities. 7. Match transmission line pairs as much as possible to improve skew performance. 8. Avoid sharp bends in PCB traces; a chamfer or rounding is generally preferred. 9. Place decoupling for power pins as close to the device as possible. a) Use low-ESR capacitors for decoupling if possible. b) A tuned PI filter should be used to negate the effects of switching power supplies and other noise sources if needed. 10.2. Layout for GSM / TDMA Buzz Reduction There are two possible mechanisms for TDMA / GSM noise to negatively impact FSA88x performance. The first is the result of large current draw by the phone transmitter during active signaling when the transmitter is at full or almost-full power. With the phone transmitter dumping large amounts of current in the phone GND plane; it is possible for there to be temporary voltage excursions in the GND plane if not properly designed. This noise can be coupled back through the GND plane into the FSA88x device and, although the FSA88x has very good isolation; if the GND noise amplitude is large enough, it can result in noise coupling to the FSA88x. The second path for GSM noise is through electromagnetic coupling onto the signal lines themselves. In most cases, the noise introduced as a result is on the VBAT and / or GND supply rails. Following are recommendations for PCB board design that help address these two sources of TDMA / GSM noise. 1. Provide a wide, low-impedance GND return path to both the FSA88x and to the power amplifier that sources the phone transmit block. 2. Provide separate GND connections to PCB GND plane for each device. Do not share GND return paths among devices. 3. Add as large a decoupling capacitor as possible (≥1µF) between the VBAT pin and GND to shunt any power supply noise away from the FSA 88x. Also add decoupling capacitance at the PA (see the reference application schematic in Figure 22 for recommended decoupling capacitor values). 4. Add 33 pF shunt capacitors on any PCB nodes with the potential to collect radiated energy from the phone transmitter. 5. Add a series RBAT resistor prior to the decoupling capacitor on the VBAT pin to attenuate noise prior to reaching the FSA88x.
Figure 22. Reference Schematic Table 17. Reference Schematic Component Values (FSA880 ONLY) 100 k Ω Pull- up resistance for open-drain JIG pin. performance of high-speed USB path.
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