FSA831A ONSEMI | Alldatasheet

Document overview

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Technical content

Features

USB Battery Charging Rev. 1.2 Supports Data Contact Detect (DCD) Dead Battery Provision (DBP) w ith 30-Minute Timer Sw itch Type Isolation Sw itch Closes for Charging Dow nstream Port (CDP) Standard Dow nstream Port (SDP) VBUS 28 V Over-Voltage Tolerance -2 V Under-Voltage Tolerance Package 10-Lead MicroPak™ 1.6 x 2.1 mm, 0.5 mm Pitc h Ordering Information FSA831AL10X

Applications

 MP3, Mobile Internet Device (MID), Cell Phone, PDA, Digital Camera, Notebook and Netbook

Description

The FSA831A is a charger -detection IC w ith an integrated isolation sw itch for use w ith a micro/mini USB port. The FSA831A detects battery chargers and is compliant w ith USB Battery Charging Specification, Rev 1.2 (BC1.2). The algorithm incorporates Data Contact Detection (DCD), w hich ensures that the shorter, inner pins of the USB connector are making contact prior to continuing w ith battery charger detection. The device determines if a Dedicated Charging Port (DCP), Charging Dow nstream Port (CDP), or a typical PC host, called a Standard Dow nstream Port (SDP), is connected. If a charger is detected, the FSA831A determines w hether the charger is a DCP or CDP. For SDP and CDP detection, an internal isolation sw itch is closed to connect the D+/D - lines of the USB cable to the resident USB transceiver w ithin the portable device. The FSA831A conforms to all the constraints for the Dead Battery Provision (DBP) w ithin the BC1.2 specification, including a 30- minute timer that cannot exceed 45 minutes, per BC1.2. Typical Application Figure 1. Mobile Phone E xample

Figure 2. Pin Assignments (Top View) (LOW=charger not detected, HIGH=DCP or CDP charger has been detected) . Hi-Z=VBUS is not at a valid voltage).

3 DP_HOST

Table 1. Functionality outputs sw itch as in row s above.

  1. Hi-Z is the internal state of DM_CON. Since a DCP has been detect ed, DM_CON is shorted to DP_CON externally and

DM_CON is shorted to V DP_SRC.

  1. Proprietary charger s that leave DP_CON and DM_CON floating are detected as SDP. Proprietary charger s that force

resistances of the resistor dividers on DP_CON and DM_CON used to create the voltages on those pins.

www.onsemi.com FSA831A — USB2.0 High-Speed (480Mbps) Charger Detector with Isolation Switch Functional Description Data Contact Detect (DCD) DCD relies on the D+ and D- lines being present. DCD w aits until the internal timeout (tDCD_TIMEOUT) has expired in the follow ing cases:  If a charger does not have a D+ pin on the USB connector  If the D+ pin is not shorted to D - pin on the connector  If D+ is pulled up to a supply  If D+ does not have a sufficient path to ground to defeat a pull-up IDP_SRC (10 µA typical) current source. The FSA831A proceeds w ith charger detection even though it is unlikely a charger is present. If there is no charger, the algorithm reports an SDP and closes the sw itch. If a device is pulling D+ HIGH, this voltage present s itself to the USB transceiver or P hysical Layer Interface (PHY) block w ithin a System on Chip (SoC) after the sw itch is closed. If the DCD timeout w as insufficient and the PHY block is so equipped, DCD and the charging algorithm can be repeated in the PHY block . The stipulation is that the total time from V BUS valid to USB transceiver connect ion w ith a 1.5 kΩ pull- up to 3.3 V must be one ( 1) second, per USB 2.0 standards (USB 2.0 connect timing), provided the portable device does not have a dead battery. A typical PS /2 port (old PC mouse / keyboard port) has a resistive pull-up to V BUS. This can cause the DCD to exceed the maximum w ait time (tDCD_TIMEOUT) and proceed to charger detection. The likely path through charger detection is classifying the PS /2 port as an SDP port. This results in closing the USB sw itches, w hich causes the voltage on the DP_CON and DM_CON pins to pas s through the sw itch to DP_HOST and DM_HOST, respectively. Since voltages on the PS /2 port can go as high as the V BUS voltage, the DP_HOST and DM_HOST pins can be pulled up to V BUS. The USB PHY connected to DP_HOST and DM_HOST must be equipped to handle these higher voltages. CHG_AL_N Output and Output Timing CHG_AL_N output indicates that charge is allow ed to be draw n from V BUS w hen CHG_AL_N is LOW. When FSA831A first pow ers up and prior to detection, the CHG_AL_N pin can follow V BUS up to 28 V, w hich is the absolute maximum VBUS voltage allow ed. Whenever V BUS is at GND, the FSA831A is completely off and the sw itches and all I/Os are in the Hi -Z state. When V BUS climbs above the valid V BUS threshold, detection occurs automatically and CHG_DET, SW_OPEN, and CHG_AL_N all simultaneously sw itch to the states indicated in Table 1 if GOOD_BAT is HIGH (see Dead Battery Provision description for GOOD_BAT = LOW). Dead Battery Provision (DBP) BC1.2 and USB 2.0 allow a portable device (defined as a device w ith a battery) w ith a dead battery to take a maximum of 100 mA from the USB V BUS line for a maximum of 45 minutes as long as the portable device forces the D+ line to VDP_SRC (0.6 V typical). FSA831A starts detection w hen VBUS crosses the V BUSVLD threshold and, if it detects a CDP or SDP and GOOD_BAT is HIGH, automatically closes the sw itch and does not force the DP_CON pin to V DP_SRC. Once the charger detection is completed, the FSA831A starts a 30- minute timer and forces the DP_CON pin to VDP_SRC until the timer elapses. During the 30 minute period, if GOOD_BAT is LOW, V DP_SRC is applied to DP_CON and the D+/D- sw itches are opened, If GOOD_BAT is HIGH, VDP_SRC is not applied to DP_CON and the D+/D - sw itches are closed, If GOOD_BAT is LOW w hen 30 minute timer expires; regardless of w hether an SDP, CDP, or DCP w as previously detected; the FSA831A removes V DP_SRC f r om DP_CON and forces CHG_DET LOW and CHG_AL_N to Hi- Z (SW_OPEN remains Hi -Z) To exit this fault condition, remove V BUS, w ait for all the V BUS Printed Circuit Board (PCB) capacitance to discharge, and re- apply V BUS. Table 1 provides the functionality of the pins w hen the timer expires. When GOOD_BAT is HIGH and the battery is removed from the portable device w hile V BUS is valid, bringing GOOD_BAT LOW; the FSA831A opens the isolation sw itches on DP_CON and DM_CON and forces the DP_CON pin to VDP_SRC. In this scenario, the timer generally expires because the SoC does not have a supply to bring GOOD_BAT HIGH unless the battery that w as removed is re- inserted w ithin 30 minutes from w hen the USB plug is inserted. If an SDP or CDP is inserted w ith GOOD_BAT HIGH during the 30- minute timer, then GOOD_BAT changes to LOW; SW_OPEN changes to Hi -Z and the counter continues counting until the 30 minutes expires. If GOOD_BAT t hen returns to HIGH, SW_OPEN changes to LOW and finishes out the 30-minute time. GOOD_BAT has an internal pull -dow n resistor to ensure it is LOW w hen the SoC is pow ered dow n. This input is designed to have very low thresholds to interface w ith low-voltage SoCs driven w ith 1.2 V supplies. Proprietary Chargers Only legitimate USB chargers that force V DM_SRC (0.6V typical) on DM_CON w hen V DP_SRC is applied to DP_CON are detected by the FSA831A and cause CHG_DET signal to be asserted. Any charger that forces a HIGH on both DP_CON and DM_CON can be detected as CDP, DCP, or SDP (depending on the resistances of the resistor dividers on DP_CON and DM_CON) and used to create the HIGH voltages on thos e pins. Any charger that lets both DP_CON and DM_CON signals float is detected as an SDP and CHG_DET stays de-asserted. In cases w here the proprietary charger is detected as an SDP or CDP, since the sw itches are closed and access is made from the USB connector D+ and D - lines to the USB PHY block; the chargers can be detected w ithin the PHY if so equipped Ground Drops When a DCP is detected, V DP_SRC is forced on DP_CON provided GOOD_BAT is HIGH or if GOOD_BAT is LOW and the DBP timer has not expired. For cu rrent up to 1.5 A flow ing into the V BUS and GND lines of the USB cable, this can translate to substantial ground drops that lift the ground of the portable device. This drop adds to the voltage at the DP_CON pin as seen from the DCP D+ pin. For the max imum ground drop of 375 mV specified in the BC1.2 specification and for the maximum V DP_SRC of 0.7 V, the

detach detection need to take this int o account. this voltage and prepares the FSA831A for charger detection. VBUS voltages up to 28 V can be tolerated by the V BUS pin. charger is plugged in backw ards. achieves battery charger detection consistent w ith BC1.2.

  • If VBUS<VBUSVLD, FSA831A powers down.
  • D+ is the DP_CON pin.
  • D- is the DM_CON pin.
  • When SW_OPEN=Hi-Z, switches are open.
  • When SW_OPEN=L, switches are closed. CHG_AL_N=L, CHG_DET=H SW_OPEN=Hi-Z CHG_AL_N=L, CHG_DET=H CHG_AL_N=L, CHG_DET=L SW_OPEN=L, Remove VDP_SRC on D+ SW_OPEN=Hi-Z, CHG_AL_N=Hi-Z, CHG_DET=L, Remove VDP_SRC on D+ tDBP SW_OPEN=Hi-Z D+=VDP_SRC GOOD_BAT=H GOOD_BAT=L Wait for VBUS < VBUSVLD NOT tDBP NOT tDBP NOT tDBP tDBP GOOD_BAT=H tDBP GOOD_BAT=L

Figure 3. Battery Charger Detection

www.onsemi.com FSA831A — USB2.0 High-Speed (480Mbps) Charger Detector with Isolation Switch Absolute Maximum Ratings Stresses ex ceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VBUS Voltage from USB Connector -2 28 V VSW USB Sw itch I/O V oltage (DP_CON, DM_CON, DP_HOS T, DM_HOS T) -0.5 6.0 V ISW USB Sw itch Current (DP_CON to DP_HOS T, DM_CON to DM_HOS T) -30 +30 mA VI/O Voltage from GOOD_BAT, CHG_AL_N, CHG_DET and SW_OPEN I/Os -0.5 6.0 V VCA Voltage from CHG_AL_N Output -0.5 28.0 V II/O CHG_AL_N, CHG_DET and SW_OPEN Outputs Sink/Source Current -5 +5 mA TSTG Storage Temperature Range -65 +150 °C TJ Maximum Junction Temperature +150 °C TL Lead Temperature (Soldering, 10 Seconds) +260 °C ESD IEC 61000-4-2 System USB Pins (DP_CON, DM_CON, V BUS) Air Gap 15 kV Contact 8 Human Body Model, JEDEC JESD22-A114 All Pins 6 Charged Device Model, JEDEC JESD22-C10 1 All Pins 1 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VBUS VBUS Input HIGH Voltage 4 6 V VSW Sw itch I/O Voltage for USB Path 0 3.6 V TA Operating Temperature -40 +85 ºC

www.onsemi.com FSA831A — USB2.0 High-Speed (480Mbps) Charger Detector with Isolation Switch Unless otherw ise indicated, VBUS=4 V to 6 V and TA=-40 to +85°C. Typical values are at T A=25°C unless otherw ise specified. Symbol Parameter Condition Min. Typ. Max. Unit Status Outputs VOHCD Output HIGH Voltage (CHG_DET) IOH=-2 mA 2.0 V VOL Output LOW Voltage (CHG_DET, CHG_AL_N, SW_OPEN) IOL=2 mA 0.4 V tDIFF Skew Betw een Any Output (CHG_DET, CHG_A L_N, SW_OPEN) Sw itching Relative to the Other Outputs Sw itching II/O=±2 mA , CHG_AL_N=20 kΩ to 5 V, SW_OPEN=10 kΩ to 1.8 V 100 ns VBUS Pin VBUSVLD VBUS Valid Detection Threshold(1) 0.8 4.0 V IBUSIN VBUS Input Leakage VBUS=0 V to 0.8 V 3 µA IVBUSACT VBUS Active Mode Average Current USB Path Active , USB Sw itch Closed After Charger Detection 250 µA tOUT Time f r om VBUS Valid Asserted to CHG_DET, CHG_AL_N and SW_OPEN Outputs Valid DP_CON pulled dow n to GND, 15kΩ, all voltages forced on VBUS, DP_CON, DM_CON and GND simultaneously 250 ms Sw itch Characteristics IOFF Pow er Off Leakage Current USB Path V BUS=0V, VSW=0 V or

3.6 V, Figure 5 10 µA

RONUSB High-Speed USB Range Sw itch On Resistance(1) VDP_CON / VDM_CON=0V, 0.4 V; ION=8 mA; Figure 4; VBUS=4 V to 6 V 4.5 6.5 Ω Control Input VIH Input HIGH Voltage (GOOD_BAT) 1.1 V VIL Input LOW Voltage (GOOD_BAT) 0.5 V RPD Pull Dow n Resistance (GOOD_BAT) 1 MΩ IIN Input Leakage Current (GOOD_BAT) VBUS=5 V, GOOD_BAT=0 V to 4.4 V 10 µA IIOFF OFF State Leakage Current (GOOD_BAT) VBUS=0 V, GOOD_BAT=0 V to 4.4 V 10 µA tDBP Dead Battery Provision (DBP) Timer 15 30 45 min tGB Time from GOOD_BAT Asserted to SW_OPEN De -Asserted, Sw itches Closed and Meet the RONUSB Specification 30 ms tDB Time f rom GOOD_BAT De-asserted to SW_OPEN Asserted, Sw itches Opened 65 ms Battery Charger Detection Parameters from BC1.2 Specification VDAT_REF Data Detect Voltage 0.25 0.40 V VDM_SRC D- Source Voltage(2) 0.5 0.7 V VDP_SRC D+ Source Voltage(2) 0.5 0.7 V VLGC Logic Threshold 0.8 2.0 V IDM_SINK D- Sink Current 25 175 µA IDP_SINK D+ Sink Current 25 175 µA IDP_SRC Data Contact Detect Current Source 7 13 µA tDCD_DBNC Data Contact Detect Debounce 10 ms tDCD_TOUT Time for DCD to Timeout 300 450 900 ms tVDPSRC_ON D+ Voltage Source On Time 40 ms tVDMSRC_ON D- Voltage Source On Time 40 ms N otes: 1. Guaranteed by characterization; not production tested. 2. The voltage source, V DP_SRC / VDM_SRC, is able to source at least 250 µA w hen the output voltage is in the specified range. This voltage source should not pull DP_CON / DM_CON below 2.2V w hen DP_CON / DM_CON is pulled to a voltage of 3.0 V minimu m or 3.6 V maximum w ith a resistance of 900 Ω minimum or 1575 Ω max imum.

www.onsemi.com FSA831A — USB2.0 High-Speed (480Mbps) Charger Detector with Isolation Switch Unless otherw ise specified, values are at TA=-40 to +85°C; a ll typical value s are for V CC=3.3 V at TA=25°C. Symbol Parameter Condition Min. Typ. Max. Unit Figure Xtalk Active Channel Crosstalk, DP_CON to DM_CON(3) f=1 MHz , RT=50 Ω, CL=0 pF -78 dB Figure 7 f=240 MHz , RT=50 Ω, CL=0 pF -36 OIRR Off Isolation Rejection Ratio, DM_HOS T to DM_CON, DP_HOS T to DP_CON(3) f=1 MHz , RT=50 Ω, CL=0 pF -84 dB Figure 6 f=240 MHz , RT=50 Ω, CL=0 pF -34 BW Bandwidth of Switch RT=50 Ω 1.7 GHz Figure 7 Note : 3. Guaranteed by characterization; not production tested. Capacitance Unless otherw ise specified, values are at TA=-40 to +85°C. Symbol Parameter Condition Typical Unit Figure COFF DP_CON, DM_CON Of f Capacitance(4) VBIAS=0.2V, f=1MHz 3.2 pF Figure 8 CON DP_CON, DM_CON On Capacitance(4) VBIAS=0.2V, f=1MHz 5.8 pF Figure 9 Note : 4. Guaranteed by characterization; not production tested.

Figure 10. 10-Lead, MicroPak™ warranty therein, which covers ON Sem iconductor products. REGISTRATION MO-255, VARIATION UABD . B. DIMENSIONS ARE IN MILLIMETERS. E. DRAWING FILENAME: MKT-MAC10Arev5.

0.10 C A B

0.55 MAX

1.62 KEEPOUT ZONE, NO TRACES

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